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Basic use of IC Compiler II (ICC II) - Programmer Sought

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1/28/22, 11:15 PM
Basic use of IC Compiler II (ICC II) - Programmer Sought
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Basic use of IC Compiler II (ICC II)
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Content
Article Directory
Content
Blocks and Design Libraries
Objects
Attributes of Objects
Application Options(App Options)
Finding/Applying Application Options
IC Compiler II GUI
Built-In Script Editor
Design Setup
Overview
IC Compiler II Library Manager
Library Manager(icc2_lm_shell) Flow
Library Prep-icc2_lm_shell
APR Flow - Design & Timing Setup
Create a “Container”: The Design Library
Read the Netlist and Create a Design
Multiple Modes and Corners
Concurrent MCMM Optimization
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Mode, Corner and Scenario Setup
Loading Constraints
Defining PVT Directly - Recommended
Specify TLUplus Parasitic RC Models
Controlling Scenario Analysis / Optimization
APR Flow - Floorplan Definition
Floorplanning Overview
Create the Initial Floorplan
Place Macros and Standard Cells
Place I/O Pins
Power Planning Challenges
Pattern_Based Power Network Synthesis
Write out the Floorplan for ICC II/DC-G
APR Flow - Placement & Optimization
Key Steps of the Placement Phase
Design and Flow Requirement Setup Steps
Congestion-Focused Setup Steps
The Five Stages of placve_opt
Placement and Logic Optimization:place_opt
Recommended place_opt Exploration Flow
Example Script
APR Flow - CTS & Optimization
Clock Tree Synthesis Goal and Flows
Comparing Classic CTS versus CCD
Clock Tree Balancing Setup
Non-Default Rules
Defining/Applying NDR
Defining CTS-Specific DRC Values
CTS Execution
Analyzing CTS Results: Clock QoR Report
Analyzing CTS Results: Clock Timing Report
Example Script
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APR Flow - Routing & Optimization
Routing Phase Goal
Recommended Routing Flow
Check Zroute DRC Violations
Example Script
APR Flow - Signoff
Signoff
Prime Time Signoff-driven Physically Aware ECO Flow
Function ECO Flow
Standard Cell Fillers and Metal Fill
Filler Insertion & Removal
In-Design Signoff DRC Checking and Fixing
Signoff DRC using IC Validator
Metal Fill Insertion
Customer Support
Solvnet
Regerence Flow
NDM
block library
New infrastructure
Multi-level physical hierarchy
Scalable Timer
Parallel optimization
preroute optimization
main feature
Fusion with redhawk
Fusion with StarRC & PT/PX
Fusion with ICV
other fusion
PT StarRC reads ICCII DataBase directly
Reference
Blocks and Design Libraries
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Block is the carrier of all design data, create a block for the netlist
Some commands for block are named *_block, such as open_block, save_block
1
1. read_verilog
2
2. open_block
save_block
3
3. create_lib
open_lib
save_lib
Objects
1
1. get_*
2
2. help_attributes
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Attributes of Objects
Every object has attributes, and attributes have values
1
1. report_attributes -application [get_selection]
Application Options(App Options)
SPG: Synopsys Physical Guidence, use the back-end physical floor plan information to
synthesize, highlight some problem information, and use it for the back-end process
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1. place_opt.flow.do_spg
2
2. category.sub_category.option_name
Finding/Applying Application Options
1
1. report_app_options
get_app_options
2
2. report_app_options time.* (Report Timing related app_options)
3
3. report_app_options -non_default (usually the default value, this comm
4
4. set_app_options -name time.remove_clock_reconvergence_pessimism -valu
IC Compiler II GUI
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Built-In Script Editor
Design Setup
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Overview
Design Library includes Block, Cell Libraries (ndm format), Technology Library
(ndm format)
Block includes Gate-Level Netlist (gate-level netlist) and some files of Design
constraints
IC Compiler II Library Manager
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ndm is generated using an ICC II Library Manager
For some standard units/memory/IP/IO used in all design, you need to know
Timing information (.db file)/physical information (.frame/LEF/GDS)/technical files
Generate NDM through ICC II Library Manager, NDM contains logic/physical
information, and then use it in ICC II
Library Manager(icc2_lm_shell) Flow
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Library Prep-icc2_lm_shell
A simple script,
1
1. create_workspace needs to specify a name and the required tech file
2
2. read_db
3
3. check_workspace
4
read_lef
4. commit_workspace save ndm
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APR Flow - Design & Timing Setup
With ndm, design & timing setup can be carried out
Create a “Container”: The Design Library
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create of design library:
1
2
1. Specify technology and some cell library (cell is ndm)
2. The default library is stored in memory
Read the Netlist and Create a Design
Read netlist to generate block
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Multiple Modes and Corners
The current chip will operate in many modes and different corners
Concurrent MCMM Optimization
Because of the different application scenarios, these modes and corners are
combined to form a scenario, that is, scenario, scene
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IC can be optimized in different scenarios at the same time
Mode, Corner and Scenario Setup
First define mode and corner, then mode and corner are combined together to
form scenarios
1
create_mode M1
2
create_mode M2
3
create_corner C1;
4
5
create_scenario -mode M1 -corner C1 -name M1_C1
6
create_scenario -mode M2 -corner C2 -name M2_C1
Loading Constraints
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After getting the scenarios, you need to read in some constraint files
1
current_scenario M1_C1
current_scenario M2_C1
2
read_sdc C1_corner.sdc
read_sdc M2_mode.sdc
3
read_sdc M1_mode.sdc
read_sdc M2_C1_scenario.sdc
4
read_sdc M1_C1_scenario.sdc
5
6
read_sdc global_constraints.sdc
Defining PVT Directly - Recommended
For each scenario to specify the corresponding process/voltage/temperature
It is recommended to use this direct assignment method for assignment
Specify TLUplus Parasitic RC Models
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Bring in the parasitic parameter extraction model
For each corner, read in the TLUplus file corresponding to the corner
TLUplus can be read in from the ndm in the previous tech library, or specified in
the subsequent design library
1
set_parasitic_parameters -corner c_slow -library $(techlib) -early_spec m
2
set_parasitic_parameters -corner c_fast -library $(techlib) -early_spec m
Controlling Scenario Analysis / Optimization
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1
create_scenario
2
set_scenario_status
Basic use of IC Compiler II (ICC II) - Programmer Sought
APR Flow - Floorplan Definition
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Floorplanning Overview
Defining
Defined size and shape
The shape and location of the voltage domain
Macro's location
I/O pin location
In order to avoid congestion, some standard unit blockages may be used
Generate power network PNS
Write out the floor
Create the Initial Floorplan
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To define the size, use: initialize_floorplan
Place Macros and Standard Cells
Put both the macro and standard units in
1
2
create_placement -floorplan [-congestion]
set_fixed_objects fix hard_macro before place_opt
Place I/O Pins
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I/O Pins need to be placed after macro placement
Usually when placing the macro, he will be placed next to the block, but
sometimes it will block the macro
When placing pins, you need to pay attention. Sometimes there will be some
interactions between blocks, so there may be restrictions on the placement of pin
blocks; or there are some special requirements for the placement of special pins,
such as signal pins, clocks, and differential signal pins. , If required, you need to
read it in before placing the pins, and use place_pins -self to place all the pins in
the correct position.
1
set_block_pin_constraints
2
place_pins -self
Power Planning Challenges
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Build a power network
Pattern_Based Power Network Synthesis
First define an area to it
Define power grid structure: level, line width, distance between lines
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Put the pattern in the PG region, and apply it to the voltage area or bounds at the
same time. You need to specify which nets to play, such as VDD, VSS, etc.; the
advantage of this is that there will be no fixed coordinates in the whole process.
When floorplan When there are some changes in the future, it is very flexible, and
there is no need to manually change these values
compile power network
Write out the Floorplan for ICC II/DC-G
Write down the floorplan information, if you need to re-run the ICC, you can quote
the previously saved information
If it is sent to the front-end synthesis, there is no need to include the placement of
standard units. DC will reconsider the placement of macros during synthesis.
1
write_floorplan -output ORCA_TOP.fp
2
write_floorplan -format icc -output ORCA_TOP.fp.dc -net_types {power grou
APR Flow - Placement & Optimization
TOP
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Key Steps of the Placement Phase
Design and Flow Requirement Setup Steps
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Specify scenario to optimize
Choose whether to open SPG Flow, SPG is to generate an initial position
information after the previous DCG synthesis, ICC II can directly use this
information to make the following optimization
remove unwanted ideal networks
Specify a specific type of library cell to use
Choose whether to optimize leakage or dynamic or total optimization of
leakage+dynamic
Congestion-Focused Setup Steps
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QoR is mainly divided into three parts: Congestion/Timing/Power
Congestion
Analyze congestion and cell/pin density after running place_opt
If there is a congestion problem, you can use the following methods to solve
congestion
Timing
Power/Area
The Five Stages of placve_opt
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initial_place/initial_drc/iniitial_opto/final_place/final_opto
Placement and Logic Optimization:place_opt
place_opt will run through five stages directly by default
You can use the -from/-to control phase to improve efficiency
Can be controlled by app options: congestion/timing, etc.
Recommended place_opt Exploration Flow
TOP
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Example Script
APR Flow - CTS & Optimization
TOP
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Clock Tree Synthesis Goal and Flows
Comparing Classic CTS versus CCD
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Classic CTS does not look at the data path, only whether the tree between the clk
entry point and each reg point is flat, reducing skew deviation
The data path is in an untouched state during optimization
The clock tree may be moved during CCD optimization, but Classic CTS will not
Clock Tree Balancing Setup
TOP
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1
# Set clock tree balance
2
set_clock_balance_points
Basic use of IC Compiler II (ICC II) - Programmer Sought
3
4
5
# Specify the expected delay and the deviation between each other
set_clock_tree_options
6
7
# Control which cell CTS chooses
8
set_lib_cell_purpose -include cts $cts_cells
9
set_dont_touch $cts_cells false
10
11
create_clock_balance_group
12
13
derive_clock_balance_constraints -slack_less_than -0.3
Non-Default Rules
Defining/Applying NDR
TOP
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create_routing_rule
2
set_clock_routing_rules
Basic use of IC Compiler II (ICC II) - Programmer Sought
Defining CTS-Specific DRC Values
1
set_max_transition <value> -clock_path [all_clocks]
2
set_max_capacitance <value> -clock_path [all_clocks]
3
4
set_max_transition 0.2 -clock_path -scenarios "S1 S4" [get_clocks SYS_CLK
TOP
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CTS Execution
Analyzing CTS Results: Clock QoR Report
Analyzing CTS Results: Clock Timing Report
TOP
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Example Script
APR Flow - Routing & Optimization
TOP
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Routing Phase Goal
Recommended Routing Flow
TOP
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Check Zroute DRC Violations
Example Script
TOP
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APR Flow - Signoff
Signoff
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Mainly do some Timing ECO or some Functional ECO
Prime Time Signoff-driven Physically Aware ECO Flow
Function ECO Flow
TOP
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There may be bugs in the design design, and some problems will also occur in
the post-imitation. We need to make some corrections, and will not restart from
the synthesis. We often use ECO to solve them.
First compare, write the changed things; then apply change, put the eco cell in it;
finally make an eco route
Standard Cell Fillers and Metal Fill
TOP
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Filler Insertion & Removal
In-Design Signoff DRC Checking and Fixing
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Signoff DRC using IC Validator
Metal Fill Insertion
TOP
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Customer Support
Solvnet
TOP
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Regerence Flow
NDM
Timing View can be understood as db, including timing information and power
consumption information
TOP
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Design view is equivalent to design, such as block, the design itself has the result
of winding and place
frame view and lef are the same
block library
block library can also be understood as ndm
The abstract view is more important. It is a simplified design view. The abstract
view is used when the top is implemented, which extracts the physical information
of the interface and the physical information on the clock tree.
New infrastructure
TOP
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The library manager is a tool for generating ndm
Multi-level physical hierarchy
If you don’t support multi-level physical hierarchy, you have to parallelize it, and
you can include it if you support it.
TOP
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Scalable Timer
Timer can perform timing operation
ICCII is based on mode rather than scenario. The library corresponding to a mode
has different voltage/temperature/process, so that different PVT can be
interpolated, thereby adding more flexibility
Parallel optimization
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preroute optimization
The first is place, there is an early clock after the place, that is, an early CTS, the
purpose is to consider the influence of the clock on the winding and the area of ​
the clock cell/clock buffer in the place stage; if the IC is optimized, it is impossible
to know the ICG The slack, because you did not make a tree, that is, early clock is
to make an initial tree to estimate the timing of the ICG, and then optimize it;
therefore, the early clock needs to be enabled in the place stage so that the time
after the timing is completed Very match
TOP
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The timing after place can be consistent with the timing after cts.
main feature
Fusion with redhawk
Fusion with StarRC & PT/PX
TOP
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Fusion with ICV
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other fusion
PT StarRC reads ICCII DataBase directly
TOP
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Reference
Synopsys Online Course: IC Compiler
Jishu dry goods|Mount-a new generation of layout bus system IC Compiler II first acquaintance
(PPT download + video playback)
Copyright Complaint
Spam Report
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Take the last Microsoft portable compiler Daquan I
MSVC_QUICKCPP Download Extraction code: 8888 Usually
need to temporarily modify the number of changes in the code
sometimes because the compiler is d...
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ICC II official tutorial notes 3 start design s
etup from create_ndm
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model is used in ICC II; the new data model Introduce the
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Implement a basic calculator to calculate a simple string expression. The string
expression contains only non-negative integer, +, -, *, / four operands and spaces.
Integer division retain only the in...
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Write permissions, build packages, and guide dependencies.
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I. NIO Foundation - Netty Learning Road
、
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、
static_cast dynamic_cast reinterpret_cast const_cast
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