22nm FD-SOI Technology with Back-biasing Capability Offers
Excellent Performance for Enabling Efficient, Ultra-low Power Analog
and RF/Millimeter-Wave Designs
S.N. Ong#1, L.H.K. Chan#, K.W.J. Chew#, C.K. Lim#, W. L. Oo#, A. Bellaouar^, C. Zhang^,
W.H. Chow#, T. Chen^, R. Rassel^, J.S. Wong#, C.W.F. Wan#, J. Kim#, W.H. Seet#, D. Harame%
#
GLOBALFOUNDRIES Singapore
^
GLOBALFOUNDRIES USA
%
now with Research Foundation State University Polytechnic at Albany, USA
1
shihni.ong@globalfoundries.com
transistor using a pair of GSGSG probes, as illustrated in Fig.
1 (a). DC current and S-parameters were characterized using
the CASCADE RF probe station together with Keysight’s
PNA and B1500 DC parametric analyzer. Calibration was
performed with the Short-Open-Load- Reciprocal thru (SOLR)
method [5], to eliminate the parasitic down to probe tips.
Abstract—This paper addresses the impact of back-gate
biasing to DC, RF/millimeter-Wave (mmWave) and high
frequency (HF) noise in 22nm FD-SOI technology
(GLOBALFOUNDRIES’ 22FDX® technology). The front-gate
and the back-gate cut-off frequency fT, together with the
maximum oscillation frequency fMAX, were extracted from the
four-port S-parameters data. The maximum achieved frontgate/back-gate fT and fMAX for the NFET is 350/85 GHz and
370/23 GHz respectively. In addition, 22FDX® technology
demonstrated a tuneable HF noise parameter by using the backgate biasing to achieve best-in-class low noise level. Two frontend (FE) modules were presented, which exploit the unique
feature of back-gate. This unique feature allows superior designs
with excellent combination of performance, power consumption
and development cost, for emerging applications such as IoT,
Telecommunication UE, RF and mmWave circuits with high
speed connectivity and networking.
Keywords— mmWave, RF, noise figure, 22FDX®, FDSOI,
four-port, back-gate.
Fig. 1. Layout view of: (a) a 4-port transistor, with GSGSG probes; (b) a 3port transistor, with GSG probes and DC needle with ferrite bead.
I. INTRODUCTION
FD-SOI technology exhibits excellent RF/mmWave
performance with high cut-off frequency fT and maximum
oscillation frequency fMAX [1]. The technology has low
parasitic to the substrate and low gate resistance. This
technology has a unique “second-gate” feature called the
back-gate, due to an ultra-thin buried oxide (BOX) between
the main gate and body substrate that allows designers to
adjust the back-gate biasing for different kind of circuits
optimization [1-3].
This paper evaluates the impacts of back-gate bias on the
DC, RF/mmWave and HF noise figure-of-merit (FoM) using
GLOBALFOUNDRIES’ 22FDX® technology. It is presented
for the first time that the noise figure and noise resistance is
improved under forward body-bias (FBB), with positive backgate bias for NFET, in contrary to [4]. In section IV, two
front-end modules, i.e., 28GHz stacked Power Amplifier (PA)
and SPST switch are presented to demonstrate the unique
feature of the back-gate.
B. Four-Port De-embedding Methodology
Four-port Open-Short de-embedding method has been
implemented to eliminate the parasitic of the GSGSG pad
frame down to M1 reference plane. 4-port S-parameters of
DUT (SDUT), OPEN (SOP) and SHORT (SSH) structures were
converted to Y-parameters (YDUT, YOP, YSH) using (1), with E is
a 4-by-4 identity matrix.
(1)
The shunt admittance and the series impedance parasitic
were removed using (2)-(3).
;
(2)
_
_
(3)
_
_
Lastly, Zdeem was converted to Sdeem, the de-embedded Sparameters of the transistor, using (4).
(4)
C. HF Noise Characterization
The impact of the back-gate bias to front-gate HF noise
was evaluated by measuring a 3-port transistor using a pair of
GSG probes with an additional DC needle with ferrite bead,
for reason to prevent measurement oscillation, as illustrated in
Fig. 1 (b). Four noise parameters were measured using MPI
II. ON-WAFER CHARACTERIZATION
A. DC/RF Characterization
The impact of the back-gate bias to front-gate DC/RF
characteristics has been investigated by measuring a 4-port
PREPRESS PROOF FILE
1
CAUSAL PRODUCTIONS
Prober TS3000, with Focus Microwave iCCMT-67100 tuner,
Agilent PNA-X N5247A Noise Module, Agilent SMU B1500,
Agilent Noise source 346CK01, and Miteq LNA JDM2126505000-45-20P. Open-Short noise de-embedding was
performed, followed by extraction of the drain/gate noise
power spectral density (Sid, Sig) and de-embedding of fournoise parameters [6].
III. BACK-GATE MODELING AND IMPACT TO FRONT-GATE AND
BACK-GATE FOM
A. Transistor Cross Section View and Operation
Fig. 3. DC characteristic versus gate and drain bias, of NFET and PFET, with
(a) Id-Vg, (b) Gm-Vg, (c) Id-Vd, and (d) Gds-Vd.
Fig. 2. Cross sectional view of the transistor with illustration of parasitic at the
front-gate and back-gate [1].
The cross sectional view of the 22FDX® n-type flippedwell transistor with parasitic resistances, capacitances and
diode are illustrated in Fig. 2 [1]. The back-gate bias is applied
through the back-gate ring, which served as a “second-gate”
for channel control.
Fig. 4 FG and BG cut-off frequency of NFET, with (a) fT-Vg, (b) fT*gM/Id -Vg,
(c) fT-Jd, and (d) fT*gM/Id -Jd.
B. DC Characteristic
The DC drain current Id, transconductance Gm and output
conductance Gds at different back-gate biases of |Vbg|=0, 2, for
NFET and PFET, are shown in Fig. 3. It shows that lower
threshold voltage Vt can be achieved by simply applying a
back-gate bias |Vbg|>0 to the transistor, under FBB condition.
Higher drain saturation current Idsat, higher output conductance
Gds and lower resistance Ron can be achieved as well with
|Vbg|>0. Circuit designers are able to optimize their circuit to
have either low power consumption at |Vbg|=0, or high speed
operation with low Ron using |Vbg|>0. This is the unique
feature of 22FDX®.
C. RF/mmWave Characteristic
By defining port 1 as front-gate, port 2 as drain, port 3 as
back-gate and port 4 as source, the front-gate (FG) and backgate (BG) cut-off frequency fT and maximum oscillation
frequency fMAX can be extracted from Y-parameters, using
equations (5) to (8).
Mag(
)
freq;
@10GHz (5)
Mag(
)
freq;
@10GHz (6)
Fig. 5 FG and BG maximum oscillation frequency of NFET, with (a) fMAX-Vg,
(b) fMAX*gM/Id -Vg, (c) fMAX-Jd, and (d) fMAX*gM/Id -Jd.
2
Fig. 6 FG and BG performance of PFET, with (a) fT-Vg, (b) fT*gM/Id -Vg, (c)
fMAX-Vg, and (d) fMAX*gM/Id -Vg.
Mag
_
|
(
)
(
(
)
Mag
_
(
)
|
(
freq;
_
|
)
)
(
)
@30GHz
)
Table 1. NFET and PFET FoMs
(7)
|Idsat|
(uA/um)
Ron
(Ohm-mm)
Peak fT
(FG/BG)
(GHz)
Peak fMAX
(FG/BG)
(GHz)
NF50 (dB)
@26GHz
freq;
_
|
(
Fig. 7 HF noise FoM of NFET, with (a) Sid-Vg, (b) Rn -Vg, (c) NFmin-Vg, and (d)
NF50 -Vg.
(
)
@30GHz
(8)
The FG and BG RF/mmW FoM, which are fT, fMAX, and
their product with gain efficiency fT*gM/Id and fMAX*gM/Id, of
NFET and PFET, at different back-gate biases of |Vbg|=0, 2,
are illustrated in Figs. 4-6. It is observed that the peak of FG
and BG fT, fMAX and their product with gain efficiency has
shifted to lower Vg when |Vbg| changes from 0 to 2V, for NFET
and PFET. These FoMs peak at the same current density Jd,
regardless of |Vbg| being 0 or 2V. This indicates that, circuit
designers are able to either obtain higher RF/mmW FoM at
lower Vg and Vbg>0V for high speed design, or getting the
similar RF/mmW FoM at same current density for low power
design. The unique feature of FD-SOI provides another degree
of freedom in circuit design, which enabled the designers to
optimize their circuit in the desired operating region.
NFET @
|Vbg|=0V
NFET @
|Vbg|=2V
PFET @
|Vbg|=0V
PFET @
|Vbg|=2V
819
1036
597
773
0.356
0.313
0.369
0.306
350 /85
343/83
244/73
244/73
370/23
343/29
277/9
270/11
4.3
4.5
-
-
The NFET and PFET FoMs with different back-gate biases
are summarized in Table 1. 22FDX® demonstrated better
RF/mmWave performances as compared to other technology
nodes such as bulk CMOS, PDSOI and FinFET, as shown in
[1].
IV. MMWAVE CIRCUITS
The back-gate control adds a new dimension to mmWave
circuit performance. There are two types of back-gate control
in a circuit; one with low impedance to the back-gate bias and
the other with high impedance. The former is also called static
control where the threshold voltage of the device is controlled.
The latter is also called AC floating back-gate bias (AFBG) in
which the back-gate bias is done through a high-impedance
(high resistor). In this case the drain/source to bulk
capacitance is reduced.
Two examples are shown for the AFBG type. The first
example is a power amplifier (PA), with the schematic using
the AFBG concept is shown in Fig. 8. Performance
comparison of the PA with and without back-gate is shown in
Table 2. The results clearly show a boost in PAE by 4.7% and
Pout improvement of 0.4 dBm.
D. HF Noise Characteristic
HF noise FoM at 26 GHz versus Vg with different backgate biases of |Vbg|=0, 2, of NFET, is shown in Fig. 7, with (a)
drain current noise Sid, (b) normalized noise resistance Rn, (c)
minimum noise figure NFmin, and (d) noise figure terminated
at 50 Ohm source resistance NF50. With lower Vt and higher
drain current Id for Vbg=2V, the intrinsic drain current noise
Sid is higher. In spite of this, the higher Gm at lower Vg at
Vbg=2V causing the Rn to be lower, and thus lower NFmin
and NF50 as well. 22FDX® allows tuneable of HF noise
parameter using back-gate bias Vbg. With Vbg>0V, lower
noise figure and noise resistance can be achieved at low Vg
regime, which is beneficial for circuit such as LNA.
3
Another example is the SPST switch insertion loss where
the AFBG concept is used on the n-well of the super-low Vt
(SLVT) transistors of 3 stacked devices [1, 7]. Fig. 9 shows
the insertion loss (IL) versus frequency of the SPST switch.
The floating BG exhibits a flatter frequency response
especially with high BG bias (3V).
V. CONCLUSION
The impact of back-gate biasing to DC, RF/mmW and HF
noise of 22FDX® technology has been described. Applying
forward back-gate bias has shown to reduce the threshold
voltage, while increasing the drain saturation current Idsat with
higher output conductance Gds thus lower resistance Ron. The
peak fT, fMAX of FG and BG and their gain efficiency product
has shifted to lower Vg with the peak values remain almost the
same, when the back-gate bias increased. Besides, lower Rn,
NFmin and NF50 can be achieved at low Vg with forward backgate bias. The front-gate/back-gate achieved performance of
the NFET for fT is 350/85 GHz and for fMAX to be 370/23 GHz.
Dynamic back-gate biasing enables active trade-off of
performance versus power. A 28GHz stacked Power
Amplifier (PA) has been presented, achieving 19.2 dBm Psat,
12.7 dB Gain and 42.9% PAE. A SPST switch with improved
IL versus frequency response has been demonstrated using AC
floating back-gate with DC back-gate bias.
REFERENCES
[1] S. N. Ong, et. al., “A 22nm FDSOI Technology Optimized for
RF/mmWave Applications,” in Proc. IEEE RFIC Symposium,
Philadelphia, PA, June 2018, pp. 72-75.
[2] J. C. Barbé, et. al., “4-port RF performance assessment and compact
modeling of UTBB-FDSOI transistors,” in Proc. IEEE RFIC
Symposium, Phoenix, AZ, 2015, pp. 355-358.
[3] B. Kazemi, et. al., "Back-gate bias effect on FDSOI MOSFET RF
Figures of Merits and Parasitic Elements", Proceeding ULIS, 2017.
[4] H.Su, H.Wang, T.Xu R.Zeng, “Effects of Forward Body Bias on HighFrequency Noise in 0.18-um CMOS Transistors,” IEEE Trans. on
Microwave Theory And Techniques, Vol. 57, No. 4, April 2009.
[5] “Making Accurate and Reliable 4-Port On-Wafer Measurements”,
Cascade Microtech, Inc. App. Note 1-4.
[6] C. H. Chen, et. al., “Extraction of the induced gate noise, channel
thermal noise and their correlation in sub-micron MOSFETs from RF
noise measurements,” in Proc. ICMTS., Kobe, Japan, 2001, pp. 131–
135.
[7] A. Bellaouar (June 2018). Millimeter-Wave Circuit Design and
Techniques in FDSOI CMOS Technology, Workshop presented at
RFIC2018, Philadelphia, PA.
Fig. 8. Stacked PA Circuit Configuration (Common Sources are SG-types and
the Cascode are EGU).
Table 2. PA Performance Comparison with/without Floating BG
2-Stack
SG-EGU
(No AFBG) #1
SG-EGU
(AFBG) #2
VDD (V)
2.0
2.0
VBB (V)
0
2 (VBB1: Cascode)
Gain (dB)
12.6
12.7
P1dB (dBm)
18.3
18.8
Psat (dBm)
18.8
19.2
Peak PAE (%)
38.2
42.9
#1
Back-gates are shorted to ground on chip
#2
Back-gates are biased with 10kOhm resister in series (AC floating bias)
VBB0=0
Fig. 9. SPST switch IL- Freq. with/without floating BG [1, 7].
4