ELEG 5923 MIDTERM STUDY GUIDE From HW2 Solutions: - Layouts/Stick diagram: Use via when possible! Check intermediate contacts especially. W and L are not the width and length of the entire layout but just the doped and poly channels. Cg is the capacitance of a normal transistor junction with a contact (6λ). See Lecture Notes 6,7,8, slide 22. Csb and Cdb are comparable to Cg, and to ½ Cg if no contact. NMH and NML do not have to be divided by VDD. For driving circuits, gate capacitance is not included in the propagation delay calculation. But, the gate capacitance of the next circuit is included. Somehow. Think of it as load impedance. From HW1 Solutions: - MOS terminal ID. For nMOS, VD > VS. For pMOS, VD < VS. Channel formation. VGS = 0, no channel. For nMOS, VGS > VT, channel formed. For pMOS, VGS < VT, channel formed. Transistor logic states. Transistor is ON when Channel is formed. When ON, it is considered as a closed switch. Check if output has connection to either VDD or GND. Pulldown analysis for converting expressions into gates. The expression is ready to construct. From In-Class Quiz 1: - nMOS and pMOS operation (see HW1 explanation) From In-Class Quiz 2: - First order Shockley model Parasitic capacitances Parasitic Capacitance Estimates C = Cg = eoxWL/tox = CoxWL = CpermicW First order Shockley Ids = 0 at cutoff, Vgs < Vt Ids = β(Vgs – Vt – Vds/2)Vds at linear, Vds < Vdsat Ids = β/2 (Vgs – Vt)2 at saturation, Vds > Vdsat β = μCoxW/L Derivation: Qchannel = CV C = Cgs = eoxWL/tox = CoxWL V = (Vgs – Vds/2) – Vt v = μE E = Vds/L So, Ids = Q/t = CV/(L/v) =CVv/L = (eoxWL/tox)(Vgs – Vds/2 – Vt)(μVds/L)/L = (CoxW)(Vgs – Vds/2 – Vt)(Vds)μ/L = β(Vgs – Vds/2 – Vt)Vds Early lectures: Other logic gates, time delay discussion Fabrication process
