Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
Name: __________________
Score: _______
Remember to box your final answers and show all your work. This is a closed book
exam, but a calculator may be used.
(5 points)
1. Complete the table below for each missing number. Each value uses a signed 8-bit
equivalence; the eighth (8th) MSB is the sign value. All negative numbers are to be
represented in 2’s complement form. Show all your work.
Decimal
-117
Signed Magnitude
2s Complement
Hexadecimal
11001111
AA
11001101
+43
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
(5 points)
2. Please add or subtract the following decimal numbers in 8-bit binary form. Show all
your work. Negative answers need to be in 2’s complement form. The MSB will be the
sign bit. Please indicate when overflow has occurred.
Decimal Operation
99 +37
99 - 22
15 - 22
-22 + 15
101 + 37
Binary Answer
Overflow (yes or no)
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
(1 points)
3. The ALU is given the AND command with the following register values. [A] = 0101
and [B] = 1001. Then [B] is loaded with = 1100 and the ALU command is XOR.
Determine the final [A] value after these operations.
(1 point)
4. Please add the two following hexadecimal numbers. Show all your work. All values
are positive.
A2 + 19.
(1 point)
5. Find the 2’s complement of DB416. Show all your work.
(1 point)
6. Add the following decimal numbers in packed BCD form. 133 + 88. Show all your
work.
(1 point)
7. Divide 1100 by 0010. Show all your work.
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
Design Problems
(30 points)
1. Design a synchronous state machine to make the following transitions 0, 2, 3, 12, 15,
0… This cycle repeats endlessly. Your solution should include a state transition
diagram, state transition table, and simplified logic for each state bit. Please use D
flip flops on this problem. All unused state can be driven to 0. You do not need to
draw the final circuit.
State Transition Diagram (10 points)
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
1. Continued
State Transition Table (10 points)
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Present State
C
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D+
Next State
C+
B+
A+
DD
Control
DC
DB
DA
K-Maps (10 points)
DD
DB
DC
DA
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
(30 points)
2. Design two circuits to detect all prime numbers between 0 and 15. Show how this
circuit can be implemented using (a) NAND-NAND gate logic and (b) Medium-ScaleIntegration (MSI) using a decoder.
Hint: To solve this problem, first complete a truth table. MSI implementation uses a
4:16 decoder. Remember to connect the enable (EN) input to 5 V. Zero (0) and one (1)
are not considered prime numbers.
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
2 (a) Continued.
2 (b) Continued.
4:16
Decoder
EN
S3
S2
S1
S0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
(25 points)
3. Use MSI to implement a comparator circuit using (a) one 8:1 multiplexers and (b)
using one (1) 4:1 multiplexer. Logic: If two (2) or more of the bit are high or all three (3)
are low the output goes high. Use bits A and B as selects and C as a variable of input.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
0
1
2
Out
8:1
MUX
3
Out (a)
3
4
0
1
5
2
6
3
7
4:1
MUX
S1
Out (b)
S0
S2 S1 S0
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
(30 points)
4. Design a Mealy Finite State Machine, which will recognize the sequence “0110”
without reset. Once the sequence is recognized, an output should go high indicating the
sequence has been found. The circuit should be a minimum 2-level SOP gate
implementation that is driving D flip-flops. The implementation should have as few
states as possible. Show the state diagram (10 pts.), the transition table (10 pts.), and the
final circuit design (10 pts.). Also show any pertinent work. Included are empty K-maps
if you need them.
Present State Input
A
B
I
Next State
A+
B+
Flip-Flops Output
DA
DB
O
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000
Digital Systems I
ELEG 2903
Sample Exam 3
Chapter 6 and 7
(Problem 4 continued)
University of Arkansas Fort Smith ∙ 5210 Grand Avenue ∙ P.O. Box 3649 ∙ Fort Smith, Arkansas 72913-3649 ∙ 479-788-7000