Reliable Boundary Scan Insertion Methodology For
Multi-Chip Module Based Designs
Shiva Kumar. K
Mtech (IV Sem )
Dept. of Electronics and Communication
BNMIT, Bangalore, INDIA
shivakmtech@gmail.com
Yasha Jyothi M Shirur
Asst.Professor
Dept. of Electronics and Communication
BNMIT, Bangalore, INDIA
yashamallik@gmail.com
Veena S. Chakravarthi, IEEE Member
Professor
Dept. of Electronics and Communication
BNMIT, Bangalore, INDIA
scveena@bnmit.org
Abstract- With the limited accessibility in the Multi Chip Figure 1 shows the MCM scenario with four cores considered.
Module (MCM) based design circuitry, Boundary scan plays a key
role in testing of MCM. With advance in MCM technology, more
and more cores are being integrated in the design. This poses
challenges in making MCM, an IEEE 1149.1 JTAG standard [1]
compliant device. A reliable Boundary scan insertion methodology
for a MCM environment with two cores is presented. The
methodology is further extended to four cores MCM design and its
testability using Boundary scan test logic is examined .The design
issues with the proposed methodology for two cores MCM [2]
under certain scenarios are revealed and further the methodology
is modified with a generic solution (i.e. the methodology can be
extended to any number of cores in MCM) to overcome the issues
and make the MCM core, IEEE 1149.1 JTAG compliant.
Figure1: MCM with four cores scenario
Keywords: MCM (Multi Chip Module), JTAG, Boundary scan,
TAP (Test Access Port), IR (Instruction Register), BSDL
(Boundary Scan Description Language)
I.
INTRODUCTION
The emerging technologies in VLSI demand for high
performance resulting from reduced signal delays, improved
signal quality between chips, reduced overall size and reduced
number of external components. This everlasting demand for
high circuit speed and low die area has lead to the development
of Multi-chip-Module (MCM).
With the limited accessibility of the internal circuitry in
MCM, testing of internal circuitry such as interconnects
between the cores becomes complex and time consuming. In
this context, Boundary scan plays an important role in testing
MCM. However with advances in MCM technology more and
more cores are being integrated in MCM. This poses a
challenge in making the MCM as an IEEE 1149.1 JTAG
standard compliant device.
Here, a Boundary scan insertion methodology is
presented for two cores in the MCM environment [1]. With the
minimal additional hardware, the MCM with two cores is made
Boundary scan compatible. The proposed methodology is
further extended to four cores in MCM and the testability of
MCM using Boundary scan test logic is examined.
With the proposed methodology for two cores MCM,
certain issues are encountered in scanning the instructions to
the Boundary scan test logic. Hence the proposed methodology
is further modified to overcome the issues faced in scanning the
instructions to MCM.
The paper is organized as follows. In section II, A new
core (Digital_timer) is designed to make it DFT(Design For
Testability) compatible with the MCM environment for two
cores and is designed to be JTAG 1149.1 -2001 standard
compliant .In section III, we extend the methodology to four
cores in MCMs. Section IV elevates issues faced by the
methodology under certain scenarios. In section V, the
modified Boundary scan insertion methodology is presented.
Section VI shows the simulation results followed by paper
conclusion in section VII.
II. DESIGNING NEW VLSI CORE FOR MCM TESTABILITY WITH
TWO CORES
A new core (Digital_timer) is designed with the inputs and
outputs as shown in the Figure 2. And signal description is
given in Table 1.
Figure 2: Digital timer core
Table1: Signal description of Figure 2.
Signal
clk_timer
Direction
Input
Bits
1
rst_timer
load_timer
Input
Input
1
2
in_6bit
Input
6
hr
min
sec
Iutput
Output
Output
5
6
6
Description
Reference clock for
Digital_timer
Reset timer
Load mode for hour
minute and seconds
Set Load value for hour
minute and second
Hour display
Minute display
Second display
The JTAG MACRO in Figure 3 consists of a TAP Controller,
Instruction Register and a Bypass Register designed according
to the standard IEEE 1149.1. Any serial data to the Boundary
scan cells and the JTAG MACRO is sent through the TDI pin.
The Boundary scan test logic operation is carried out with
respect to TCK (Test Clock). The TAP Controller and the
Instruction loaded in the Instruction Register, controls the
operation of the Boundary scan test logic in the circuit.
Digital_timer core with Boundary scan test logic
inserted with respect to the proposed Boundary scan insertion
methodology for two cores MCM is shown in Figure 4. The
corresponding signal description is given in Table 3.
The conventional Boundary scan compliant devices with
respect to IEEE 1149.1 standard will have the structure as
shown in the Figure 3 [2]. And corresponding signal
description is given in Table 2.
.
Figure 4: Digital_ timer core with modified boundary scan circuitry
Table 3: Signal description of Figure 4
Figure 3: Conventional core with JTAG.
Signal
Direction
Bits
Description
MCM_mode
Input
1
From_prev_
core_TDO
Input
1
This decides the core to
work in an mcm mode or
Digital_timer only test
mode.
This
pin
is
configured as bonding pad
option.
Signal driven from the
TDO of the previous core
Table 2: Signal description of Figure 3
Signal
TCK
Direction
Input
Bits
1
TMS
Input
1
TDI
Input
1
TDO
Output
1
TRST
Input
1
Description
Reference clock for boundary
scan test logic
Test Mode Selectthe state of
the tap controller changes with
respect to the value of TMS at
positive edge of TCK
Test Data In Any serial data
to the Boundary scan cells and
the JTAG MACRO is sent
through the TDI pin
The data sent through TDI is
verified through TDO
Reset boundary scan test
logicactive low
A Boundary scan compliant device should have [3]:
 One TAP controller between TDI and TDO.
 One Instruction Register, which has no length
restriction.
 One Bypass Register of exact one bit length.
 One IDCODE Register (optional) of exact 32 bit
length.
The Integration of the Digital timer core with another Boundary
scan compatible core (core1) in the two cores MCM
environment is shown in the Figure 5.
Figure 5: Digital_timer integrated in MCM core
The MCM with two cores as shown in Figure 5 satisfies all the
conditions for a device to be Boundary scan compliant
according to the IEEE 1149.1 standard [1].
II.I. INTERCONNECT TEST FOR TWO CORE MCM
The Boundary scan in an MCM is mainly used to test
interconnects between cores. The interconnects can be tested by
loading the EXTEST instruction and shifting the appropriate
test patterns to the Boundary scan test logic through TDI to
detect different faults, such as shifting logic ‘1’ to the
appropriate Boundary scan cell to detect the interconnect being
stuck at logic ‘0’.
The following steps are to be performed to test interconnects
under different scenarios, assuming both cores having
Instruction Register of same length.
Figure 7: Illustration of Case II
III.
EXTENDING THE METHODOLOGY TO FOUR CORES IN
MCM
The
proposed
Boundary
scan
test
methodology is extended to
Case I: Testing of interconnects in the board between MCM
four
cores
MCM
environment
as
shown
in the Figure 8.
and other JTAG compatible Integrated Circuit(IC).
1) Load EXTEST instruction in both IC1 and mcm_top1
by shifting the respective instruction OPCODE with
respect to the length of the Instruction Register
specified in BSDL file of both IC1 and Digital_timer
core (i.e., for mcm_top1).
2) Shift the serial test data to the respective Boundary
scan cell, for which interconnects is to be tested.
3) Update the test data to the respective interconnect.
4) Capture the test data from interconnects to the
respective boundary scan cell and shift to obtain the
value at the TDO of mcm_top1.
Case I is illustrated as shown in Figure 6.
Figure 8. Digital_timer in MCM scenario
Figure 6: Illustration of Case I with IC1and mcm_top1
Case II: Testing of interconnects within the MCM
Here it presumes the steps of case I to test interconnect,
considering each core in the MCM as an individual Boundary
scan compatible IC embedded in the board.
Case II is illustrated as shown in Figure 7.
The TDI pin of the mcm_top2 is connected to TDI of core1
(i.e., inputs to all data and Instruction Register) and to the
JTAG MACRO of the Digital_timer core. The TDO of core1 is
connected to the TDI of core2 and the TDO of core2 is
connected to the TDI of core3, to form a daisy chain connection
with respect to the serial test data pins (TDI and TDO) of
core1, core2 and core3.The TDO of core3 is connected to
boundary scan register of the Digital_timer core.
The MCM with four cores as shown in Figure 8 satisfies
all the conditions for a device to be Boundary scan compliant
according to the IEEE 1149.1 JTAG standard.
IV.
DESIGN ISSUES WITH THE PROPOSED
METHODOLOGY
The proposed Boundary scan insertion methodology poses
certain issue in shifting the instruction to the respective cores in
the MCM mode in following scenarios.
Case1. For two cores MCM with cores having different IR
length:
Since the instruction loading in MCM is with respect to the
IR length of the Digital_timer core (According to methodology
[1]),a random instruction will be loaded in core1 while
scanning instruction in the MCM mode. This may result in not
selecting the Boundary scan register between TDI and TDO of
core1, thus making the boundary scan chain discontinuous.
Case1 is illustrated as shown in Figure 9.
Figure 9: Illustrating case1 showing the effect of loading EXTEST in
IC1 and mcm_top1 for testing interconnects between IC1 and
mcm_top1
V.
FURTHER MODIFICATION TO THE PROPOSED
METHODOLOGY
To overcome the issues encountered in scanning instructions
under different scenarios as explained in section III, the
following modification is incorporated in the Boundary scan
insertion methodology.
The IR length in the BSDL file for the MCM has to be
specified to the maximum total length of Instruction Registers
of serially connected cores with respect to test data pins (TDI
and TDO). The operational code (OPCODE) for the respective
instructions has to be provided through the BSDL file
according to the IR length, such that each core in MCM will be
loaded with respective instruction.
Consider the scenario of four cores MCM with
Digital_timer, in which each core have IR length of two bit.
Then the IR length of the MCM has to be specified as ‘six’,
since maximum IR length of the serially connected cores in the
MCM (core1, core2, core3) is six. The OPCODE to be
specified for the above case is
Case2. For four cores MCM with cores having different IR
length:
Here, random instruction is loaded in core1, core2 and
core3 while scanning instruction in the MCM mode similar to For EXTEST instruction—000000
BYPASS instruction – 111111
previous case.
Case2 is illustrated as shown in Figure 10.
The following shows the content of the BSDL with the above
said modification:
“
attribute INSTRUCTION_LENGTH of IC2_MCM:
entity is 6;
Figure 10. Illustrating case2 showing the effect of loading EXTEST
in IC1 and mcm_top2 for testing interconnects between IC1 and
mcm_top2
attribute INSTRUCTION_OPCODE of IC2_MCM:
entity is
"EXTEST
(000000)," &
"SAMPLE
(010101)," &
"PRELOAD
(010101)," &
"BYPASS
(111111)" ;
Attribute
INSTRUCTION_CAPTURE
of
Case3. For four cores MCM with cores in MCM having equal
”
IC2_MCM: entity is "010101";
IR length:
With this modification, the issue of interconnect testing
Here, random instruction is loaded in core2 and core3, while
scanning instruction OPCODE in the MCM mode, thus making shown in Figure 11 is solved resulting in continuous Boundary
the Boundary scan chain discontinuous. This condition is scan chain as shown in Figure12.
illustrated as shown in the Figure 11.
Figure 11. Illustrating the effect of loading EXTEST in IC1 and mcm_top2
for testing interconnect between IC1 and mcm_top2
Figure 12. Illustrating the effect of the EXTEST instruction for testing of
interconnects between IC1 and mcm_top2 with modified methodology.
VI. RESULTS
The Digital_timer core with the proposed Boundary scan
insertion logic is integrated with three other Boundary scan
compatible cores (core1, core2, core3) in the MCM
environment. Every core is designed to have same IR length of
two. The RTL is developed using Hardware description Figure 14. Simulation results showing the status of boundary scan register cells
language (Verilog) and simulated using NCSIM simulation tool
when core2 and core3 are loaded with IDCODE instruction.
from Cadence.
SIMULATION RESULTS OBTAINED FOR CASE 3 (FIGURE 10):
SIMULATION RESULTS OBTAINED FOR CASE 3 (FIGURE 11):
Figure 13 shows the instruction being loaded into the
mcm_top2, when the IR length of the MCM is specified to be
‘two’ in the BSDL file. The instruction for ‘EXTEST’ is shifted
in the Instruction Register for two TCK clock cycles in the
shift_IR state (shift_IR state9). It is to be observed in the
Update_DR state(hex value’d’), the instruction being
updated in each Instruction Register is as shown in Table 4.
Figure 15 shows the shifting of instruction to the mcm_top2
when IR length is specified as ‘six’ in the BSDL file of
mcm_top2. Here at the end of the instruction scan (carried out
for ‘six’ TCK clock cycles) i.e, at the Update_DR state, each
core in mcm_top2 is loaded with the ‘EXTEST’ instruction.
Figure 15. Simulation results showing, the loading of EXTEST instruction to
mcm_top2 with IR_length specified as six
Figure 13. Simulation results showing the loading of EXTEST instruction to
mcm_top2 with IR length specified as two bit.
SIMULATION RESULTS OBTAINED FOR CASE 3 (FIGURE 12)
SHOWING CONTINUITY OF BOUNDARY SCAN CHAIN:
Table 4: The scanning of instruction for the IR length of mcm_top2 specified
as two bit.
State
Capture_DR
Shift_DR1st
positive edge
of TCK
Shift_DR2nd
positive edge
of TCK
Figure 16 shows the status of the Boundary scan registers after
TDI Core1_I Core2_I Core3_I Digital_timer_ shifting the instructions as shown in the Figure 15. It is to be
IR
IR
IR
IR
observed that the ‘clk_dr_bsc’ is not gated here, since every
0
01
01
01
01
core is loaded with the ‘EXTEST’ instruction, which intern
00
10
10
00
0
selects the Boundary scan register cells between TDI and TDO
of the respective cores. This enables the testing of interconnects
between IC1 and the mcm_top2.
0
00
01
01
00
SIMULATION RESULTS OBTAINED FOR CASE 3 (FIGURE 11)
SHOWING DISCONTINUITY OF BOUNDARY SCAN CHAIN:
Figure 14 shows the status of the Boundary scan registers after
shifting the instructions as shown in the Figure 13. It is
observed that, since IDCODE instruction is loaded in core2 and
core3 at the end of shifting instruction, Identification register is
selected between TDI and TDO of core2 and core3. The
Clk_dr_bsc signal for the Boundary scan register cells is gated
to ‘logic 1’ for core2 and core3 as seen in Figure 14 indicated
by an arrow. Since the Clk_dr_bsc signal is gated for core2 and
core3, no shifting will be carried out in the boundary scan
register cells. This is indicated within the box in Figure 14.
Figure 16. Simulation results showing the status of boundary scan register cells
when every core in MCM loaded with EXTEST instruction
The table 5, 6, 7 shows description of the signals in Figure
13,14,15,16.
Table 5: Signal description of Figures 12,13,14,15.
Signal
Direction
Bits
Description
state
Intermediate
register
Intermediate
register
4
Shows the current state
of the TAP controller
Updated instruction
register (in the
Update_DR state) of
core1 to be decoded
ir_out1
2
Signal
ir_out2
Direction
Intermediate
register
Bits
ir_out3
Intermediate
register
2
ir_out4
Intermediate
register
Bsc_scan
_reg
Intermediate
register
Clk_dr_b
sc
Input
IR_scan_
reg
Intermediate
register
2
2
1
2
Description
Updated instruction
register(in the
Update_DR state) of
core2 to be decoded
Updated instruction
register (in the
Update_DR state) of
core3 to be decoded
Updated instruction
register (in the
Update_DR state) of
Digital_timer core to be
decoded
Boundary scan register
cell scan out values are
stored in this register
Respective core
reference test clock
pulses gated from TCK
for the boundary scan
register cells
Respective cores
instruction register used
to shift the instruction
Table 7: Instructions and their respective OPCODE
Instruction
EXTEST
IDCODE
SAMPLE
BYPASS
VII.
OPCODE [1:0]
00
01
10
11
CONCLUSION
With addition of the minimal hardware to the Boundary scan
test logic, a reliable boundary scan insertion methodology is
presented for two cores MCM. The methodology is further
extended to four cores in the MCM environment. However the
methodology poses certain issues in scanning the instruction to
the MCM cores under different scenarios. The Boundary scan
insertion methodology is further modified to overcome the
design issues.The modified Boundary scan insertion
methodology can be extended to any number of cores in the
MCM making it IEEE 1149.1 standard JTAG compliant with
the tradeoff of increasing the IR length with the increase in
number of cores in the MCM.
VIII.
ACKNOWLEDGMENT
Authors wish to acknowledge Staff of Electronics &
Communication department for their support. Authors also
wish to acknowledge the BNMIT management for the
encouragement in carrying out this work.
REFERENCES
Table 6: Tap controller state assignment table
Controller State
Hex
Exit2-DR
0
Exit1-DR
1
shift-DR
2
Pause-DR
3
Select-IR-Scan
4
Update-DR
5
Capture-DR
6
Select-DR-Scan
7
Exit2-IR
8
Exit1-IR
9
Shift-IR
A
Pause-IR
B
Run-Test/Idle
C
Update-IR
D
Capture-IR
E
Test-Logic-Reset
F
1.
2.
3.
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boundary scan insertion and pattern generation for MCM based
designs, ”International Conference on Microelectronics, pp. 373 –
376, Dec. 2008.
IEEE Computer Society. “IEEE Standard Test Access Port and
Boundary-Scan architecture – IEEE Std. 1149.1-2001”, IEEE,New
York, 2001.
Frans de Jong and Alex Biewenga, “SiP-TAP : JTAG
implementation for SiP designs,” IEEE International Test
Conference, pp.1-10, Oct. 2006 .