FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Digital Logic Design
Laboratory Manual
CS - 211
Spring 2021
Semester 3RD
Name: FAIZAN KHAN
Roll Number: 1119-2020
Department of Computing
Hamdard Institute of Engineering & Technology
Hamdard University
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
LIST OF EXPERIMENTS
S#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Date
Experiments
Signature
Introduction to Digital Logic Design and Electronic Workbench
To understand the operation of various 2-Input and 3-Input logic
gates and verify its truth table
To design and implement the logic gate circuit for a given Boolean
expression
To simplify complex logic circuits using De Morgan’s theorem and
Boolean algebra identities
To understand the working of half adder and full adder and verify
its truth table
To understand the working of half subtractor and full sub tractor
and verify its truth table
To understand the concept of universal gates and implement the
logic circuit using NAND and NOR gates.
To study the Karnaugh maps and simplify the logic circuit using
truth tables
To understand the operation of magnitude comparator and verify
its behavior
To understand the operation of seven segment display and BCD to
seven segment decoder
To Implement 555 Timer IC As An Astable And Mon stable
Multivibrator.
To understand the operation of Multiplexers & De multiplexers
and observe the working of Dual 4-to-1 Multiplexer
To familiarize with the concept of sequential circuits and
implement the basic SR latch and D latch circuit
To study the working of JK type flip flop, implement the circuit
and verify the truth table
To understand the operation of Synchronous & Asynchronous
Counters and implementing using JK Flip Flops.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Marks Evaluation
Experiment No.
Marks
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Final
________________________
Instructor Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 01
Introduction to Digital Logic Design
EQUIPMENT TO BE USED IN THE LAB
Before performing Lab activities in the Lab, it is necessary that student should have a thorough
understanding of the equipment that is to be used in the lab.
The details of such equipment are mentioned as under:
1. Bread Board
Breadboard (or protoboard) is a construction base for prototyping of electronics. A Building or
prototyping circuit on a breadboard is also known as 'bread boarding’. In Breadboards we have
two sets of connected lines known as rows and columns as shown below:
Once inserted in a row, a component will be electrically connected to anything else placed in that
row. The same holds true for columns. But rows and columns are not connected with each other
unless connected externally.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Handling Precautions:
i. Always keep your work neat.
ii. Keep your component leads short.
iii. Avoid both overcrowding and excessive spacing.
iv.
Never force components into the breadboard socket contacts.
v. Never bend a component lead at the body of the component.
vi.
Leave at least ¼" of lead length available to plug into the breadboard socket itself.
2. Logic Probe
A logic probe is a hand-held pen-like test probe used for analyzing and troubleshooting the
logical states (Boolean 0 or 1) of a digital circuit. While most are powered by the circuit under
test, some devices use batteries. They can be used on either TTL (transistor-transistor logic) or
CMOS (complementary metal-oxide semiconductor) integrated circuit devices. Following figure
shows a logic probe:
There are usually three differently-colored LEDs on the probe's body:
•
•
Red and green LEDs indicate high and low states respectively.
An amber LED indicates a pulse (as used in a NOID Light to test for pulses to fuel
injectors on an electronically controlled fuel injection vehicle)
Handling Precautions:
i. Be careful when working close to any kind of high voltage or current.
ii. If high voltage or current is exposed in your circuit, cover that portion up so you don’t
actually touch it with your fingers or the logic probe.
iii. To use the logic probe you really have to know what points in the circuit to test. This
means you need to have a schematic or other wiring diagram, so you know what goes to
where.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
3. Power Supply
Power supplies are amongst the most popular pieces of electronic test equipment. There are a
variety of different types of power supplies used in Electronics Labs. The Power Supplies we’re
going to use are called multiple output power supplies. Multiple output power supplies have
more than one DC output, often two or three. These are useful and cost-effective for systems that
require multiple voltages. An often-used power supply for circuit development is a triple output
supply. One output supplies 0 to 5 volts, intended for digital logic. The other two supply
(typically) 0 to 25 or 0 to 30 volts, which can be used with bipolar analog circuitry. Sometimes a
tracking adjustment is supplied for the two 25 volt supplies so that the + and - 25 volt supplies
can be adjusted together by turning one knob.
Handling Precautions:
i. Electrical Power, floor and wall outlets are at 220 Volts AC. If you come in contact with
220 Volts AC it could be fatal; take appropriate safety precautions.
ii. Double-check your wiring and circuit connections. It is a good idea to use a point-topoint wiring diagram to review when making these checks.
iii. Avoid shorting the Power Supply as it may lead to serious Electric and Life hazards.
iv.
Switch off the circuit while modifying the circuit.
v. Double check the circuit before switching on the supply
4. Logic Gate ICs:
In electronics, a logic gate is an idealized or physical device implementing a Boolean function;
that is, it performs a logical operation on one or more logical inputs, and produces a single
logical output. Logic gates are primarily implemented using diodes or transistors acting as
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
electronic switches, but can also be constructed using electromagnetic relays (relay logic), fluidic
logic, pneumatic logic, optics, molecules, or even mechanical elements.
For small-scale logic, designers now use prefabricated logic gates from families of devices such
as the TTL 7400 series by Texas Instruments, the CMOS 4000 series by RCA, and their more
recent descendants. Increasingly, these fixed-function logic gates are being replaced by
programmable logic devices, which allow designers to pack a large number of mixed logic gates
into a single integrated circuit.
Handling Precautions:
i. Prevent Over-Voltage and Over-Current Conditions
ii. Unconnected input pins with very high impedance levels can adversely affect stability of
operation. Such pins should be connected through an appropriate resistance to a power
supply pin or ground pin.
iii. IC pins are numbered anti-clockwise around the IC starting in the bottom left-hand
corner, near the notch or dot. This is shown below:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
SAFETY PRECAUTIONS
Following proper safety practices are a must when working with electronic equipment. Not only
is there the danger of electrical shock, but the components can explode if not connected properly.
Many of today’s electronic components are easily damaged by improper handling. The test
equipment used in the electronic service industry is expensive and easily damaged if proper
operating procedures are not followed.
1. While implementing circuits on hardware, test points should be introduced and Logic
should be checked after every step/connection to avoid errors in the circuit.
2. Never make any changes to circuits without first isolating the circuit by switching off
and/or removing connections to supplies.
3. Equipment/Circuits must not be left unattended.
4. Equipment found to be faulty should be reported immediately to Instructor or Lab Staff.
5. It should be noted that unconnected TTL gate terminals are by default on High logic
Level which may affect the output logic of the circuit.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
INTRODUCTION TO ELECTRONIC WORKBENCH SOFTWARE
Electronics Workbench (EWB) is a design tool that provides you with all the components and
instruments to create board-level designs on your PC. The user interface of EWB consists of the
following:
Menus
•
•
Parts bin Toolbar
Circuit Window
Power Switch
Circuit window: The place where you create your schematics.
Parts bin: The components and instruments that you need to construct a circuit are
grouped into parts bins.
Each parts bin has a corresponding button on the Parts Bin toolbar. Clicking one of these buttons
displays another toolbar containing buttons representing the components and instruments
contained in that parts bin. To place a component or instrument on the circuit window, click the
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
desired part button and drag the component or instrument to the circuit widow. Instruments
toolbar includes a digital meter, a word generator, a logic analyzer, and a logic converter. These
instruments may be dragged onto the circuit window and used to test the circuit that you build
just as you would use test instruments in a lab. The final item on the menu bar is a power switch.
You need to click on the power switch when you are ready to activate your circuit.
Conclusion:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the basic concept of DLD, Logic probe and IC voltage level. .
LO2: Understand the how to use simulation software Electronics workbench.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 02
OBJECTIVE:
To understand the operation of various 2-Input and 3-Input logic gates and verify its truth table
BACKGROUND THEORY:
In general, logic circuits have one or more inputs and only one output. The circuits respond to
various input combinations, and a truth table shows this relationship between circuits input
combinations and its output. The truth table for a particular circuit explains how the circuit
behaves under normal conditions. Familiarization with a logic circuit’s truth table is essential to
the technologist or technician before he or she can design with or troubleshoot the circuit.
2-Input Logic Gates:
In this experiment, logic circuits with 2-inputs are:
Gate
Symbol
Truth Table
Boolean
Expression
IC Schematic
7408
AND
A
B
Y
0
0
0
0
1
0
1
1
0
1
0
1
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
7432
OR
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
7404
NOT
A
0
Y
1
1
0
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
7400
NAND
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
7402
NOR
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
3-Input Logic Gates:
In this experiment, logic circuits with 3-inputs are:
Gate
Symbol
Truth Table
Boolean
Expression
IC Schematic
7410
A B C Y
NAND
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
7427
A B C Y
NOR
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
• Power supply with cables
• Breadboard
• Logic gate ICs: 1) 7432, 2) 7408, 3) 7400, 4) 7402, 5) 7404, 6) 7410, 7) 7427
• LEDs
• Logic Probe (optional)
PROCEDURE:
1. Start with 7432 and carefully place it on to the breadboard as shown below:
2. After placing the IC, make Vcc and GND connections taking care not to reverse the
polarity.
3. Apply logic signals to inputs of the gate and observe the output using an LED connected
at the output. (Or by using Logic Probe if available).
4. Note the values in the tables provided and compare the findings with respective
predefined Logic Tables.
5. Now repeat the steps 2-4 with all the ICs provided
OBSERVATIONS:
7432 (OR)
7402 (NOR)
Input A Input B Output Y
Input A Input B Output Y
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
7408 (AND)
7400 (NAND)
Input A Input B Output Y
Input A Input B Output Y
7404 (NOT)
Input A Output Y
7410 (NAND)
7427 (NOR)
Input A Input B Input C Output Y
Input A Input B Input C Output Y
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1.If you ask to implement Y = AB + C, mention all the required IC number.
Q.2.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the working of Logic gate ICs and how to utilize them in circuits.
LO2: To experimentally verify the behavior of Logic gates against their established truth tables
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
MULTI SIM:
AND GATE:
OR GATE:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
NOT GATE:
NOR GATE:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
NAND GATE:
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 03
OBJECTIVE:
To design and implement a logic gate circuit for the given Boolean expression
BACKGROUND THEORY:
In computer science, a Boolean expression is an expression in a programming language that
produces a Boolean value when evaluated, i.e. one of true or false. A Boolean expression may be
composed of a combination of the Boolean constants true or false, Boolean-typed variables,
Boolean-valued operators, and Boolean-valued functions. Boolean expressions correspond to
propositional formulas in logic and are a special case of Boolean circuits.
Most programming languages have the Boolean operators OR, AND and NOT; in C and some
newer languages, these are represented by "||" (double pipe character), "&&" (double ampersand)
and "!" (Exclamation point) respectively, while the corresponding bitwise operations are
represented by "|", "&" and "~" (tilde). In theoretical literature the symbols used are often "+"
(plus), "·" (dot) and over bar, or "∨" (cup), "∧" (cap) and "¬" or "_" (prime).
In Boolean expressions, we observe the regular order of operations: Multiplication (AND) comes
before addition (OR). Thus, when we write
, we mean
.We can use
parentheses when this order of operations isn't what we want. For NOT, the bar over the
expression indicates the extent of the expression to which it applies; thus,
NOT x OR y), while
represents
represents (NOT A) OR (NOT B).
A warning: Students new to Boolean expressions frequently try to abbreviate
as
, that
is, they draw a single line over the whole expression, rather than two separate lines over the two
individual pieces. This abbreviation is wrong.
EXAMPLE PROBLEM
Every expression directly corresponds to a circuit and vice versa. To determine the expression
corresponding to a logic circuit, we feed expressions through the circuit just as values propagate
through it. Suppose we do this for our below circuit
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
LAB TASK
Design a logic gate circuit for the Boolean expression given below:
A
B
C
HARDWARE REQUIRED:
• Power supply with cables
• Breadboard
• Logic gate ICs: 1) AND Gate 2) OR Gate 3) NOT Gate
• LEDs
• Logic Probe (optional)
PROCEDURE:
1. Build the circuit on the bread board or electronic workbench software.
2. Check the Output (Y) of the circuit after applying Inputs (A, B, C)
3. Compute the truth tables.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
Y
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1. Does the theoretical calculations confirmed by Experimental findings? If yes, what is the advantage
in designing the circuits on paper rather than going straight to Hardware implementation without
calculation?
Q.2.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand fairly complex Boolean expressions.
LO2: Design a Logic Circuit for a given Boolean expression
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
MULTI SIM:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 04
OBJECTIVE:
To simplify complex logic circuits using De Morgan’s theorem and Boolean algebra identities
BACKGROUND THEORY:
Following are some Boolean identities and laws which will be very useful during simplification
of Logic expressions:
Additive
Multiplicative
Boolean Laws
0+A=A
0A=0
1+A=1
1A=A
Basic Identity
A+A=A
AA=A
Identity Law
Inverse Law
Double Inverse Law
A+B=B+A
AB=BA
Commutative Law
(A + B) + C = A + (B + C)
(A B) C = A (B C)
Associative Law
A (B + C) = A B + A C
A + (B C) = (A + B) (A + C)
Distributive Law
DeMorgan’s Laws
DeMorgan proposed two laws that are an important part of Boolean algebra. The two
DeMorgan's laws are stated as follows:
Law # 1:The complement of a product of two variables is equal to the sum of complements of the
individual variables
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Law # 2:The complement of a sum of two variables is equal to the product of complements of the
individual variables.
EXAMPLE CONVERSION OF COMPLEX LOGIC FUNCTION TO SIMPLE LOGIC
FUNCTION
To illustrate, let's take the following expression and reduce it using De Morgan's Theorems:
Correct Method
Following the advice of breaking the longest
(uppermost) bar first, we should begin by
breaking the bar covering the entire expression
as a first step:
Incorrect Method
Following is the incorrect method for applying
De Morgan’s Theorem:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
LAB TASK:
Simplify the following Boolean expression using De Morgan’s theorem and Boolean identities
(attach working on a separate sheet):
Task 1
Y=A+A.B
Logic Circuit and Truth Table for Original Expression
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
A
B
0
0
0
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
1
Y
1
0
1
1
A
B
0
0
0
1
1
0
1
1
Simplified Expression
Logic Circuit and Truth Table for Simplified Expression
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
Y
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Task 2
Y=
Logic Circuit and Truth Table for Original Expression
B
C
0
0
0
1
1
0
1
1
Y
B
C
0
0
0
1
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
Y
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
1
0
1
1
Simplified Expression
Logic Circuit and Truth Table for Simplified Expression
HARDWARE REQUIRED:
• Power supply with cables
• Breadboard
• Logic gate ICs: 1) AND Gate 2) OR Gate 3) NOT Gate
• LEDs
• Logic Probe (optional)
PROCEDURE:
1. First of all, implement the logic circuit of the original expressionfor task 1 and build the
truth table.
2. Simplify the expression of task 1 using Booleanidentities and DeMorgan laws.
3. Now implement the logic circuit of the simplified expression and built its truth table.
4. Compare the two truth tables for task 1
5. Repeat the same procedure for task 2.
REVIEW QUESTIONS:
Q.1. Does the theoretical calculations confirmed by Experimental findings? _________________
Q.2. List at least two advantages of simplifying Boolean expressions:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Q.3.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand and validate De Morgan’s Theorem.
LO2: Observe the advantages of simplifying a complex Boolean expression in Logic circuits
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Experiment # 05
OBJECTIVE:
To understand the working of half adder and full adder and verify its truth table
BACKGROUND THEORY:
In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many
computers and other kinds of processors, adders are used not only in the arithmetic logic unit(s),
but also in other parts of the processor, where they are used to calculate addresses, table indices,
and similar operations.
• HALF ADDER:
The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C).
The carry signal represents an overflow into the next digit of a multi-digit addition. The simplest
half-adder design, pictured on the right, incorporates an XOR gate for S and an AND gate for C.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
With the addition of an OR gate to combine their carry outputs, two half adders can be combined
to make a full adder.
Inputs
Outputs
A
B
Sum
Cout
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
• FULL ADDER:
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full
adder adds three one-bit numbers, often written as A, B, and Carry in (Cin); A and B are the
operands, and Cin is a bit carried in from the previous less significant stage. The full-adder
is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The
circuit produces a two-bit output, output carry and sum typically represented by the signals carry
out (Cout) and Sum (S).
Inputs
Outputs
A
B
Cin
Sum
Cout
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
Logic gate ICs:
1) 7486 XOR
LEDs
Logic Probe (optional)
2) 7408 AND
3) 7432 OR
PROCEDURE:
1. Construct the circuit for Half Adder on Breadboard
2. Apply all Input combinations to the circuit.
3. Check and note the outputs for the corresponding inputs and record the values in the
observation table.
4. Now construct the circuit for Full Adder on Breadboard
5. Repeat steps 2 and 3.
OBSERVATION:
Inputs
Outputs
Inputs
Outputs
A
B
Cin
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A
B
0
Sum
Cout
Sum
Cout
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1. Mention an application both of Half Adder and Full Adder Circuit:
______________________________________________________________________________
Q.2.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the concept of Half Adder and Full Adder.
LO2: Observe the behavior of Half Adder and Full Adder in Logic circuits
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment #06
OBJECTIVE:
To understand the working of half sub tractor and full sub tractor and verify its truth table
BACKGROUND THEORY:
In electronics, a Subtractor is a digital circuit that performs subtraction of numbers and can be
designed using the same approach as that of an adder. First taking the 2’s complement of the
subtrahend and adding it to the minued. The 2’s complement can be obtained by taking the 1’s
complement and adding 1.
To perform A - B, we complement the bit of B, add them to the bit of A, and add 1 to the input
carry as follow:
• HALF SUBTRACTOR:
Subtracting a single-bit binary value B from another A (i.e. A - B) produces a difference bit D
and a borrow out bit B-out. This operation is called half subtraction and the circuit to realize it is
called a half Subtractor.
Inputs
Outputs
A
B
D
Br
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
• FULL SUBTRACTOR:
The full-Subtractor is a combinational circuit which is used to perform subtraction of three bits.
It has three inputs, X (minuend) and Y (subtrahend) and Bi (borrow in) and two outputs D
(difference) and Bo (borrow out). The full Subtractor is a combination of X-OR, AND, NOT,
OR Gates. The two half Subtractor put together gives a full Subtractor.
Inputs
Outputs
A
B
Br-in
D
Br-out
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
Logic gate ICs:
1) 7486 XOR 2) 7408 AND 3) 7404 NOT 4) 7432 OR
LEDs
Logic Probe (optional)
PROCEDURE:
1. Construct the circuit for half Subtractor on breadboard or electronic workbench
2. Apply all Input combinations to the circuit.
3. Check and note the outputs for the corresponding inputs and record the values in the
observation table.
4. Now construct the circuit for full Subtractor on breadboard or electronic workbench
5. Repeat steps 2 and 3.
OBSERVATION:
Inputs
A
B
0
Outputs
Difference Borrow
Inputs
Outputs
A
B
Br-in
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Difference
Borrow
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1. Mention an application both of half subtractor and full subtractor circuit:
______________________________________________________________________________
Q.2.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the concept of half subtractor and full subtractor.
LO2: Observe the behavior of half subtractor and full subtractor in Logic circuits.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 07
OBJECTIVE:
To understand the concept of universal NAND and NOR Gates and implement Logic Circuits
using only NAND or NOR gates.
BACKGROUND THEORY:
Because the NAND function has functional completeness all logic systems can be
converted into NAND gates. This is also true of NOR gates. In principle, any combinatorial logic
function can be realized with enough NAND gates and/or NOR Gates.
NAND GATE EQUIVALENT OF BASIC LOGIC GATES
Gate
NOT
Description
A NOT gate is made by joining the inputs
of a NAND gate together. Since a NAND
gate is equivalent to an AND gate
followed by a NOT gate, joining the inputs
of a NAND gate leaves only the NOT gate.
AND
An AND gate is made by following a
NAND gate with a NOT gate
OR
If the truth table for a NAND gate is
examined or by applying De Morgan's
Laws, it can be seen that if any of the
inputs are 0, then the output will be 1.
To be an OR gate, however, the output
must be 1 if any input is 1. Therefore, if
the inputs are inverted, any high input will
trigger a high output.
NOR
A NOR gate is simply an inverted OR
gate. Output is high when neither input A
nor input B is high
XOR
An XOR gate is constructed similarly to an
OR gate, except with an additional
NAND gate inserted such that if both
inputs are high, the inputs to the final
NAND gate will also be high, and the
output will be low
Desired Gate
NAND Equivalent
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Gate
Description
XNOR An XNOR gate is simply an XOR gate
with an inverted output
Desired Gate
NAND Equivalent
NOR GATE EQUIVALENT OF BASIC LOGIC GATES
Gate
Desired Gate
NAND Equivalent
NOT
AND
OR
NAND
XOR
XNOR
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
AND OR INVERTER (AOI)TO NANDGATE CONVERSION STEPS
1. If starting from a logic expression, implement the design with AOI logic.
2. In the AOI implementation, identify and replace every AND, OR, and INVERTER gate with its
NAND equivalent.
3. Redraw the circuit.
4. Identify and eliminate any double inversions (i.e. back-to-back inverters).
5. Redraw the final circuit.
Example
Boolean expression to be converted into Universal NAND equivalent:
1. Implement the circuit using AOI Logic:
2. Identify and replace every AND, OR and/or NOT gate with its NAND equivalent.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
3. Redraw the circuit (using NAND counterparts).
4. Identify and eliminate any double inversions (i.e. back-to-back inverters).
5. Redraw the final circuit.
NOTE: The same procedure can be followed for conversion of AOI gates to Universal NOR Gates
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
LAB TASK 1:
Consider the Boolean expression given below:
a) Construct and AOI circuit for the expression and develop its Truth Table
b) Convert the circuit into its Universal NAND equivalent. (Attach working on separate sheet).
NAND Gate equivalent of the given expression:
Truth table for the AOI circuit
Input Input Input Output
A
B
C
Y
Truth table for the NAND circuit
Input Input Input Output
A
B
C
Y
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
• Power supply with cables
• Breadboard
• NAND gate IC
• LEDs
• Logic Probe (optional)
PROCEDURE:
1.
2.
3.
4.
5.
Construct the NAND equivalent circuit on bread board.
Apply inputs and check corresponding Outputs.
Note the readings in Table 3.2
Compare the two tables 3.1 and 3.2
Was the conversion successful? If yes,
LAB TASK 2:
Design the equivalent circuit for the following expression using Universal NOR Gate (attach
working on separate sheet):
NOR Gate equivalent of the given expression:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Truth table for the AOI circuit
Input Input Input Output
A
B
C
Y
Truth table for the NOR circuit
Input Input Input Output
A
B
C
Y
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the importance of NAND and NOR Gates as Universal gates.
LO2: Apply the rules of converting AOI Gates to their Universal NAND or Universal NOR equivalents.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 08
OBJECTIVE:
To understand and use the Karnaugh maps in designing Logic circuits using Truth tables.
BACKGROUND THEORY:
The Karnaugh map, also known as the K-map, is a method to simplify Boolean algebra
expressions. Maurice Karnaugh introduced it in 1953 as a refinement of Edward Veitch's 1952
Veitch diagram. The Karnaugh map reduces the need for extensive calculations by taking
advantage of humans' pattern-recognition capability. It also permits the rapid identification and
elimination of potential race conditions. The required Boolean results are transferred from a truth
table onto a two-dimensional grid where the cells are ordered in Gray code, and each cell
position represents one combination of input conditions, while each cell value represents the
corresponding output value. Optimal groups of 1s or 0s are identified, which represent the terms
of a canonical form of the logic in the original truth table. These terms can be used to write a
minimal Boolean expression representing the required logic. Some important terms related to Kmaps are as follows:
Sum of Products(SOP): A Sum of Products (SOP) expression contains: – Only AND (product)
operations at the “outermost” level – Each term must be a sum of literals.
Example SOP expression: Y = A.B + B.C + A.C
Product of Sum(POS): A Product of Sums (POS) expression contains: – Only OR (sum)
operations at the “outermost” level – Each term that is summed must be a product of literals.
Example POS expression: Y = (A+B+C) . (A+B) .(A+C)
Minterm: A min term is a special product of literals, in which each input variable appears exactly
once. A function with ‘n’ variables has 2 n minterms (since each variable can appear
complemented or not). If you have a truth table for a function, you can write a sum of minterms
expression just by picking out the rows of the table where the function output is ‘1’.
Maxterm: A maxterm is a sum of literals, in which each input variable appears exactly once. A
function with ‘n’ variables has 2 n maxterms. If you have a truth table for a function, you can
write a product of maxterms expression by picking out the rows of the table where the function
output is ‘0’.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
2-Input K-Map
In the truth table of a 2-Input Logic system:
3-Input K-Map
In the truth table of a 3-Input Logic system:
4-Input K-Map
In the truth table of a 4-Input Logic system:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
AN EXAMPLE SYSTEM SIMPLIFICATION USING K-MAP
The easiest way to simplify an expression with a Karnaugh map is to follow these steps:
a) Build the expression's truth table.
b) Starting with a blank Karnaugh map, take each row of the truth table where the output is 1 and
mark the corresponding minterm in the map with a 1.
c) Form rectangular blocks of neighboring cells where each cell contains a 1. The size of these
blocks must be a power of two, e.g. one, two, four, eight, etc. Large blocks will give simpler
final equations, so try to make the blocks as large as possible.
d) Find the equation for each block. Each block will have variables which remain constant and
the block's equation is the ANDing of these variables. Now build an OR function with the block
equations as arguments. You have created the sum or products simplified expression.
Example:
The given Boolean algebraic expression is
m = a′bc + ab′c + abc′ + abc
First build the truth table as below:
To use a Karnaugh map we draw the following map which has a position (square) corresponding
to each of the 8 possible combinations of the 3 Boolean variables. The upper left position
corresponds to the 000 row of the truth table, the lower right position corresponds to 101.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
The 1s are in the same places as they were in the original truth table. The 1 in the first row is at
position 110 (a = 1, b = 1, c = 0).
The minimization is done by drawing circles around sets of adjacent 1s. Adjacency is horizontal,
vertical, or both. The circles must always contain 2n 1s where n is an integer.
We have circled two 1s. The fact that the circle spans the two possible values of a
(0 and 1) means that the a term is eliminated from the Boolean expression corresponding to this
circle.
Now we have drawn circles around all the 1s. Thus the expression reduces to
m = bc + ac + ab
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
LAB TASK
From the given truth table of a Logic Circuit, determine the simplified Boolean expression of the
system in SOP (Sum of Products) form (attach working on a separate sheet):
A
B
C
Y
0
0
0
1
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
0
Simplified Expression
A
B
C
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
Y
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
Logic gate ICs:
1) 7408 AND 2) 7404 NOT 3) 7432 OR
LEDs
Logic Probe (optional)
PROCEDURE:
1. Solve the initial equation of the system by K-Map.
2. Simplify the equation as much as possible using De Morgan’s Theorem and/or Boolean
identities. (attach working on separate sheet)
3. Now build the logic circuits for the simplified Boolean expression and complete the table.
REVIEW QUESTIONS:
Q.1. Does the given truth table are confirmed by the observed truth table? ________
Q.2.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand and use K-Maps.
LO2: Design and/or synthesis and logic circuits using K-Maps.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 09
OBJECTIVE:
To understand and practically observe the working of 7485 Magnitude comparator.
BACKGROUND THEORY:
A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing unit s (CPUs) and
microcontrollers (MCUs).
The operation of a single bit digital comparator can be expressed as a truth table shown below:
Inputs
Outputs
A
B
A>B
A=B
A<B
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
Gate 1 produces the function A>B and gate 3 gives A<B while gate 2 is an XNOR gate giving an
equality output.
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
IC 7485 (Magnitude comparator)
LEDs
Logic Probe (optional)
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
PROCEDURE:
1. The connection diagram of 7485 Magnitude Comparator is shown below:
A0 … A3 & B0 … B
Pins 5, 6, and 7
Pins 2, 3 and 4
Vcc, GND
: 2, 4-Bit data to be compared.
: Comparator outputs.
: Cascading outputs, to be used if connecting another comparator.
: Supply Pins for the IC.
2. Make supply connections to the IC.
3. Now apply the inputs to the comparator and check the corresponding outputs.
4. Complete the following Truth Table as per observations:
S #.
1
2
3
A3
0
1
1
A2
0
0
1
A1
0
0
1
A0
1
0
1
B3
1
1
1
B2
0
0
0
B1
1
1
1
B0
0
0
0
4
5
6
7
8
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
A>B
A=B
A<B
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1. Write one application of magnitude comparator?
Q.2.Draw the block diagram for the 8-bit magnitude comparator using two 7485 ICs?
Q.3.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the working of Digital Comparators.
LO2: Experimentally verify the behavior of 7485 IC
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 10
OBJECTIVE:
To investigate the operation of seven segment display and practically observe the working of
7447 BCD to seven segment Decoder.
BACKGROUND THEORY:
Typically 7-segment displays consist of seven individual colored LED’s (called the segments),
within one single display package. In order to produce the required numbers or HEX characters
from 0 to 9 and A to F respectively, on the display the correct combination of LED segments
need to be illuminated and BCD to 7-segment Display Decoders such as the 74LS47 do just that.
A standard 7-segment LED display generally has 8 input connections, one for each LED segment
and one that acts as a common terminal or connection for all the internal display segments. Some
single displays have also have an additional input pin to display a decimal point in their lower
right or left hand corner.
In electronics there are two important types of 7-segment LED digital display:
The Common Cathode Display (CCD) – In the common cathode display, all the cathode
connections of the LED’s are joined together to logic “0” or ground. The individual segments are
illuminated by application of a “HIGH”, logic “1” signal to the individual Anode terminals.
The Common Anode Display (CAD) – In the common anode display, all the anode connections
of the LED’s are joined together to logic “1” and the individual segments are illuminated by
connecting the individual Cathode terminals to a “LOW”, logic “0” signal.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
BCD to 7-Segment Display Decoders:
A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or
74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a smaller
4-bit binary number (half a byte) to be used to display all the denary numbers from 0 to 9.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
7447 (BCD to 7 Segment Decoder)
LEDs / Seven Segment Display
Logic Probe (optional)
PROCEDURE:
1. The connection diagram of 7447 IC (BCD to 7-segment decoder) is shown below:
A, B, C, D
a–g
Lamp Test
RBI & RBO
Vcc , GND
2.
3.
4.
5.
:
:
:
:
:
BCD inputs.
Decoded outputs.
If grounded, turns all the outputs high, regardless of input applied.
Blanking Input & Blanking Output respectively
Supply Pins for the IC.
Make supply connections to the IC.
Now apply the inputs to the Decoder on specified pins (A to D),
Connect a common anode 7 segment display on the outputs (a to g).
Observe the output on 7 Segment display
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1.What will be displayed on 7-segment when the BCD inputs are 1111? ________
Q.2.What is the function of LAMP TEST input?
Q.3.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the working of 7 Segment displays.
LO2: Experimentally verify the behavior of BCD to 7 Segment Decoders
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
EXPERIMENT#11
Objective
Implementation Of 555 Timer As An Astable And Monostable Multivibrator.
Hardware Required
•
•
•
•
•
•
•
•
Power Supply
555 IC
Ceramic Capacitor 0.1 uF
Electrolyte capacitor 100 uF
Resistors (1K, 10K and 20K)
LED
Bread Board
Oscilloscope
Theory
The 555 is most widely IC used for timer, pulse generation and oscillation circuit. The
555 IC introduce in 1972 and still in use because it is simple in use, low price and good stability.
The 555 IC is available in 8 pin package. Internally 555 contain two comparators, a RS-Flip
Flop, an output non-inverting buffer, a discharge NPN Transistor and three 5-Kohms resistance
in series combination.
Multi vibrator are the circuit which produces two state output, that is square waveform.
The name Multivibrator was initially applied to the free-running oscillator version of the circuit
because its output waveform was rich in harmonics.
There are three types of multivibrators:
a) Bi-Stable Multivibrator
b) Mono-stable Multivibrator
c) Astable Multivibrator
In this lab the 555 IC is used to implement Multivibrator, required only few external
components.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Fig 9.1: The 555 Timer IC
Astable Multivibrator
Astable Multi-vibrator has no stable state means both logic 0 and logic 1 are at unstable
state. The output is at logic 0 after some time it shifted to logic 1 and again come to logic 0 after
some time. Simply we can say that Astable Multi-vibrator is that, in which the circuit is not
stable in either state Astable Multi-vibrator is basically square wave generator circuit.
Formula to calculate Frequency
of Astable
Multi Vibrator
Fig 9.2: Astable
Multi-vibrator
circuit using 555 IC
F = 1.44 / ((R1 + 2R2) C1)
Monostable Multivibrator
Monostable multivibrator is also called as one–shot Multivibrator. When the output is
low, the circuit is in stable state, transistor T1 is ON and Capacitor C is shorted to the ground.
However, upon application of a negative trigger pulse to Pin–2, transistor T1 is turned OFF,
which releases short circuit across the external capacitor and drives the output High. The
capacitor C now starts charging up toward VCC through R. However when the voltage across the
external capacitor equals 2/3 VCC, upper comparator‟s output switches from low to high which
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
in turn derives the output to its low state. And the output of the flip flop turns transistor T1 ON,
and hence the capacitor C rapidly discharges through the transistor. The output of the
Monostable remains low until a trigger pulse is again applied. Then the cycle repeats. The time
during which the output remains high is given by:
tp = 1.1 R C
Design
1. Choose a desired pulse width, say tp =1.1 ms.
2. Choose a value for capacitor C (0.1 μF) and then calculate the value
of R by using the equation for tp.
Circuit Diagram
1. Connect the components/equipment as shown in the circuit diagram.
2. Switch ON the power supply.
3. Connect function generator at the trigger input.
4. Connect channel-1 to the trigger input and channel-2 to the output (Pin
3).
5. Using Function Generator, apply 1 KHz square wave with amplitude of
approx. equal to 6 Vpp at the trigger input.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
6. Observe the output voltage with respect to input and note down the pulse
width and amplitude.
8. Compare the practical pulse width noted in the step above with its
theoretical value (tp=1.1 RC)
Calculations
Theoretical Pulse width R = C = tp = 1.1 RC =
Practical Pulse width tp =
Result
Attach the result which you observed during performing the lab.
Exercise
1. What is the formula for the output frequency of Astable multivibrator?
2. What is the other name for monostable multivibrator (MSMV)?
3. What is the formula for the output pulse width of MSMV?
Learning Outcomes
Upon completion of the laboratory experiment, the student will able to:
1. Implement 555 time IC in astable and monostable mode
Conclusion
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
__________________________________________________________
__________________________________________________________
__________________________________________________________
__________________________________________________________
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 12
OBJECTIVE:
To investigate the operation of Multiplexers and practically observe the working of 74153 Dual
4-to-1 Multiplexer.
BACKGROUND THEORY:
In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line. A multiplexer of 2 n inputs has n
select lines, which are used to select which input line to send to the output. Multiplexers are
mainly used to increase the amount of data that can be sent over the network within a certain
amount of time and bandwidth. A multiplexer is also called a data selector. An electronic
multiplexer makes it possible for several signals to share one device or resource, for example one
A/D converter or one communication line, instead of having one device per input signal.
Fig. 10.1. Schematic of a 2-to-1 Multiplexer. It can be equated to a controlled switch
Conversely, a demultiplexer (or demux) is a device taking a single input signal and selecting one
of many data-output-lines, which is connected to the single input. A multiplexer is often used
with a complementary demultiplexer on the receiving end. The schematic below shows a 1-to-2
demultiplexer on the left and an equivalent switch on the right.
Fig. 10.2. Schematic of a 1-to-2 Demultiplexer. Like a Multiplexer it can be equated to a
controlled switch
An electronic multiplexer can be considered as a multiple-input, single-output switch, and a
demultiplexer as a single-input, multiple-output switch.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
DESIGN PROCESS OF A MULTIPLEXER BASED CIRCUIT
The design process explained below uses 2-to-1 Multiplexer as an example system. Here we
have 21 = 2 inputs, so we must have n = 1 selector pins for the multiplexer.
S
0
A
1
0
1
1
0
B
1
0
1
0
1
0
1
0
Z
1
1
0
0
1
0
1
0
Table 10.1. Truth Table of 2 x1 MUX
In case of Multiplexers, the selector pin ‘S’ determines which output should appear on output, as
− If S = 0, then A is the Output (Z = A).
− If S = 1, then B is the Output (Z = B).
Keeping in view the above mentioned conditions, the Truth Table in Table 10.1 can be
simplified as:
S Z
0 A
1 B
Table 10.2. Simplified Truth Table
By closely observing the Table 10.1, we can extract the following equation for 2-to-1
Multiplexer:
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Fig. 10.3. Logic circuit of 2 x1 MUX
The same method can be used to design Multiplexers with higher no. of inputs and
correspondingly higher no. of selector pins.
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
74153 (Dual 4-to-1 Multiplexer)
LEDs
Logic Probe (optional)
PROCEDURE:
1. The connection diagram of 74153 Dual 4-to-1 Multiplexer is shown below:
Fig. 10.4. Connection diagram of Dual 4x1 MUX IC
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
a) 1G, 2G: Pins for enabling multiplexers 1 & 2 respectively. Must be grounded for
enabling the required Multiplexer.
b) 1C0...1C3 and 2C0…2C3: The 4 inputs of Multiplexers 1 & 2 respectively.
c) A, B: Selector pins.
d) Y1, Y2: Output pins for Multiplexers 1 & 2 respectively.
e) Vcc, GND: Supply Pins for the IC.
2. Make supply connections to IC. Then ground the strobe pin 1G to enable Multiplexer 1.
3. Now apply the inputs to the multiplexer on specified pins (1C1 to 1C3) and apply
selector combinations. Observe the output on Pin Y1. Use following Truth Table for
assistance and verifying results:
Table 10.2. Truth Table of 4 x1 MUX
4. After verifying results, design the Gate level circuit for 4-to-1 Multiplexer using design
process used in designing of 2-to-1 Multiplexer (attach working on a separate sheet).
Draw the circuit for 4x1 Multiplexer below:
Equation for 4-to-1 Multiplexer
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
REVIEW QUESTIONS:
Q.1. Write the application of MUX in digital circuit.
Q.2. Use three 2x1 MUX and connect them to make one 4x1 MUX
Q.3.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the working of Multiplexers and Demultiplexers.
LO2: Experimentally verify the behavior of Multiplexers
LO3: Use Multiplexers to make circuit designing fast and simple.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 13
OBJECTIVE:
To familiarize with the concept of sequential circuits and study the working of SR Latch, Gated
SR Flip Flop and D-type Flip Flop.
BACKGROUND THEORY:
Unlike Combinational Logic circuits that change state depending upon the actual signals being
applied to their inputs at that time, Sequential Logic circuits have some form of inherent
“Memory” built in to them as they are able to take into account their previous input state as well
as those actually present, a sort of “before” and “after” effect is involved with sequential logic
circuits.In other words, the output state of a “sequential logic circuit” is a function of the
following three states, the “present input”, the “past input” and/or the “past output”. Sequential
Logic circuits remember these conditions and stay fixed in their current state until the next clock
signal changes one of the states, giving sequential logic circuits “Memory”.Sequential logic
circuits are generally termed as two state or Bistable devices which can have their output or
outputs set in one of two basic states, a logic level “1” or a logic level “0” and will remain
“latched” (hence the name latch) indefinitely in this current state or condition until some other
input trigger pulse or signal is applied which will cause the bistable to change its state once
again.
Following is the Block Diagram of a Sequential logic. Note that a sequential logic is mainly a
combinational logic with memory element (flip flops) added to it:
Fig. 12.1. Block diagram of sequential circuit
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
SR-LATCH
The SR Latch, also known as SR flip-flop, can be considered as one of the most basic sequential
logic circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has
two inputs, one which will “SET” the device (meaning the output = “1”), and is labelled ‘S’ and
another which will “RESET” the device (meaning the output = “0”),labelled ‘R’.Then the SR
description stands for “Set-Reset”. The reset input resets the flip- flop back to its original state
with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset
condition.
The basic SR Latch can be implemented by using either NAND Gates (NAND Latch) or NOR
gates (NOR Latch), both of them are shown as under:
NAND LATCH
To make single bit SR NAND Latch, connect
together a pair of cross- coupled 2-input
NAND gates as shown, to form a Set-Reset
Bistable also known as an active LOW SR
NAND Gate Latch, so that there is feedback
from each output to one of the other NAND
gate inputs. This device consists of two
inputs, one called the Set, ‘S’ and the other
called the Reset, ‘R’ with two corresponding
outputs ‘Q’ and its inverse or complement Q
(Q’) as shown below:
NOR LATCH
As well as using NAND gates, it is also
possible to construct simple one-bit SR Flipflops using two cross-coupled NOR gates
connected in the same configuration. The
circuit will work in a similar way to the
NAND gate circuit above, except that the
inputs are active HIGH and the invalid
condition exists when both its inputs are at
logic level “1”, and this is shown below:
Fig. 12.2a. SR NAND Latch Circuit
Fig. 12.2b. SR NOR Latch Circuit
S R Q Q’
0 1 1 0
1 1 1 0
1 0 0 1
0 0 1 1 Invalid
S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
1 1 1 1 Invalid
Table 12.1a. Truth table of SR NAND Latch
Table 12.1b. Truth table of SR NOR Latch
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
GATED SR FLIP FLOP
It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only
changes state when certain conditions are met regardless of the condition of either the Set or the
Reset inputs. By connecting a 2-input AND gate in series with each input terminal of the SR
Flip-flop a Gated SR Flip-flop can be created. This extra conditional input is called an “Enable”
input and is given the prefix of “E“. The addition of this input means that the output at Q only
changes state when it is HIGH and can therefore be used as a clock (CLK) input making it levelsensitive. The circuit symbol with internal circuitryis shown below:
Fig. 12.3. Gated SR-type flip flop symbol and logic circuit
When the Enable input “E” is at logic level “0”, the outputs of the two AND gates are also at
logic level “0”, (AND Gate principles) regardless of the condition of the two inputs S and R,
latching the two outputs Q and Q into their last known state. When the enable input “E” changes
to logic level “1” the circuit responds as a normal SR bistable flip-flop with the two AND gates
becoming transparent to the Set and Reset signals.This additional enable input can also be
connected to a clock timing signal (CLK) adding clock synchronization to the flip-flop creating
what is sometimes called a “Clocked SR Flip-flop“. So a Gated Bistable SR Flip-flop operates as
a standard bistable latch but the outputs are only activated when a logic “1” is applied to its E
input and deactivated by a logic “0”. The Truth Table for Gated SR Flip Flop is as follows:
E/C
S
R
Q
Q’
0
X
X
Qprev
Qprev
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
1
1
Table 12.2. Truth table of Gated SR-type flip flop
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Major Drawback in an SR Flip Flop:
Both S & R inputs cannot be ‘0’ (NAND Latch) or ‘1’ (NOR Latch) at the same time as it may
cause the latch to produce undesirable results at output.
D-TYPE FLIP FLOP
One way to eliminate the undesirable condition of the indeterminate state in SR Latch is to
ensure that the inputs ‘S’ & ‘R’ are never equal to ‘1’ at the same time. This is done in the DLatch (or D-type Flip Flop). This latch has only two inputs: ‘D (Data)’ and ‘E/C
(Enable/Control)’. The ‘D’ input goes directly to the ‘S’ input and its complement is applied to
the ‘R’ input. The resulting Gate level circuit with circuit symbol is shown below:
Fig. 12.4. Gated D-type flip flop symbol and logic circuit
E/C D
Q
Q’
Comment
0
X Qprev Qprev No change
1
0
0
1
Reset
1
1
1
0
Set
Table 12.3. Truth table of Gated D-type flip flop
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
Logic ICs
a) NOT gate
LEDs
Logic Probe (optional)
b) AND gate
c) NOR gate
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
PROCEDURE:
1. Connect the circuit of SR Flip Flop as shown in figure 12.3 and verify the Truth Table.
2. Now connect the inverter between S and R inputs (D-type Flip Flop configuration) and
verify the truth table for D-type Flip Flop.
REVIEW QUESTIONS:
Q.1. Based on your knowledge of D-Flip Flop, how can we develop a Toggle Flip Flop (T-Flip
Flop) from D-Flip Flop?
Q.2.What have you learnt from this experiment?
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the concept of Sequential Logic
LO2: Understand the working of SR Latch, Gated SR Flip Flop and D Type Flip Flop.
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Experiment # 14
OBJECTIVE:
To understand the working of JK Type Flip Flop, and study the error safe configuration of JK
Flip Flop (Master-Slave configuration).
BACKGROUND THEORY:
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to
be a universal flip-flop circuit. The JK flip flop is basically a gated SR Flip-flop with the addition
of a clock input circuitry that prevents the illegal or invalid output condition that can occur when
both inputs S and Rare equal to logic level “1”. Due to this additional clocked input, a JK flipflop has four possible input combinations:
1.
2.
3.
4.
Logic 1
Logic 0
No change
Toggle
Fig. 13.1. Gated JK-type flip flop symbol and logic circuit
Input Output Description
J K Q Q’
0 0 0
0
Memory
no change
0 0 0
1
0 1 1
0 Reset Q » 0
0 1 0
1
1 0 0
1
Set Q » 1
1 0 1
0
1 1 0
1
Toggle
1 1 1
0
Comments
same as
for the
SR Latch
toggle
action
Table 13.1. Truth table of Gated JK flip flop
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Although above circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called “race” if the output ‘Q’ changes state before the timing pulse of the clock input
has time to go “OFF”. To avoid this the timing pulse period (T) must be kept as short as possible
(high frequency). As this is sometimes not possible with modern TTL IC’s the much improved
Master-Slave JK Flip-flop was developed.
THE MASTER -SLAVE JK FLIP -FLOP
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from the
“Slave” flip-flop are fed back to the inputs of the “Master” with the outputs of the “Master” flip
flop being connected to the two inputs of the “Slave” flip flop. This feedback configuration from
the slave’s output to the master’s input gives the characteristic toggle of the JK flip flop as
shown below:
Fig. 13.2. Gated Master-Salve JK flip flop circuit
The input signals J and K are connected to the gated “master” SR flip flop which “locks” the
input condition while the clock (CLK) input is “HIGH” at logic level “1”. As the clock input of
the “slave” flip flop is the inverse (complement) of the “master” clock input, the “slave” SR flip
flop does not toggle. The outputs from the “master” flip flop are only “seen” by the gated “slave”
flip flop when the clock input goes “LOW” to logic level “0”. Following is the working
mechanism:
− When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional changes to its
inputs are ignored. The gated “slave” flip flop now responds to the state of its inputs passed over by the “master”
section.
− Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are fed through to the
gated inputs of the “slave” flip flop and on the “High-to-Low” transition the same inputs are reflected on the output
of the “slave” making this type of flip flop edge or pulse-triggered.
− Then, the circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the
falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only
passes data with the timing of the clock signal.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
HARDWARE REQUIRED:
•
•
•
•
•
Power supply with cables
Breadboard
7473 Dual JK Flip Flops
LEDs
Logic Probe (optional)
PROCEDURE:
1. The connection diagram of 7473 Dual JK Flip Flop is shown below:
Fig. 13.3. Connection diagram of Dual JK flip flop IC
a) 1J, 2J, 1K, and 2K: Pins for J and K inputs for flip flops 1 & 2 respectively.
b) 1CLK and 1CLK: Clearing Inputs for Flip Flops 1 & 2 respectively. Activated by
grounding pins where required.
c) 1CK, 2CK: Clock inputs for Flip Flops 1 & 2 respectively.
d) Q1, Q2, Q1, and Q2’: Output pins for Flip Flops 1 & 2 respectively.
2. Connect the circuit as shown in figure 13.2 for Master Slave JK Flip Flop.
3. Now apply the inputs to the Flip Flop on specified pins (J1, J2, K1& K2). Apply Clock
input on 1CLR and inverted clock on 2 CLR. Observe the output on Pins Q1 &Q2’.
4. Note the observations in the following Truth Table compare it with Table 13.1.
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Input Output Description
J K Q Q’
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Table 13.2. Truth table of experimental findings
LEARNING OUTCOMES:
Upon successful completion of the lab, students will be able to:
LO1: Understand the JK Flip Flop
LO2: Understand the possible shortcoming in JK Flip Flops and its correction by the concept of
JK Master Slave Flip Flop
To be filled by Demonstrator/Lab Instructor
Date of Conduct
Last Date of Submission
Signature
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.
FACULTY OF ENGINEERING SCIENCES AND TECHNOLOGY
Hamdard Institute of Engineering & Technology
Hamdard University
Hamdard Institute of Engineering & Technology, Hamdard University
Sharae Madinat Al-Hikmah, Muhammad Bin Qasim Avenue, Karachi 74600, Pakistan.