An original method based on Simulink to
model and simulate a.c.-d.c. converters
taking into account the overlap phenomenon
Christophe Batard, Frederic Poitiers, Christophe Millet and Nicolas Ginot
Nantes Atlantique Electrical Engineering and Electronics Research Institute, University of
Nantes, France
E-mail: frederic.poitiers@univ-nantes.fr
Abstract This paper presents a simple and original method to simulate the behaviour of a.c.-d.c.
converters with Matlab-Simulink. This approach takes into account the overlap phenomenon with
continuous and discontinuous conduction modes. The a.c. to d.c. converter is presented as a block
(voltage input and voltage output) which can be inserted in a complex structure. The simplicity of the
method makes it easy to understand and its short computing time makes it an interesting alternative to
the Matlab SimPower Systems toolbox and PSIM software for teaching power electronics simulation.
The method is designed in order to be user-friendly and easy to implement for students. In this
paper, it is used for a six-pulse rectifier and extended to a twelve-pulse rectifier with delta/wye-delta
transformer. Experimental results are provided to validate the proposed modelling method.
Keywords a.c.-d.c. converter; power electronics education; power system modelling; power system
simulation; six-pulse rectifier; twelve-pulse rectifier
Three-phase a.c. to d.c. converters are widely used in many industrial power converters in order to obtain continuous voltage using a classical three-phase a.c.-line. These
converters, when they are used alone or associated for specific applications, can
present problems due to their non-linear behaviour. It is then important to be able
to model accurately the behaviour of these converters in order to study their influence on the input currents waveforms and their interactions with the loads (classically inverters and a.c.-motors).
Several studies have shown the importance to have tools to simulate the behaviour
of complex power electronics systems1–3 and several methods have been also presented in order to reduce the simulation time or to improve the precision. Although
constant topology methods have been developed,4 variable topology methods seem
to be very suitable for simulation of power-electronics converters.5
The development of specific software dedicated to simulation of power electronic
systems (PSIM, SABER, PSCAD, SimPowerSystems toolbox of Simulink . . .)
allows the fast and accurate simulation of converter switching. However, for educational purposes, it can be interesting to have several elementary functions instead of
using pre-designed blocks of these softwares. Furthermore, by using elementary
functions, the computing time can be decreased.
In this paper, we develop an original and simple method to model and simulate
a.c.-d.c. converters taking into account the overlap phenomenon with continuous
and discontinuous conduction modes using Matlab-Simulink. If the electrical
network is considered as ideal (no line inductance) and the conduction is
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C. Batard, F. Poitiers, C. Millet and N. Ginot
Fig. 1 Basic modelling of a single-phase rectifier.
maintained continuous, (id > 0), the modelling of the converters can be realised very
simply by a functional approach (commutation functions) where the switches are
opened or closed. An example is presented in Fig. 1. In this paper, the proposed
approach is completely different from the approach based on commutation functions. It permits us to simulate accurately the commutation in three-phase rectifier
bridges, even under unbalanced supply voltages (the influence of voltage unbalances on a.c. harmonic magnitude currents has been demonstrated6) or line impedance conditions.
The overlap phenomenon and the unbalance of line impedances can be taken into
account by modifying the commutation functions to correspond to the real behaviour
of the rectifiers in these conditions. Indeed, the commutations are not instantaneous.
Several contributions have already been proposed in scientific literature to refine the
modelling of rectifiers. Most of these contributions show good simulation results but
the analytical models used are complex and do not reflect precisely the real behaviour of the converter.7,8
Some methods have been developed in order to model and simulate power factorcorrected single-phase a.c.-d.c. converters.9 Here, our approach is applied to a sixpulse rectifier fed by a delta-wye transformer. The method is then extended to a
twelve-pulse diode rectifier fed by a delta/wye-delta transformer. Multi-pulse rectifiers configurations are often used to improve power quality10 and particularly the
twelve-pulse configuration which is widely used in industrial equipments in order
to obtain almost sinusoidal input currents and to have almost ripple-free output
d.c.-voltage.11,12,13
We show here that our method can be easily applied to this configuration. The
system can then be computed and the results obtained are compared to the experimental ones. Using these results, the validity of the model is discussed.
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Modelling of a six-pulse a.c.-d.c. converter
Let us consider the case of a diode rectifier fed by a step-down transformer connected
to a three-phase electrical network and its block representation made with Simulink
(Fig. 2). In order to model the rectifier taking into account input and output inductances L1 and Ld, we have chosen an approach with changeable topology of static
converters. The diodes are modelled by an ideal model which indicates the state of
the switch:
vD = 0 when the diode is on
iD = 0 when the diode is off
Description of the operation modes
There are 13 operation modes to describe:
1 stage of discontinuous conduction mode (P0)
6 stages of classical conduction (P1 to P6)
6 stages of overlap (O1 to O6)
For one running stage, we determine the value of di/dt for each inductance (L1 and
Ld) and the voltage for each diode. In order to simplify the presentation of the results,
we consider that the line is balanced (same r.m.s. voltages and line inductances L1)
Fig. 2 Six-pulse a.c.-d.c. converter.(a) Electrical circuit; (b) Simulink equivalent circuit.
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C. Batard, F. Poitiers, C. Millet and N. Ginot
and have no resistive part. Naturally, the method is equivalent under unbalanced
conditions but the mathematical expressions of the different variables are more
complex.
• Discontinuous conduction mode
This mode corresponds to the case where id = 0 (Fig. 3(a)). In this case, all diodes
are open, we have eqn (1):
dia1 dib1 dic1
=
=
=0
dt
dt
dt
(1)
The voltages in two diodes must reach zero in order to move the simulation into one
of the six classical conduction stages:
– it moves from P0 to
– it moves from P0 to
– it moves from P0 to
– it moves from P0 to
– it moves from P0 to
– it moves from P0 to
•
P1 if
P2 if
P3 if
P4 if
P5 if
P6 if
ua1b1 > |ua1c1| and ua1b1 > |ub1c1|
ua1c1 > |ua1b1| and ua1c1 > |ub1c1|
ub1c1 > |ua1b1| and ub1c1 > |u a1c1|
ub1a1 > |ua1c1| and ub1a1 > |ub1c1|
uc1a1 > |ua1b1| and uc1a1 > |ub1c1|
uc1b1 > |ua1b1| and uc1b1 > |ua1c1|
Classical conduction stages
We have 6 classical conduction stages:
P1: D1 and D5 ‘on’; P2: D1 and D6 ‘on’; P3: D2 and D6 ‘on’; P4: D2 and D4 ‘on’; P5:
D3 and D4 ‘on’; P6: D3 and D5 ‘on’;
As an example, we will consider the following succession of stages: P0, P1, O1, P2,
O2 . . . P6, O6, P1, . . .
The first classical phase P1 is described by (Fig. 3(b)):
dia1
di
di
u −v
= − b1 = d = a1b1 o
dt
dt
dt
2L1 + Ld
(2)
dic1
=0
dt
(3)
To go from stage P1 (D1 D5 ‘on’) to overlap stage O1 (D1 D5 D6 ‘on’), looking for
D6 voltage:
vD6 = ub1c1 +
L1
(ua1b1 − vo )
2L1 + Ld
(4)
When vD6 = 0, we go from stage P1 to stage O1.
•
Overlap stages
We can distinguish 6 overlap stages:
O1: D1, D5 and D6 ‘on’; O2: D1, D2 and D6 ‘on’; O3: D2, D4 and D6 ‘on’; O4: D2, D3
and D4 ‘on’; O5: D3, D4 and D5 ‘on’; O6: D1, D3 and D5 ‘on’;
For each overlap stage, we determinate the value of di/dt for each inductance, for
example for overlap stage O1 (Fig. 3(c)):
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Simulation of a.c.-d.c. converter behaviour
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Fig. 3 Operation modes (a) Discontinuous conduction stage; (b) classical conduction
stage P1: D1 and D5 ‘on’;(c) Overlap stage O1: D1 D5 and D6 ‘on’.
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C. Batard, F. Poitiers, C. Millet and N. Ginot
dia1 did
=
dt
dt
(5)
ib1 + ic1 = −id ⇔ −
dib1 dic1 did
−
=
dt
dt
dt
(6)
The expression of the di/dt as a function of the device parameters is more complicated to obtain here than in the case of a classical running stage. Equations have
been detailed in Ref. 15 and the final result is recalled below:
dia1 did
1
[ua1b1 + ua1c1 − 2vo ]
=
=
dt
dt 3L1 + 2 Ld
(7)
dib1
1
=
dt
3L1 + 2 Ld
⎛ − 2L1 + Ld u + L1 + Ld u + v ⎞
a1b1
a1c1
o⎟
⎜⎝
⎠
L1
L1
(8)
dic1
1
=
dt
3L1 + 2 Ld
⎛ − L1 + Ld u − 2L1 + Ld u + v ⎞
a1b1
a1c1
o⎟
⎜⎝
⎠
L1
L1
(9)
The transition between overlap stage O1 to the following classical stage P2 is done
when iD5 reaches zero. To obtain equations for this stage, we just have to do index
permutation in eqns (2) and (3). So, for the stage P2, D1 and D6 are on and eqns (2)
and (3) can easily be used with simple permutations of indexes b and c:
dia1
di
di
u −v
= − c1 = d = a1c1 o
2 L1 + Ld
dt
dt
dt
(10)
dib1
=0
dt
(11)
In the same way, to go from stage P2 (D1 D6 ‘on’) to overlap stage O2 (D1 D6 D2
‘on’), we are looking for D2 voltage:
vD2 = ub1c1 +
L1
(ua1c1 − vo )
2L1 + Ld
(12)
When vD2 = 0, we go from stage P2 to stage O2.
To obtain equations of O2 stage, we just have to do a permutation of indexes a and
c in eqns (7), (8) and (9) and modify the sign of vo and did/dt.
We obtain the di/dt corresponding to the other operation modes and overlap stages
by doing circular permutations of indexes.
‘Six-pulse diode rectifier’ block
The internal structure of the six-pulse diode rectifier block is presented in Fig. 4.
Four different blocks can be seen in this scheme: the first one called ‘diode voltage’
is a Matlab function which computes each diode voltage. The inputs of this block
are the initial phase and the three-phase network voltages.
The second one called ‘di/dt + phase’ computes the new running stage and each
inductance di/dt. The new running stage depends on the initial phase, the diode
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Fig. 4 Internal structure of ‘six-pulse diode rectifier’ block.
voltages and currents. The diode voltages and the values of di/dt are computed using
the electric schemes of Fig. 3.
The third, called ‘initial phase’ extracts the running stage of the ‘di/dt + phase’
block; this running stage becomes the initial phase of the next calculation step (the
Simulink block ‘memory’ is used).
The block ‘diode current’ then computes each diode current which permits us to
obtain the d.c. current and the line currents.
•
Diode current block
This block contains diode rectifier, line inductances and inductance of the d.c. side.
The line currents ia1, ib1, ic1 and d.c. current id are traditionally computed by integration of di/dt values of L1 and Ld. We then use six integrator blocks. The most important difficulty is the accurate determination of the instant when the current reaches
zero; this instant permits us to know when the switches become off.
The originality of our approach is the calculation of the values of each diode
current with the values of di/dt of inductances L1 and Ld (Fig. 5). We then use six
integrator blocks (one for each diode). The integrator blocks are set to limit their
minimal output value to zero (lower saturation limit); this feature permits us to
avoid the problem of accurate determination of the instant when diode currents
reach zero.
It is then possible to determine the output current of the rectifier (id = iD1 + iD2 +
iD3) and the input line currents (ia1 = iD1 − iD4, ia2 = iD2 − iD5, ia3 = iD3 − iD6).
Transformer
The transformer is considered as ideal. We consider m1 = n2/n1, the turns ratio
between secondary and primary windings (Fig. 2). The delta/wye coupling is simple
to model:
Voltages:
ua1b1 = m1 (uAB − uBC ) ; ub1c1 = m1 (uBC − uCA ) ; uc1a1 = m1 (uCA − uAB )
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C. Batard, F. Poitiers, C. Millet and N. Ginot
Fig. 5
Internal structure of ‘diode current’ block.
Currents:
iA = m1 (ia1 − ic1 ) ; iB = m1 (ib1 − ia1 ) ; iC = m1 (ic1 − ib1 )
The equivalent Simulink model is shown in Fig. 6.
Load
In order to simplify the demonstration, we have considered a purely resistive load
and using Simulink, the value of the resistance is modelled as a gain. More complex
loads can also be simply simulated.15
Experimental validation
The waveforms related to the device presented in Fig. 2 can be seen in Fig. 7. The
simulation parameters are adjusted as follows:
a.c. input transformer line-line r.m.s. voltage: U = 88 V, 50 Hz; m1 = 0.58; Rd = 30
Ω; Ld = 1 H; L1 = 1.2 mH
We can see that the simulated waveforms are very close to the experimental ones.
The overlap interval υ1 is equivalent for simulation and experimental results
(υ1 ≅ 0.7 ms).
The list of configuration parameters used for Matlab simulation is:
Start time: 0
Type: Variable-step
Stop time: 0.2 s
Solver: ode15 s (stiff/NDF)
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Fig. 6
Internal structure of ‘D–Y transformer’ block.
Simulation of a.c.-d.c. converter behaviour
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C. Batard, F. Poitiers, C. Millet and N. Ginot
Fig. 7 Comparison of simulation and experimental waveforms in a six-pulse linefrequency diode bridge converter. (a) Simulation; (b) experimental results.
Max step size: 1e-4
Relative tolerance: 1e-5
Min step size: auto
absolute tolerance: auto
Using a PC with an Intel core 2 duo CPU running at 2.19 GHz with 1 GB RAM,
the simulation time was 4 s.
This model has also been tested with a load constituted of an inverter and an
induction machine. The results of this test have validated operations for discontinuous conduction mode. For the same configuration parameters, the simulation time
was 5 s.
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Simulation of a.c.-d.c. converter behaviour
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Modelling of a twelve-pulse diode rectifier
The method developed for modelling the set ‘transformer + six-pulse diode rectifier’
can be extended to the modelling of a delta/wye-delta transformer feeding a twelvepulse diode rectifier.
Let us consider the electrical scheme presented in Fig. 8 and its representation by
a block approach with Simulink. As done previously, we can find three blocks:
D-Y-D transformer, twelve-pulse diode rectifier and resistive load.
Description of operation modes
The approach is similar to the one used for six-pulse rectifier but the number of
stages to be described has increased.
Fig. 8
Twelve-pulse a.c.-d.c. converter. (a) Electrical circuit; (b) Simulink
equivalent circuit.
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C. Batard, F. Poitiers, C. Millet and N. Ginot
There are now 73 operation modes to describe:
1 stage of discontinuous conduction mode (P0)
36 stages of classical conduction (P1 to P36)
36 stages of overlap (O1 to O36)
•
Classical conduction stages
We have 36 classical conduction stages:
P1: D1, D5, D7 & D11 ‘on’; P2: D1, D6, D7 & D11;
.............................................................................
P35: D3, D5, D9 & D11; P36: D1, D5, D9 & D11.
For each stage, we determine the inductance di/dt, then we obtain di/dt for the 35
other stages by doing circular permutations of indexes.
Example of classical phase P1 (Fig. 9): D1, D5, D7 and D11 ‘on’:
dia1 dia2
di
di
di
=
= − b1 = − b2 = d
dt
dt
dt
dt
dt
(13)
did
1
(ua1b1 + ua2b2 − vo )
=
(
dt 2 L1 + L2 ) + Ld
(14)
dic1 dic2
=
=0
dt
dt
(15)
To go from stage P1 (D1, D5, D7 & D11 ‘on’) to overlap stage O1 (D1, D5, D6, D7 &
D11 ‘on’), we are looking for D6 voltage:
vD6 = ub1c1 +
L1
(ua1b1 + ua2b2 − vo )
2 ( L1 + L2 ) + Ld
(16)
When vD6 = 0, we go from stage P1 from stage O1.
•
Overlap stages
We can distinguish 36 overlap stages:
O1: D1, D5, D6, D7 & D11 ‘on’; O2: D1, D6, D7, D11 & D12; O3
.................................................................................................
O35: D1, D3, D5, D9 & D11 ‘on’; O36: D1, D5, D7, D9 & D11.
The method used for the six-pulse rectifier to obtain the values of diodes di/dt can
be applied to this device. For overlap stage O1, we have:
dia1 did ua1b1 + ua1c1 + 2 (ua2b2 − vo )
=
=
dt
dt
3L1 + 4 L2 + 2 Ld
(17)
dib1
1
=
[(−2L1 − 2L 2 − Ld ) ua1b1 + ( L1 + 2 L2 + Ld ) ua1c1
dt
L1 (3L1 + 4 L2 + 2 Ld )
− L1 (ua2b2 − vo )]
(18)
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Fig. 9 Operation modes. (a) Classical conduction stage P1: D1, D5, D7 and D11 ‘on’.
(b) Overlap stage O1: D1, D5, D6, D7 and D11 ‘on’.
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C. Batard, F. Poitiers, C. Millet and N. Ginot
dic1
1
[( L1 + 2 L2 + Ld ) ua1b1 − ( 2 L1 + 2 L2 + Ld ) ua1c1
=
dt
L1 (3L1 + 4L2 + 2 Ld )
− L1 (ua2b2 − vo )]
(19)
The transition between overlap stage O1 to classical stage P2 is done when iD5 reaches
zero.
In the same way, to go from stage P2 (D1, D6, D7, D11 ‘on’) to overlap stage O2
(D1, D6, D7, D11, D12 ‘on’), we are looking for D12 voltage:
vD12 = ub2c2 +
L2
(ua1c1 + ua2b2 − vo )
2 L1 + 2 L2 + Ld
(20)
When vD12 = 0, we go from stage P2 to stage O2.
‘Twelve-pulse diode rectifier’ block
The internal structure of the ‘twelve-pulse diode rectifier’ block is presented in Fig.
10. It looks like the structure used for the six-pulse rectifier, the main difference
being the block called ‘current’ which has three outputs: iabc1, iabc2 and id corresponding respectively to the current values in inductances L1, L2 and Ld while uabc1, uabc2
and vo are used as inputs for the twelve-pulse diode rectifier block.
Transformer
The transformer is considered as ideal, the delta/wye coupling is simple to model
and has been presented in Fig. 6. We consider m2 = n3/n1, the turns ratio between
tertiary and primary windings.
The delta/delta voltage coupling is modelled by a simple gain:
ua2 b2 = m2 uAB ; ub2 c2 = m2 uBC ; uc2 a2 = m2 uCA
The delta/delta coupling is more complicated for currents. It depends on the running
stage, for example:
Fig. 10
Internal structure of ‘twelve-pulse diode rectifier’block.
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Simulation of a.c.-d.c. converter behaviour
Phase P1: ja2 = 2ia2/3;
Phase P2: ja2 = ia2/3;
jb2 = ib2/3;
jb2 = ib2/3;
419
jc2 = ib2/3
jc2 = 2ic2/3
For overlap stages, we always have:
J a 2 = (ia2 − ib2 ) 3 ; J b 2 = (ib2 − ic2 ) 3 ; J c 2 = (ic2 − ia2 ) 3
The transitions between each running stage are managed with Simulink using a
Matlab function (Fig. 11).
The transformer primary windings currents are deduced from the two secondary
winding currents:
iA = m1 (ia1 − ic1 ) + m2 ( ja2 − jc2 )
(21)
iB = m1 (ib1 − ic1 ) + m2 ( jb2 − jc2 )
(22)
iC = m1 (ic1 − ia1 ) + m2 ( jc2 − ja2 )
(23)
Experimental validation
The tests have been made with the same transformer as previously, the same resistive
load and the same primary phase-to-phase voltage (U = 88 V). The tertiary winding
of the transformer has been delta coupled.
The simulation parameters are:
m2 = m3 = 0.58; R = 30 Ω; Ld = 1 H; L1 = 1.2 mH; L2 = 0.4 mH.
Simulation and experimental waveforms related to the twelve-pulse a.c.-d.c. structure are shown in Fig. 12.
We can see that the simulated waveforms are very close to the experimental ones.
The overlap interval is equivalent for simulation and experimental results (υ1 ≅
0.9 ms, υ2 ≅ 0.6 ms).
The configuration parameters described earlier are also used here. Using the same
PC, the simulation time was 10 s.
Conclusions
Modelling and simulation of power electronic devices with Matlab-Simulink has
been presented. The method used permits the simulation of three-phase diode rectifier bridges in continuous and discontinuous conduction modes and takes into
account the overlap phenomenon. The method is designed to be user-friendly and
easy to implement for students. Thus they can simulate complex power electronic
devices with different loads with a reduced computing time compared to commercial
software.
After presenting the method with a six-pulse rectifier fed by a delta-wye transformer, it has been applied to a twelve-pulse diode rectifier fed by a delta/wye-delta
transformer. The results have shown that the simulation time is short even for a
complex device and the experimental validation has proven the good accuracy of
the model. For academic research, this approach is currently used by students to
study associations of active filters with non-linear loads.
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C. Batard, F. Poitiers, C. Millet and N. Ginot
Fig. 11 Internal structure of ‘D–Y-D transformer’ block.
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Fig. 12 Comparison of simulation and experimental waveforms in a twelve-pulse
line-frequency diode converter. (a) Simulation; (b) experimental results.
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International Journal of Electrical Engineering Education 48/4
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