electronics
Article
A High-Accuracy Ultra-Low-Power Offset-Cancelation
On-Off Bandgap Reference for Implantable
Medical Electronics
Jiangtao Xu 1 , Yawei Wang 1 , Minshun Wu 1 , Ruizhi Zhang 1 , Sufen Wei 1,2 , Guohe Zhang 1, *
and Cheng-Fu Yang 3, *
1
2
3
*
School of Microelectronics, Xi’an Jiaotong University, Xi’an 710049, China
School of Information and Engineering, Jimei University, Fujian 361021, China
Department of Chemical and Materials Engineering, National University of Kaohsiung, No. 700,
Kaohsiung University Rd., Nan-Tzu District, Kaohsiung 811, Taiwan
Correspondence: zhangguohe@mail.xjtu.edu.cn (G.Z.); cfyang@nuk.edu.tw (C.-F.Y.)
Received: 11 June 2019; Accepted: 19 July 2019; Published: 21 July 2019
Abstract: An ultra-low-power and high-accuracy on-off bandgap reference (BGR) is demonstrated
in this paper for implantable medical electronics. The proposed BGR shows an average current
consumption of 78 nA under 2.8 V supply and an output voltage of 1.17 V with an untrimmed accuracy
of 0.69%. The on-off bandgap combined with sample-and-hold switched-RC filter is developed to
reduce power consumption and noise. The on-off mechanism allows a relatively higher current in
the sample phase to alleviate the process variation of bipolar transistors. To compensate the error
caused by operational amplifier offset, the correlated double sampling strategy is adopted in the BGR.
The proposed BGR is implemented in 0.35 µm standard CMOS process and occupies a total area of
0.063 mm2 . Measurement results show that the circuit works properly in the supply voltage range of
1.8–3.2 V and achieves a line regulation of 0.59 mV/V. When the temperature varies from −20 to 80 ◦ C,
an average temperature coefficient of 19.6 ppm/◦ C is achieved.
Keywords: bandgap reference; ultra-low power; high accuracy; switched-RC; correlated double sampling
1. Introduction
Along with the continuous development of modern society and growing demand for high-quality
life, implantable medical electronics are increasingly adopted in healthcare medical devices such as
cardiac pacemakers [1–3]. These devices are usually battery powered and need to have ultra-low
power consumption of a few microwatts or less [4–8]. Since they would probably be placed where
they are not easily removed or recharged, they have to continue working for a relatively long time.
A number of important analog circuits for high-precision signal processing, such as voltage regulators,
analog to digital converters (ADCs) and digital to analog converters (DACs), are used in almost every
biomedical system. All of them demand an accurate bandgap reference (BGR) [9]. In these devices,
BGRs provide the voltage references for other important functional blocks and are supposed to be
working all the time. Thus, the required average current dissipation of BGR is in the range of several
tens of nano-ampere [10–12].
To meet the requirement for low power, subthreshold voltage references without bipolar transistors
have been developed and used widely [10–12]. However, these VTH -based references often suffer
from degraded performance in accuracy since the threshold voltage (VTH ) of MOSFET changes too
much (about 50–100mV) with process variation. Trimming is usually employed to solve this issue.
However, the temperature coefficient would be worse after trimming [12]. A conventional bipolar
junction transistor (BJT)-based BGR can provide a fairly precise reference voltage, but it requests
Electronics 2019, 8, 814; doi:10.3390/electronics8070814
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Electronics 2019, 8, 814
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larger power consumption. When we try to budget a lower current consumption for BJT-based BGR,
resistors with very large values are needed, and the VBE of BJT also varies dramatically. VBE variation
introduces large fluctuations to the output reference voltage. Even for relatively larger budgeted
power consumption, trimming is still generally required for BJT-based BGR because of the existence of
mismatch and offset [13].
In this paper, an ultra-low power, high accuracy BGR is presented. The proposed reference
provides a 1.17 V output under 2.8 V supply voltage with 78 nA average current consumption.
An on-off bandgap combined with sample-and-hold switched-RC filter is developed to reduce power
consumption and noise. The on-off mechanism increases the working current of the BJT-based BGR
during the sample period, which decreases VBE spread. A correlated double sampling (CDS) strategy
is adopted to cancel the offset of the operational amplifier (Opamp), which is fulfilled by a sampling
capacitor block combined with chopper mechanism. The conflict between low power and high accuracy
is preliminarily settled. The theoretical foundation and specific circuit design are described in Section 2.
Section 3 presents the simulation and measurement results as well as a performance comparison.
Electronicsconclusions
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PEER
REVIEW
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Finally,
summarized
in Section 4.
junction
transistor
(BJT)-based
2.
Proposed
Bandgap
ReferenceBGR can provide a fairly precise reference voltage, but it requests
larger power consumption. When we try to budget a lower current consumption for BJT-based BGR,
2.1.
Errorwith
Analysis
the BJT-Based
BGR
resistors
veryoflarge
values are
needed, and the VBE of BJT also varies dramatically. VBE variation
introduces
large
fluctuations
to
the
voltage.
relativelycorrelated
larger budgeted
The key point of this paper is tooutput
utilizereference
the techniques
of Even
offsetfor
cancelling,
double
power
consumption,
trimming
is
still
generally
required
for
BJT-based
BGR
because
of the existence
sampling and switched-RC to improve the accuracy of the raw BGRs under stringent
power
of mismatch and
offset [13]. A conventional BJT-based BGR is employed here for demonstration.
consumption
constraints.
In this
paper,
an BJT-based
ultra-low BGR
power,
high accuracy
is presented.
The proposed
reference
The core
circuit
of the
is shown
in FigureBGR
1. The
reference voltage
generated
by it is
provides
given
by: a 1.17 V output under 2.8 V supply voltage with 78 nA average current consumption. An
R2
on-off bandgap combined with sample-and-hold switched-RC
filter is developed to reduce power
VREF = VBE2 +
∆VBE .
(1)
R1 the working current of the BJT-based BGR
consumption and noise. The on-off mechanism increases
duringconsidering
the sample period,
which
decreases
VBE spread.
A correlated
double
sampling
(CDS)
When
non-ideal
factors
relevant
with VBE
and Opamp
offset,
Equation
(1)strategy
can be
is
adopted
to
cancel
the
offset
of
the
operational
amplifier
(Opamp),
which
is
fulfilled
by
a
sampling
approximately rewritten as
capacitor block combined with chopper
mechanism.
R2 The conflict between low power and high
VREF 0 = VBE2 0 +
(∆VBE + Vos )
(2)
accuracy is preliminarily settled. The theoretical foundation
and specific circuit design are described
R1
in Section
II. Section 0III
presents
simulation
and measurement
as wellof
asMOS
a performance
where
the superscript
denotes
thethe
erroneous
quantity.
High mismatchresults
characteristic
transistors
comparison.
Finally,
conclusions
are
summarized
in
Section
IV.
can introduce considerate offsets to Opamp especially under extreme low power consumption. The V
BE
spread is also critical because it directly translates an error in VREF . The proposed circuit concentrates
2. Proposed Bandgap Reference
on canceling these two sources of errors which have large magnitudes of effects on the accuracy of
BGR output voltage.
2.1. Error Analysis of the BJT-based BGR
Figure
bandgap reference
reference (BGR)
(BGR)
Figure 1.
1. The
The basic
basic topology
topology of
of the
the bipolar
bipolar junction
junction transistor
transistor (BJT)-based
(BJT)-based bandgap
core
circuit.
core circuit.
The key point of this paper is to utilize the techniques of offset cancelling, correlated double
sampling and switched-RC to improve the accuracy of the raw BGRs under stringent power
consumption constraints. A conventional BJT-based BGR is employed here for demonstration. The
core circuit of the BJT-based BGR is shown in Figure 1. The reference voltage generated by it is given
by:
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2.2. Architecture of the Proposed BGR Circuit
2.2. Architecture of the Proposed BGR Circuit
The systematic architecture of the proposed BGR is shown in Figure 2, which consists of an
architecture
of the
proposed aBGR
is shown in Figure
2, which
of an onon-offThe
VBEsystematic
-based BGR
with chopper
mechanism,
sampling-capacitor
block,
and a consists
sample-and-hold
off VBE-based filter.
BGR with
a sampling-capacitor
block, and aclocks
sample-and-hold
switched-RC
Also,chopper
there is amechanism,
digital block
to generate the low-duty-cycle
used in the
switched-RC
filter.
Also,
there
is
a
digital
block
to
generate
the
low-duty-cycle
clocks
used
in the
onon-off BGR, which is manually designed as the analog circuits to reduce the turnover rate
of the
clocks
off
BGR,
which
is
manually
designed
as
the
analog
circuits
to
reduce
the
turnover
rate
of
the
clocks
and thus save power. The on-off BGR takes advantages of the conventional VBE -based BGR topology.
and thus
save power.
Theofon-off
BGR takes
advantages
of the conventional
VBE-based
BGR
topology.
When
consuming
dozens
microampere
(µA),
the conventional
VBE -based BGR
operates
reliably
and
When
consuming
dozens
of
microampere
(μA),
the
conventional
V
BE-based BGR operates reliably
has little process variation spread. During the hold period, the on-off BGR is turned off to save power.
and sampling-capacitor
has little process variation
During
the hold of
period,
the on-off
BGR
is turned
off to
save
The
block isspread.
based on
the technique
correlated
double
sampling
(CDS),
which
power.
The
sampling-capacitor
block
is
based
on
the
technique
of
correlated
double
sampling
(CDS),
samples twice in a working (on) period, before and after the conversion of the chopper connection
whichinsamples
twice
a working (on)
period,
after
the conversion
of the
chopper
state
the on-off
BGR,inrespectively.
Therefore,
thebefore
offset and
of the
Opamp
Vos is cancelled
out.
When
connection
state
in
the
on-off
BGR,
respectively.
Therefore,
the
offset
of
the
Opamp
V
os is cancelled
the BGR block entered the off state, the switched-RC filter takes the average of the last twice sampled
out. Whenholds
the BGR
block
entered
the(on)
off state,
filter
takes the average
of the last
voltages,
it until
next
working
state, the
andswitched-RC
gets rid of the
out-of-band
noise through
the
twice
sampled
voltages,
holds
it
until
next
working
(on)
state,
and
gets
rid
of
the
out-of-band
noise
function of filtering.
through the function of filtering.
C1
VREF
ON-OFF BGR
(Chopper machenism )
CLK_1
CLK_3
CLK_2
CLK_3
Rs
C0
C2
Sampling-Capacator
Sample-and-hold
Switched-RC Filter
Figure 2. Block diagram of the proposed BGR.
2.3. Chopper Mechanism and Correlated Double Sampling
2.3. Chopper Mechanism and Correlated Double Sampling
Figure 3 shows the implementation of the on-off BGR which employs chopper mechanism.
Figure 3 shows the implementation of the on-off BGR which employs chopper mechanism. A
A near-zero power consumption start-up structure is adopted. The parameter values of the main
near-zero power consumption start-up structure is adopted. The parameter values of the main
components in the BGR core circuit are as follows. The emitter area of Q1 and Q2 is 2 × 2 µm.
components in the BGR core circuit are as follows. The emitter area of Q1 and Q2 is 2 × 2 μm. R1 = 10
R1 = 10 kΩ and R2 = 80 kΩ. The size of MP1/2 is 8 µm/16 µm × 6 while the size of the switch transistors
kΩ and R2 = 80 kΩ. The size of MP1/2 is 8 μm/16 μm × 6 while the size of the switch transistors is
is 4 µm/1 µm × 1. The sizes of the transistors are designed to be large for good matching and low flicker
4μm/1μm × 1. The sizes of the transistors are designed to be large for good matching and low
noise. Considering the low speed characteristic of the designed circuit, the lengths of the transistors
flicker noise. Considering the low speed characteristic of the designed circuit, the lengths of the
are selected at least 3 times of the 350 nm minimum channel length for lower static leakage current.
transistors are selected at least 3 times of the 350 nm minimum channel length for lower static leakage
Under phase Φ1 and Φ2 , the BGR power cycle is controlled by the clock ON/OFF CLK as shown
current.
in Figure 3b. With the duty cycle D = 0.25% (TON = 250 us, TON + TOFF = 100 ms), a working current
Under phase Φ1 and Φ2, the BGR power cycle is controlled by the clock ON/OFF CLK as shown
of 16 uA is budgeted for the BGR block to achieve an average power consumption as low as 40 nA.
in Figure 3b. With the duty cycle D = 0.25% (TON = 250 us, TON + TOFF = 100 ms), a working current of
The base-emitter voltage of transistor Q2 is given by
16 uA is budgeted for the BGR block to achieve an average power consumption as low as 40 nA. The
base-emitter voltage of transistor Q2 is given by
I
VBE2 = VT ln( C ),
(3)
JISCA
VBE 2 = VT ln(
),
(3)
JS A
where IC and JS are the working collector current and reverse
saturation current per unit area of the
transistor,
respectively,
and A iscollector
the emitter
area.and
Wereverse
assumesaturation
the current
variation
is IX .area
Then
where IC and
JS are the working
current
current
per unit
of the
relative
error
can
be
deduced
as
in
Equation
(5).
transistor, respectively, and A is the emitter area. We assume the current variation is IX. Then the
relative error can be deduced as in Equation (5).
I + IX
VBE2 0 = VT ln( C
)
I C J+S A
IX
'
VBE 2 = VT ln(
I +I
JS A
(4)
(4)
)
ln( CJ AX )
VBE 0 − VBE
1
IX D
S
ε=
=
−1 ≈
·
,
IC
IA
VBE
IA
I(C + I)X
ln
(
)
ln
J A
ln( J A )
V ' − VBE
=
ε = BE
VBE
S
(5)
S
JS A
I D
1
−1 ≈
⋅ X ,
IC
IA
IA
ln(
)
ln(
)
JS A
JS A
(5)
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where ε represents the relative error, and IA = IC. D is the average current. When the working collector
where
the relative
error, duty
and IAcycle
= ICof
. D0.25%,
is the average
current.
theofworking
collector
currentε Irepresents
C is increased
by an on/off
the relative
errorWhen
spread
VBE is 400
times
current
I
is
increased
by
an
on/off
duty
cycle
of
0.25%,
the
relative
error
spread
of
V
is
400
times
less.
C
BE
less.
The
are controlled
controlled by
10Hz CH_CLK
CH_CLK to
cancel the
the offset
offset of
the Opamp
Opamp under
under
The chopper
chopper blocks
blocks are
by the
the 10Hz
to cancel
of the
phases
Φ
and
Φ
.
In
the
middle
of
the
on-phase
of
BGR,
the
chopper
blocks
convert
connection
phases Φ33 and Φ4.4In the middle of the on-phase of BGR, the chopper blocks convert connection status
status
from
(XX
to (XX1 —A,
theon-phase,
next on-phase,
the connection
changes
2 —A,
1 —B)
2 —B).
from (X
2---A,
1---B)Xto
(X1---A,
2---B).XIn
the In
next
the connection
status status
changes
back.
back.
Another
chopper
block
is
introduced
in
the
signal
path
of
the
designed
Opamp
to
assure
that
Another chopper block is introduced in the signal path of the designed Opamp to assure that aa
negative
negative feedback
feedback loop
loop be
be formed
formed according
according to
to the
the chopper
chopper status
status in
in the
the on-off
on-offBGR.
BGR.
VBIAS
Φ2
Φ1
Φ1
MP1
MP2
x3
VREF
Φ3 x Φ4
1
Φ2
Φ4
A
R1
Φ2
x1
R2
Φ3
x2
Φ3
Φ4
Φ4
Φ3
x3
B
x2
N=8 N=1
Q1
Start-up
Q2
Core Circuit
Designed Opamp
(a)
(b)
Figure
(a) Proposed
Proposed on-off
on-off BGR
Figure 3.
3. (a)
BGR with
with chopper
chopper mechanism;
mechanism; (b)
(b) Control
Control clocks
clocks for
for BGR
BGR power
power cycle
cycle
and
chopper
blocks.
and chopper blocks.
Figure
shows the
the sampling-capacitor
sampling-capacitor circuit
technique of
of correlated
correlated double
double sampling
sampling
Figure 44 shows
circuit using
using the
the technique
(CDS)
[14,15].
The
values
of
the
sampling
capacitors
are
selected
as
C
=
C
=
C
=
40
µm
40 (1.6
µm
(CDS) [14,15]. The values of the sampling capacitors are selected as C11= C2 =2 C0 = 040 μm × 40×μm
(1.6
In the
control
of double
sampling
clocks
CLK_1
andCLK_2,
CLK_2,whose
whoseclock
clocktimings
timingsare
are shown
shown in
in
pF).pF).
In the
control
of double
sampling
clocks
CLK_1
and
Figure
4b,
C
and
C
sample
the
output
of
the
on-off
BGR
V
before
and
after
the
chopper
connection
1
2
REF
Figure 4b, C1 and C2 sample the output of the on-off BGR VREF before and after the chopper connection
state
and TS2,, respectively,
respectively, in
in aa working
state conversion
conversion during
during T
TS1
S1 and TS2
working (on)
(on) period.
period. C
C00 samples
samples during
during the
the
interval
T
and
sums
up
the
two
sampled
voltages
in
it.
Using
Equation
(2),
only
the
Opamp
offset
S
interval TS and sums up the two sampled voltages in it. Using Equation (2), only the Opamp offset is
is
considered,
considered,
R2
R
V1 0 = VBE2 +
(∆VBE + Vos ) = Vdes + 2 Vos
(6)
R2 R1
R1 R2
'
V1 = VBE2 + (ΔVBE + Vos ) = Vdes + Vos
(6)
R1 R
R2 R1
2
0
V2 = VBE2 +
(∆VBE − Vos ) = Vdes − Vos
(7)
R1
R1
V2 ' = VBE2 +
V1 0 C + V2 0 C + V0 C = V00 ∗ 3C
R2
R
( ΔVBE − Vos ) = Vdes − 20 Vos V1 0 + V 0 2
R1 If, V00 = V0 So, V
R10 =
= Vdes ,
2
(7)
(8)
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Electronics 2019, 8, 814
'
'
'
0
If, V = V0
'
0
V1 C + V2 C + V0 C = V * 3C
'
'
So, V = V1 + V 2 = Vdes ,
2
5 of 11
'
0
(8)
where C1 = C2 = C0 = C, V 1 is the voltage on C1 which is sampled before the connection state
where
C1 = CV
2 = 0C0 = C, V1’ is the voltage on C1 which is sampled before the connection state conversion,
conversion,
2 is the voltage on C2 sampled after the conversion, V 0 is the current voltage on C0 and
V
2’ 0is the voltage on C2 sampled after the conversion, V0 is the current voltage on C0 and V0’ is the sample
V 0 is the sample voltage in next cycle on C0 . Eventually, Vdes is the original design value of VREF .
voltage
in next
cycle
on C0. Eventually,
des is the original design value of
the stable condition
0 VREF. When
0
When the
stable
condition
is reached,VV
0 is the average value of V 1 and V 2 , canceling the error of
is
reached,
V
0 is the average value of V1’ and V2’, canceling the error of VREF caused by the Opamp offset.
V
caused by the Opamp offset.
0
REF
Double Sampling-Clocks
TS1
C1
CLK_1
CLK_1
V1’
Rs
VREF
CLK_2
TS2
CLK_3
CLK_2
TS
CLK_3
V2’
CLK_3
C0
ON/OFF
CLK(Ф2)
C2
CH_CLK
(Ф3)
SamplingCapacitor
Switched-RC
Filter
(a)
(b)
Figure
sampling-capacitorcircuit
circuitalong
alongwith
withswitched-RC
switched-RC
block;
Control
clocks
Figure 4. (a)
(a) Proposed sampling-capacitor
block;
(b)(b)
Control
clocks
for
for
sampling
switches.
sampling switches.
2.4. Sample-and-Hold
Sample-and-HoldSwitched-RC
Switched-RC Filter
Filter
2.4.
Figure 55 shows
shows the
the circuit
Figure
circuit implementation
implementation of
of the
thesample-and-hold
sample-and-holdswitched-RC
switched-RCfilter.
filter.AAMOS-R
MOSis
used
to
achieve
a
high
RC
filtering
resistance
of
25
MΩ
with
small
chip
area.
To
alleviate the
the
R is used to achieve a high RC filtering resistance of 25 MΩ with small chip area. To alleviate
effect
of
injection
and
clock
feedthrough,
a
dummy
MOS
switch
M
is
added
in
series
with
the
actual
effect of injection and clock feedthrough, a dummy MOS switch M22 is added in series with the actual
switch M
M11[13].
[13].
switch
Since
the drain-bulk
drain-bulk and
and drain-source
drain-source leakage
leakage is
is critical
critical to
Since the
to the
the accuracy
accuracy and
and stability
stability of
of V
VREF
REF
output,
especially
during
a
long
hold
time
of
100
ms,
a
simple
feedback
buffer
A
is
used
to
reduce
the
1
output, especially during a long hold time of 100 ms, a simple feedback buffer A1 is used to reduce
voltage
drop.
In the
hold
phase,
thethe
bulk
and
source
through M ,
1 1are
the
voltage
drop.
In the
hold
phase,
bulk
and
sourcenodes
nodesofofMM
arebuffered
bufferedto
toVVREF
REF through M77,
eliminating
charge
leakage
at
C
.
eliminating charge leakage at CSS.
Moreover, the
the filter
filter emulates
emulates aa much
much lower
lower filter
filter pole
pole frequency
frequency by
by pulse-switching
pulse-switching them.
them.
Moreover,
Compared
to
the
RC
filter
in
Figure
2,
the
effective
pole
frequency
in
Figure
5
is
given
by
[13]:
Compared to the RC filter in Figure 2, the effective pole frequency in Figure 5 is given by [13]:
D
D
fLPFf LPF
==
2π RSS C
CSS
2πR
(9)
(9)
0.06%
S = 60
us,us,
THT+HT+
S =T100
a filter
polepole
of 0.4
cancan
be
with
with CSS==10
10pF,
pF,RRSS==2525MΩ,
MΩ,and
andDD= =
0.06%(T(T
100 ms),
a filter
of Hz
0.4 Hz
S = 60
S = ms),
achieved,
which
is
about
two
decades
lower
than
the
noise
integration
bandwidth.
Consequently,
be achieved, which is about two decades lower than the noise integration bandwidth. Consequently,
out-of-band
out-of-band noise
noise could
could be
be filtered
filtered more
more thoroughly.
thoroughly.
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A1
VREF1
M5
VREF2
M
M5 6
CLK_3_
VREF2
CLK_3
M6
CLK_3_
M1
VBUF
M1
Vbias
CLK_3
CLK_3
M7
M2
M2
VREF
Vbias
CLK_3_
M4
A1
CLK_3_
M7
CLK_3_
CLK_3_
VREF1
VBUF
CLK_3
CLK_3
M4
CLK_3_
M3
MOS-R
M3
CS
VREF
TS=60us & TS+TH=100ms
TS VBUF
TH
MOS-R
CS
T =60us & T +T =100ms
T
S
H
S
Figure 5. Proposed sample-and-hold
switched-RCS filter circuit
and control clock timing.
CLK_3
TH
3. Simulation
and Measurement Results
Figure 5. Proposed sample-and-hold switched-RC filter circuit and control clock timing.
Figure 5. Proposed sample-and-hold switched-RC filter circuit and control clock timing.
The Offset-Cancelation Switched-RC Bandgap Reference presented in this paper has been
3. Simulation and Measurement Results
applied
in an and
implanted
cardiac pacemaker
ASIC, featured with low power, high reliability and low
3. Simulation
Measurement
Results
TheConsequently,
Offset-Cancelation
Switched-RC
Bandgap is
Reference
presented
innot
thisadvanced
paper hasbut
been
applied
speed.
0.35 μm
CMOS technology
employed,
which is
adequately
Offset-Cancelation
Switched-RC
Bandgapwith
Reference
presented
in this paper
hasspeed.
been
inqualified
anThe
implanted
cardiac
pacemaker
ASIC,
low battery
power,
high areliability
and low
for such
applications
[1,2].
Also,featured
a lithium-iodine
with
typical supply
voltage of
applied
in
an
implanted
cardiac
pacemaker
ASIC,
featured
with
low
power,
high
reliability
and
low
Consequently,
0.35 used
µm CMOS
technology
is employed,
which
advancedlevel
but adequately
qualified
2.8V is usually
for cardiac
pacemakers,
which
hasis anot
sufficient
of safety and
good
speed.
0.35 μm
CMOS technology is employed, which is not advanced but adequately
for
suchConsequently,
applications
[1,2].
Also,
discharging
characteristics
[4]. a lithium-iodine battery with a typical supply voltage of 2.8 V is
qualified
for
such
applications
[1,2]. Also,
a lithium-iodine
battery
with
a typical
supply
voltage of
usually
used
forBGRs
cardiac
pacemakers,
which
hassettling
a sufficient
level
of
safety
and good
discharging
For
on-off
with
small duty cycles,
the
time for
start-up
is usually
concerned.
Figure
2.8V
is
usually
used
for
cardiac
pacemakers,
which
has
a
sufficient
level
of
safety
and
good
characteristics
[4].
6 shows the transient output voltage of the proposed circuit at the supply voltage of 2.8 V and
discharging
characteristics
[4].
For on-off
BGRs
with
cycles,
thetosettling
time forstate.
start-up
is usually
Figure
6
temperature
of
27 °C.
It small
takes duty
about
0.6 ms
reach steady
Monte
Carlo concerned.
200 simulation
runs
For
on-off
BGRs
with
small
duty
cycles,
the settling
time
start-up
is usually
concerned.
Figure
shows
transient
output
voltage
of the
proposed
circuit at
thefor
supply
voltage
of 2.8 Vand
andmismatch.
temperature
have the
been
done after
layout
parasitic
extraction,
considering
the
process
variation
The
6 shows
the
transient
output
of the proposed
circuit
at the
voltage
of have
2.8 Vbeen
and
of
27 ◦ C.are
It takes
aboutin
0.6Figure
ms voltage
to7a.
reach
Monte
Carlo
200supply
simulation
runs
results
presented
Thesteady
mean state.
value (μ)
of the
proposed
BGR is 1.1689
V with the
temperature
of
27
°C.
It
takes
about
0.6
ms
to
reach
steady
state.
Monte
Carlo
200
simulation
runs
done
after deviation
layout parasitic
extraction,
theofprocess
variation
and mismatch.
The
results
standard
(σ) of 4.6
mV, andconsidering
the coefficient
variation
is calculated
to be about
0.39%.
The
have
been done
after
layout
parasitic
extraction,
considering
the process
variation
and
mismatch.
The
are
presented
in
Figure
7a.
The
mean
value
(µ)
of
the
proposed
BGR
is
1.1689
V
with
the
standard
simulated temperature dependence of the output reference voltage VREF is plotted in Figure 7b. The
results are(σ)presented
Figure
7a. The mean
value (μ) calculated
of the proposed
BGR0.39%.
is 1.1689
Vsimulated
with the
deviation
4.6 mV,inand
theofcoefficient
of variation
be about
The
temperatureofcoefficient
(TC)
the proposed
BGR is is
9.43 ppm/°Cto
with
temperature
ranging
from –
standard
deviation
(σ)
of
4.6
mV,
and
the
coefficient
of
variation
is
calculated
to
be
about
0.39%.
The
temperature
20 to 80 °C.dependence of the output reference voltage VREF is plotted in Figure 7b. The temperature
simulated
temperature
dependence
of
the
output
reference
voltage
V
REF
is
plotted
in
Figure
7b.
The
coefficient (TC) of the proposed BGR is 9.43 ppm/◦ C with temperature ranging from −20 to 80 ◦ C.
temperature coefficient (TC) of the proposed BGR is 9.43 ppm/°C with temperature ranging from –
20 to 80 °C.
Figure 6. The output voltage of the proposed circuit.
Figure 6. The output voltage of the proposed circuit.
Figure 6. The output voltage of the proposed circuit.
Electronics
2019,
8, 814
Electronics
2019,
8, x FOR PEER REVIEW
7 of
11 11
7 of
(a)
(b)
Figure
7. (a)
200200
Monte
Carlo
simulation
results.
(b) Temperature
coefficient
simulation
at 2.8at
V 2.8V
supply.
Figure
7. (a)
Monte
Carlo
simulation
results.
(b) Temperature
coefficient
simulation
supply.
The proposed BGR circuit is implemented in 0.35 µm standard CMOS process. Figure 8 shows the
2 , which could be optimized
BGR micrograph
of the
die.circuit
The core
circuit occupies
area
0.063 mm
The proposed
BGR
is implemented
in an
0.35
μmofstandard
CMOS
process. Figure 8 shows
2, which
after
an
elaborate
layout
design.
The
total
current
consumption
is
measured
as
78
nA on
average
frombe
the BGR micrograph of the die. The core circuit occupies an area of 0.063 mm
could
30optimized
samples. The
digital
clock
generation
block
consumes
26
nA
average
current,
which
means
thaton
after an elaborate layout design. The total current consumption is measured as 78 nA
theaverage
percentage
overhead
consumption
by block
the clock
generation
is 33.3%
or which
one
from of
30the
samples.
The power
digital clock
generation
consumes
26 nAblock
average
current,
third.
Figure
9
shows
the
distribution
of
the
measured
output
voltage
in
30
samples
with
2.8
V
supply
means that the percentage of the overhead power consumption by the clock generation block is 33.3%
voltage
27 ◦ C.Figure
The mean
valuethe
(µ)distribution
is 1.167 V with
the measured
standard deviation
(σ) of 8.1
The proposed
or oneatthird.
9 shows
of the
output voltage
in mV.
30 samples
with 2.8
BGR
can achieve
an accuracy
0.69%
in value
the measurement.
accuracy
of 0.69%
is achieved
without
V supply
voltage
at 27 °C. of
The
mean
(μ) is 1.167 VThe
with
the standard
deviation
(σ) of
8.1 mV.
trimming
and
could
be
considered
to
be
adequate
for
most
implantable
biomedical
electronics.
The
low is
The proposed BGR can achieve an accuracy of 0.69% in the measurement. The accuracy of 0.69%
power
feature
is obtained
due to
thecould
low duty
cycle (D =to
0.25%)
operation
the on-off
BRG. Moreover,
achieved
without
trimming
and
be considered
be adequate
forofmost
implantable
biomedical
theelectronics.
following correlated
double
sampler
and
the
switched-RC
filter
just
consume
about
12
nA
average
The low power feature is obtained due to the low duty cycle (D = 0.25%) operation
of the
2 chip area of the total 0.063 mm2 chip area, but guaranteed the
current
and
occupy
about
0.03
mm
on-off BRG. Moreover, the following correlated double sampler and the switched-RC filter just
good
performance
the
on-offcurrent
BRG. The
on-off BGR
untrimmed
of
consume
about 12ofnA
average
and occupy
aboutachieves
0.03 mm2an
chip
area of the measured
total 0.063 accuracy
mm2 chip area,
0.69%,
which
is
comparable
with
the
accuracy
of
BGRs
with
current
consumptions
of
hundreds
of
but guaranteed the good performance of the on-off BRG. The on-off BGR achieves an untrimmed
times
larger,accuracy
just at aof
small
price.
measured
0.69%,
which is comparable with the accuracy of BGRs with current consumptions of
hundreds of times larger, just at a small price.
Electronics 2019, 8, x FOR PEER REVIEW
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8 of 11
Figure 8. Microphotograph of BGR chip.
Microphotograph of
of BGR
BGR chip.
chip.
Figure 8. Microphotograph
Figure 9. Measured results for 30 samples.
Figure 9. Measured results for 30 samples.
Figure 10 shows VREF versus
temperature
ranging
−20
to 80 ◦ C and the measured TC ranges
Figure
9. Measured
resultsfrom
for 30
samples.
◦
◦
Figure
10
shows
V
REF versus
temperature
ranging
from
–20
to◦80
and the
measured
TC ranges
from 13.7 ppm/ C to 38.2 ppm/ C with an average TC of 19.6 ppm/
C. °C
Figure
11 shows
the measured
◦
from
13.7
ppm/°C
to
38.2
ppm/°C
with
an
average
TC
of
19.6
ppm/°C.
Figure
11
shows
the
measured
reference
voltage
versus
supply
voltage at
27 C. from
When–20
thetosupply
voltage
changes from
1.8 V
Figure
10 shows
VREFthe
versus
temperature
ranging
80 °C and
the measured
TC ranges
reference
voltage
versus
the
supply
voltage
at
27
°C.
When
the
supply
voltage
changes
from
1.8
V to
to 3.213.7
V, the
BGR voltage
variation
is less
than 0.83
Theppm/°C.
reference
voltage
can achieve
the line
from
ppm/°C
to 38.2 ppm/°C
with
an average
TCmV.
of 19.6
Figure
11 shows
the measured
3.2
V,
the
BGR
voltage
variation
is
less
than
0.83
mV.
The
reference
voltage
can
achieve
the
line
regulationvoltage
of 0.59 versus
mV/V. the
For supply
measurement
when
the power
supply
reference
voltageconvenience,
at 27 °C. When
themeasuring
supply voltage
changes
fromrejection
1.8 V to
regulation
of
0.59
mV/V.
For
measurement
convenience,
when
measuring
the
power
supply
rejection
ratioV,(PSRR),
thevoltage
on-off period
is setisatless
10 ms
instead
of 100The
ms,reference
which willvoltage
not affect
authenticity
of
3.2
the BGR
variation
than
0.83 mV.
canthe
achieve
the line
ratio
(PSRR),
the
on-off
period
is
set
at
10
ms
instead
of
100
ms,
which
will
not
affect
the
authenticity
the measured
results.
Figure
12 shows the convenience,
PSRR results,when
whichmeasuring
is better than
58.6 dBsupply
before rejection
200 kHz.
regulation
of 0.59
mV/V.
For measurement
the power
of theare
measured
results.
Figure
12 shows
thems)
PSRR
results,
which
is betterofthan
58.6 dB When
beforethe
200
There
peaks
at
multiples
of
100
Hz
(1/10
due
to
the
characteristic
sampling.
ratio (PSRR), the on-off period is set at 10 ms instead of 100 ms, which will not affect the authenticity
kHz. There
at multiples
ofsupply
100 Hzis(1/10
ms) due
to the
characteristic
of effect
sampling.
When
the
frequency
ofare
thepeaks
fluctuation
on the
same
as the
sampling
rate,than
the
of the
supply
of
the measured
results.
Figure
12 shows
the the
PSRR
results,
which
is better
58.6 dB
before
200
frequency
of
the
fluctuation
on
the
supply
is
the
same
as
the
sampling
rate,
the
effect
of
the
supply
fluctuation
on the
sampled
output
is alsoms)
thedue
same
during
the on phase
in every When
sampling
kHz.
There are
peaks
at multiples
ofvoltage
100 Hz (1/10
to the
characteristic
of sampling.
the
fluctuation
on the
sampled
output voltage is also the same during the on phase in every sampling
period
and
thus
will
be
attenuated.
frequency of the fluctuation on the supply is the same as the sampling rate, the effect of the supply
period
thus will be
Theand
performance
ofattenuated.
theoutput
proposed
BGRiscircuit
is same
summarized
in Table
1, and
are
fluctuation
on the sampled
voltage
also the
during the
on phase
in these
everyresults
sampling
The
performance
of the proposed
BGRFrom
circuit
is summarized
in Table
1,
and
these
results
are
compared
with
other
published
references.
Table
1,
it
is
observed
that
this
work
has
the
best
period and thus will be attenuated.
compared
with
other
published
references.
From
Table
1,
it
is
observed
that
this
work
has
the
best
line regulation
and temperature
coefficient
the untrimmed
voltage
references,
it also has
The performance
of the proposed
BGR in
circuit
is summarized
in Table
1, and while
these results
are
line
regulation
and
temperature
coefficient
in
the
untrimmed
voltage
references,
while
it also has
advantageswith
in the
aspects
of current
consumption
untrimmed
accuracy.
However,
thehas
limitations
compared
other
published
references.
From and
Table
1, it is observed
that
this work
the best
advantages
the aspects
of current
consumption
and
untrimmed
However, the limitations
of
such
on-offinBGR
analyzed
as
follows.
First,
small
ripplevoltage
ataccuracy.
the switching
exists
line
regulation
and are
temperature
coefficient
in
theauntrimmed
references,moment
while itstill
also
has
of such
on-off BGR
are analyzed
as follows. First,
a small ripple
at theshould
switching
moment still
exists
after
switched-RC
filtering.
For
continuous-time
applications,
this
issue
be
considered.
Second,
advantages in the aspects of current consumption and untrimmed accuracy. However, the limitations
after switched-RC
filtering.
For
continuous-time
applications,
this issue
should
be considered.
because
the BGR
output
voltage
is
the acapacitor,
it hasatlimited
driving
ability.
of
such on-off
BGR
are analyzed
assampled
follows. in
First,
small ripple
the switching
moment
still exists
Second, because the BGR output voltage is sampled in the capacitor, it has limited driving ability.
after switched-RC filtering. For continuous-time applications, this issue should be considered.
Second, because the BGR output voltage is sampled in the capacitor, it has limited driving ability.
Electronics 2019, 8, x FOR PEER REVIEW
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Figure 10. Measured reference voltage versus temperature for 30 samples.
Figure 10. Measured reference voltage versus temperature for 30 samples.
Figure 10.
10. Measured
Measured reference
voltage
versus
temperature
for 30for
samples.
Figure
reference
voltage
versus
temperature
30 samples.
Figure 11. Measured reference voltage versus the supply voltage.
Figure 11.
11. Measured
Measured reference
voltage
versus
the the
supply
voltage.
Figure
reference
voltage
versus
supply
voltage.
Figure 11. Measured reference voltage versus the supply voltage.
64
63 64
64
62 63
PSRR (dB)
PSRR
PSRR
(dB)(dB)
63
61 62
62
60 61
61
59 60
60
58 59
59
57 58
58
56 57
57
55 56
1
10
55
56 1
10
2
3
10
10
4
10
5
10
Frequency
(Hz) 4
3
5
10
10
10
10
Frequency
(Hz)
55 1
2
3
4
5
Figure
Measured
power
ratio
(PSRR).
12.12.Measured
power
supplyrejection
rejection
ratio
(PSRR).
10 Figure
10
10 supply
10
10
Frequency
(Hz)
Figure 12. Measured power supply rejection ratio (PSRR).
2
Figure 12. Measured power supply rejection ratio (PSRR).
6
10
6
10
6
10
Electronics 2019, 8, 814
10 of 11
Table 1. Comparison table.
Parameter
[16]
[17]
[18]
[19]
This Work
Process
Publication Year
Accuracy (σ/µ)
Type
TC (ppm/°C)
Supply
Output Voltage
Current Consumption
Line regulation
65 nm
JSSC 2017
0.39%(T)
VTH
5.6(T)
0.8 V
428 mV
16.3 µA
1 mV/V
180 nm
TCAS-II 2015
3.9%(UT)
VTH
64(T)
0.45 V
120 mV
32.4 nA
1.2 mV/V
130 nm
ISSCC 2015
0.67%(UT)
VBE
75(UT)
0.5 V
500 mV
64 nA
10 mV/V
180 nm
TCAS-II 2017
2%(T),1
VTH
84.5(UT)
0.4 V
212 mV
480 nA
2 mV/V
350 nm
2019
0.69%(UT)
VBE
19.6(UT)
2.8 V
1.17 V
78 nA
0.59 mV/V
(T) :
trimmed.
(UT) :
untrimmed. 1 : 3σ.
4. Conclusions
An ultra-low power, high accuracy BGR designed for implantable medical electronics is presented
in this paper. To solve the conflict between low power and high accuracy, an on-off bandgap combined
with sample-and-hold switched-RC filter is developed. A higher working current is allowed to
alleviate VBE spread, which directly causes error to output voltage, but also keeps the average power
consumption as low as 220 nW with the voltage supply of 2.8 V. Furthermore, to improve the accuracy
ulteriorly, the error brought by the Opamp offset is eliminated by applying correlated double sampling
strategy. As a result, the measured voltage accuracy of 0.69% is achieved without trimming, which is
adequate for most implanted medical electronics. The circuit shows a line regulation of 0.59 mV/V in
the supply voltage range of 1.8–3.2 V and a TC of 19.6 ppm/◦ C in the temperature ranging from −20 to
80 ◦ C. The proposed BGR circuit meets all the requirements of implantable medical electronics. It is
very suitable for application in biomedical systems.
Author Contributions: Conceptualization, J.X. and R.Z.; investigation, M.W. and S.W.; writing—original draft
preparation, J.X. and Y.W.; writing—review and editing, G.Z. and C.-F.Y.; project administration, R.Z.
Funding: This research was funded by National Natural Science Foundation of China (Grant No. 61774126),
Core Electronic Devices, High-end General Chips and Basic Software Products Projects of China (Grant No.
2017ZX01030204), and the Fundamental Research Funds for the Central Universities.
Conflicts of Interest: The authors declare no conflict of interest.
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