Homework Assignment 3
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Table 1: Process parameters for hand calculation problems.
Transistor
µ (cm2/Vs)
Cox (F/cm2)
Vth (V)
 (V-1)
NFET
PFET
250
200
2.5 × 10−6
2.5 × 10−6
0.3
-0.3
0.1
0.1
Question A. Charging and discharging a capacitor using nFET. Use minimum channel
length for the nFET. Use VDD=0.8 V. Simulation using FreePDK45.
1. Consider the nFET circuit shown in Fig. 1. The gate of the nFET is connected
to VDD = 0.8 V so it is turned on. A capacitor of 10 fF is attached to one of its
output terminals, while the other output terminal has a voltage V1. The pulse
voltage varies between 0 and VDD, as shown in Fig. 1. Assume the initial
voltage condition across the capacitor to be 0 V. Plot the result of Vout versus
time.
2. What is the maximum output voltage when V1 = VDD = 0.8 V? Explain your
answer.
3. Find the time that it takes to charge and discharge the capacitor by 50% of its
steady state value?
Figure 1: nFET circuit for Question A. The body of the nFET is connected to the ground.
Assume Vout(t = 0) = 0 V. Assume that the rise and fall times of the pulse V1(t) are 10 ps.
Question B. Charging and discharging a capacitor using pFET. Use minimum channel
length for pFET. Use VDD=0.8 V. Simulation using FreePDK45.
1. Consider the pFET circuit shown in Fig. 2. The gate of the pFET is connected
to ground so it is turned on. A capacitor of 10 fF is attached to one of its output
terminals, while the other output terminal has a voltage V1. The pulse voltage
varies between 0 and VDD, as shown in Fig. 2. Assume the initial voltage
condition across the capacitor to be VDD = 0.8 V. Plot the result of Vout versus
time.
2. What is the maximum output voltage when V1 = VDD = 0.8 V? Explain your
answer.
3. Find the time that it takes to charge and discharge the capacitor by 50% of its
steady state value?
Figure 2: pFET circuit for Question B. The body is connected to VDD. Assume Vout(t = 0) = VDD =
0.8 V. Assume that the rise and fall time of the pulse V1(t) are 10 ps.
Question C. Transient simulation of CMOS inverter using FreePDK45. Use minimum
channel length for both nFET and pFET.
1. Attach a 5 fF capacitive load at the output of the inverter. Use supply voltage
VDD = 0.8 V. Consider the input signal shown in Fig. 1 with equal rise and fall
times of 10 ps. Size the inverter for equal low-to-high and high-to-low delay
times. Report W p/W n of this inverter. Such an inverter is called balanced
inverter.
2. Vary the rise time (keep fall-time of the signal constant at 10 ps). Measure the
high-to-low delay at the output. Plot the high-to-low delay for rise time of 0.1
ps, 50 ps, 100 ps, 150 ps, 250 ps, 500 ps. Do you see the effect of finite input
slew on delay?
3. Consider the rise and fall time of the input signal to be 200 ps. Re-size the
inverter to achieve equal low-to-high and high-to-low delay. Is there any
difference from the required value of W p/W n found in Part (1) of this problem?
4. Now consider the inverter driving another similarly sized inverter as shown in
Fig. 3. The sizing of both inverters is that found in Part (1) above. Do not attach
any extra capacitance at the output of first inverter. Find the low-to-high and
high-to-low delay of the first inverter. Consider the input signal for the first
inverter as shown in Fig. 1 with equal rise and fall time of 10 ps.
5. Increase the widths of all transistors in Part (4) by 5 times. Repeat the problem
in Part (4). Explain your observation.
Figure 3: Inverter driving another inverter for Part (4) of Question C.
6. Consider the single inverter stage in part (1) above. Connect a capacitor at its
output node that is 10 fF. Consider a pulse input to the inverter as shown in
Fig. 1. The rise and fall times of the input signal are both 10 ps. Determine the
dynamic and short-circuit energy dissipation of the first inverter. For shortcircuit energy dissipation, consider that the switching occurs between 10% to
90% of VDD.
Question D. Ring oscillator design using FreePDK45.
Consider a three-stage ring oscillator as shown in Fig. 4, where the inverter circuits are
identical. The ring oscillator circuit exhibits steady-state voltage oscillations. The frequency of
oscillations is given as
1
𝑓=
2𝑛𝜏𝑖𝑛𝑣
where n is an (odd) number of stages in the ring-oscillator and τinv is the delay of the inverter.
Implement the ring oscillator in CADENCE using FreePDK45. Assume that the inverters have
the size you obtained in Question C, Part (1). Run a transient simulation to plot the voltage at
node denoted as “Output”.
Figure 4: A three-stage CMOS ring oscillator.
1. Use the transient simulation results to determine the frequency of oscillation
at VDD = 0.8 V. Determine the switching power dissipation of the circuit. Note
the switching power will include both charging/discharging dynamic power as
well as the short-circuit power.
2. Reduce the supply voltage of each inverter from VDD = 0.8 V to 0.2 V in steps
of 0.2 V. For each supply voltage, report the value of the frequency. Plot the
frequency as a function of VDD. Does the frequency increase or decrease by
reducing VDD. Explain your observation.
Question E. Hand calculation.
Assume a long-channel nFET is used to charge a large capacitor CL as shown in Fig. 5 (left).
Using the data in Table 1, answer the following questions. Consider that the body of the nFET is
connected to the ground. Ignore both channel length modulation and body effect. Use VDD = 1.2
V.
1. Determine the low-to-high delay (tpLH) of the output signal assuming an ideal
input step of 0 V to VDD = 1.2 V at the gate terminal of the transistor. Assume
that the intrinsic/parasitic capacitance of the transistor is negligible compared
to CL.
2. Assume that the load capacitor scales with the width of the transistor. That is,
CL = C0×W, where C0 is the process dependent parameter and W is the
transistor width. If tpLH = t0 for W = W 0, how does tpLH change if W is increased
to 5W 0.
3. Now assume a long-channel pFET is used to discharge the capacitor CL= 5 fF
that is initially charged to VDD, as shown in Fig.5 (right). The pFET dimensions
are W p = W n=100 nm and L=50 nm. Determine the high-to-low (tpHL) delay of
the circuit. Ignore the body effect and channel-length modulation.
Figure 5: (left) An input pulse is applied at the gate of the nFET. The output capacitor is initially
discharged. (right) An input pulse is applied to the gate of the pFET. The capacitor is initially
charged to VDD.