Digital Design with Verilog HDL
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Contents
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Design Levels & Design Flow
Module, Data Types, Operators
Lexical Conventions
Operators
Modeling Styles
Testbenches
Finite State Machine
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Digital Design with Verilog HDL
Design Levels & Design Flow
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Design Levels
Level
Modeling Object
System
Structural Circuit
Example of
Modeling Object
RAM
bus
CPU
Mathematical
Apparatus
Queuing theory
HDL
SystemVerilog,
SystemC
Add
RegisterTransfer
Functional
Circuits on the
level of multibit
devices
Accumulator
Input
Command Register
+1
Command Counter
Boolean Algebra
Gate
Circuit on the
level of gates and
flip-flops
Verilog,VHDL
J
K
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Design Levels (2)
Level
Circuit
Modeling Object
Example of
Modeling Object
Electrical Circuit
Mathematical
Apparatus
HDL
System of
differential
equations
Spice
n+
p+
Device
n
IC Components
n+
p
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System of
differential
equations with
partial
derivative
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Classification of Digital Design
◼ Full Custom
High
High
Low
– How to make transistors using the target technology?
– How to design circuits from the scratch?
– Field-programmable gate array (FPGA), complex
programmable logic device (CPLD), …
• How to use the logic elements available in the
device?
– How to map the logic elements into the target
device?
Low
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Final price per product
◼ Programmable Logic
Design Time
– Standard cell, gate array, …
• How to use the logic gates provided in the library?
– How to connect them?
– How to place them?
Performance
◼ Semi Custom
High
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Hardware Description Language (HDL)
◼ HDL
– Hardware description language that is used to model a piece of hardware
– VHDL, Verilog HDL, …
◼ Hardware modeling and design
– System or algorithm modeling (behavioral or functional level)
– Logic synthesis (Register Transfer Level(RTL) or gate level)
•
•
•
•
•
library components (Samsung, NEC, Altera…)
design optimization w.r.t. speed, area, power, etc.
synthesis tools(Synopsys, Cadence, Altera..)
use only a subset of the language
save time and money, allows easy prototyping and initial estimates
◼ Simulation at several different levels
– RTL, logic level, switch level..
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Synthesis and HDLs
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Front-end
Algorithm
General Flow of the Cell-based Design
Back-end
You will experience these steps
with focusing on the first one.
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