Lab report 1
Introduction
Main Ideology of this lab was to get us comfortable with making circuits in Cadence. We should
be able to simulate a circuit electronically in the Cadence with various types of voltage sources.
We will also get some handful experience with ModelSim, a HDL software which will we will use
later in the semester
Schematic
We were given a schematic of a circuit as the part of prelab and were asked to run various analyses
depending on the voltage source. We measured the voltage on three different points V in, Vmid, Vout
marked on the schematic.
Image above gives the circuit constructed in the Cadence which was also given to us in the
prelab.
Simulation
DC Response
We ran an analysis with DC voltage supply from the “Vsource” component. The simulation
measured various values from 0V to 5V.
According to the graph above, we can see that the Vout and Vmid are half of the value measured for what we
have for Vin at that instant. This is similar to what we wanted in the prelab. We can see that Vmid and Vout
have the same graph just like the predictions in the prelab. We can also observe that 𝑉𝑖𝑛 =
1
2
∗ 𝑉𝑜𝑢𝑡 at
every instant just like we calculated in the prelab.
The reason it satisfies our predictions is because the 𝑅1 ||𝑅2 = 5𝑘Ω and Thevenin Resistance for the circuit
is 10kΩ. In other words, its two resistors of 5kΩ each connected in series, hence the voltage drop across
each resistor would be equal.
AC Response
We ran an analysis with AC voltage supply from the “Vsource” component.
According to the graph we can observe that the graph follows the characteristics of a low pass filter which
was also we predicted in the prelab. We supplied the voltage of 1Vpk-pk from the Vsourse at the frequency
range of 1m Hz to 1M Hz. The corner frequency to be 1592 Hz in the prelab. According to the graph above
we can observe that there is a voltage drop at Vmid and Vout , which tells our calculations are right for the
ideal conditions. We can also observe that Vout has a larger drop than Vmid which also coincides with the
properties of the low pass filter.
Transient Response
We ran a transient analysis with step voltage supply from the “Vsource” component.
According to the graph above we can see that Vout and Vmid are unit step functions with slight delay similar
to what we predicted in the prelab. We can also observe that Vout has more delay than Vmid , which is because
of the resistor R3 connected after Vmid . This extra resistor delays the process even further for the voltage
every time it increases or decreases.
ModelSim
We were asked to make an inverter through Verilog using the ModelSim software. In the images
above we can see the code we used to create the inverter. In the image in the left we have the
code for the inverter, and the code on the right is the function used for the test bench simulation
for the same.
Image above gives us the output for the testbench simulation for the inverter we created. We can clearly
see the output signal (B) is the inversion of the input signal (A) stating the program we created is working
correctly without any errors.
Appendix- Prelab