Labview FPGA FOC Implementation for Synchronous
Permanent Magnet Motor Speed Control
Matheus Alexandre Bevilaqua
Ademir Nied, José de Oliveira
Whirlpool Corporation, Motors Team
State University of Santa Catarina - UDESC
Joinville, SC, Brazil
matheus.bevilaqua@gmail.com
Grupo de Controle de Sistemas - GCS
State University of Santa Catarina – UDESC
Joinville, SC, Brazil
email.ademir@gmail.com, jose.oliveira@udesc.br
Abstract — this paper describes an implementation of FOC
(Field Oriented Control) algorithm for speed control of a
Permanent Magnet Synchronous Motor - PMSM. The motor
considered is a Brushless-AC type - BLAC, with sinusoidal
back-electromotive force - BEMF waveform, and the application
intended for this motor is the direct drive - DD type of washing
machines. The FOC algorithm is implemented using a National
Instruments Labview FPGA System. This system is composed of
a high level/high productivity tool for FPGA logic synthesis. The
paper describes the design principles for FOC algorithm and
then explains the implementation of the designed controllers in
the Labview FPGA platform. Experimental results are provided
to verify the FOC implementation.
Labview, FPGA, FOC, BLAC, Electric Drives
I.
INTRODUCTION
The FOC algorithms have been used widely in the Electric
Drives Industry in the recent years. As this technology
becomes increasingly popular new applications arises, even
where cost is a hard restriction. One of these new applications
is the direct-drive type of washing machines. In this type of
drive system, there is not a mechanical transmission interface
e.g., belts or gearboxes, between the motor and the washing
machine drum. The motor most commonly used in the
appliance industry for this application is a permanent magnet,
sinusoidal BEMF – BLAC type. The use of direct-drive
BLAC – DD-BLAC motors improves efficiency of the
washing machine, increases the dynamic control of the speed
during tumbling or spin, as well as it allows new sensing
methodologies for washing machines that brings new
consumer benefits and makes the appliance quiet and energyefficient.
To take advantage of all benefits of FOC applied in DDBLAC motors, it is necessary to conduct a lot of research and
development activities. In this scenario, a rapid motor control
prototyping tool is recommended to save time and resources
during the development phase of electric drives.
978-1-4799-5551-0/14/$31.00 ©2014 IEEE
In this paper a complete platform for rapid motor control
prototyping based on Labview FPGA is described. It is
composed of a hardware that includes a power inverter with
braking capability and interface board for signals, a software
that implements FOC algorithm for BLAC motor and a user
interface – UI, that allow the user to set command speed, and
observe the motor signals and control variables during real
time operation.
II.
DYNAMIC MODEL OF A BLAC MOTOR
In this section, the dynamic equations that describe the
variables of interest for the FOC implementation are shown.
These variables are the motor currents in the d-q reference
frame and the rotor speed and position. In this paper the d axis
of the d-q reference frame is aligned on the rotor magnets flux.
A. Electric dynamic modeling
The direct axis current – id and quadrature axis current – iq
dynamics in a BLAC motor can be modeled as in (1) where R
is the phase to neutral resistance of the stator, Ld and Lq are
the direct axis and quadrature axis phase to neutral
inductances of the stator, vd and vq are the direct axis and
quadrature axis voltages applied to the stator, ωe is the electric
angular frequency of the stator voltages and λm is the magnets
flux constant [1], [2] and [3]:
(1)
Equation (1) can be written in terms of transfer functions
as shown in the block diagram of Fig.1. There is a coupling
mechanism between the d and q axis currents, and this
coupling is proportional to ωe . This coupling needs to be
compensated by the current controllers. A technique presented
in [4] for three phase induction motors is extended for BLAC
motors and explained in this paper.
TABLE I.
Figure 1. Block diagram of the electricc model
B. Mechanic dynamic modeling
The mechanic dynamics of an electriic motor can be
modeled by (2), where ωr is the rotor speedd, θm is the rotor
position, b is the dynamic friction coefficieent, J is the total
inertia (rotor + load), Te is the electromagnetic torque, Tl is the
load torque and Tc is the Coulomb or static toorque necessary to
start the rotation of the system:
MOTOR PARAMETERS
P
PARAMETER
VAL
LUE
UNIT
R
4.48
Ω
N – number of pole pairs
21
Ld =Lq
54.80
0
mH
Kt
7.52
Nm/A
λm
0.201
1
Vs
b
0.005
57
Nm/rad/s
J
0.300
06
Kgm²
Nominal Torque
40
Nm
Maximum current to avoid
demagnetization - Imax
8
A (peak)
The electromagnetic torque - Te produced by the motor is
proportional to the iq current imposeed to the stator. Therefore,
the speed controller is designed to actuate
a
over the iq current
controller reference – i*q to mitigaate the error between the
measured speed ωr and the referencee speed –ω*r .
(2)
In the frequency domain, the mechaniccal model can be
described by the block diagram of Fig. 2.
Figure 3. FOC Alg
gorithm
Figure 2. Block diagram of the mechaniic model
III.
CONTROLLER DESIGN
N
A. Motor parameters
To design the controllers and perforrm the dynamic
simulations it is necessary to know the m
motor parameters.
Usually, these parameters are determined ffrom experiments,
and the description of the tests performed iss out of the scope
of this paper. The reader can find complete iinformation about
procedures in the references [5] and [6]. The parameters of the
motor considered in this paper are summarizeed in the Table 1.
B. FOC algorithm
The FOC algorithm is shown on Fig. 3. In this structure
the motor currents are controlled in the d-qq reference frame.
The id current is associated with the maggnetic flux in the
motor and the id current reference – i*d is seet to zero, as in a
PMSM this flux is generated exclusively by tthe magnets in the
rotor [3].
C. Speed controller design
n this paper is of the
The speed controller used in
proportional-integral - PI action typ
pe and it is shown in the
block diagram of Fig. 4, where k p and
a k i are the proportional
and integral gains, and eωr is the sp
peed error that is input to
the controller.
Figure 4. Speed Co
ontroller
Considering Tl and Tc as externaal disturbances, the closed
loop transfer function – Tωr s , of the speed controller is
shown in (3). Considering that b<<JJ it is possible to compare
(3) to a second order system as sho
own in (4), [4]. Therefore
the gains of the controller can be written
w
as a function of the
damping coefficient ξ and bandwidth
h of the controller - ωb as
in (5) and (6), [4]. The ωb is co
onsidered as the angular
frequency that leads to a reduction of 3dB on the gain of a
transfer function.
(3)
control of the iq (that generates the torque) and id (that control
the flux) as independent variables.
The controllers are designed considering the coupling as
an external disturbance to be compensated as shown in Fig. 6.
(4)
(5)
(6)
Figure 6.
The bandwidth and damping coefficient of the controller
were determined by simulation of the mechanical model. The
design goal was to have the better dynamic response that do
not cause saturation in the control action (i*q imax ) during a
20Nm (50% of the nominal motor torque considered) step in
the load torque – Tl .
Considering the maximum motor current to not
demagnetize the rotor as imax = 8A (peak value), the controller
parameters are:
k
ω
Current controllers for iq and id
The closed loop transfer function – Tiq s , of the iq
controller is given by (7). Considering that the proportional
gain k >>R it is possible to compare (7) to a second order
system as in (4). Therefore the gains of the controller can be
written as a function of the damping coefficient ξ and
bandwidth of the controller - ωb as in (8) and (9), [4]:
(7)
=0.63; k ω =26.34; ξ=1.2; ωb =45Hz.
The step response of the designed controller is shown on
Fig. 5.
(8)
(9)
Figure 5. Step response of the ωr controller
D. Current controllers design
The d-q current controllers used in this paper are of the PI
type. These controllers have two objectives: (i) to control the
current amplitudes with high bandwidth and (ii) to de-couple
the d and q axis coupling shown in Fig. 1, allowing a better
As the Iq controller is inside a cascade loop of speed
control, the bandwidth was selected to be 10 times higher than
the speed control bandwidth. The damping coefficient was
selected to provide a good step response, with no overshoot.
Therefore, by simulations of the plant model the controller
parameters were determined as:
k
=150; k
=11521; ξ=3; ωb =450Hz.
The step response of the designed controller is shown on
Fig. 7.
Figure 8. Power inverter voltages
Figure 7. Step response of iq current controller
For surface mounted permanent magnets motors, the Ld
and Lq inductances have ideally the same value. Therefore, the
dynamics of the id and iq currents is similar as can be
observed in Fig. 6. This interesting fact allows the designed iq
controller gains to be used for id controller. It is important to
note that coupling between d and q axis currents is considered
as an external disturbance in the design procedure used in this
paper. However, these disturbances have different impacts on
the d and q axis depending on the speed. That might lead to
small adjustments on the controller gains for optimum
performance.
IV.
Substituting (11) in (12) it is possible to determine the six
constraints that the signal v0 must obey to comply (12). These
constraints are given by (13) and are shown graphically with
the voltages normalized to Vdc in Fig. 9, considering vab and
vbc as sinusoidal voltages of the same amplitude of Vdc . The
choice for the v0 signal in this paper is given by (14) and it is
shown on Fig. 9.
c1 v0 ‐2vab ‐vbc
c2 v0 vab ‐vbc
c3 v0 vab 2vbc
c4 v0 3Vdc ‐2vab ‐vbc
c5 v0 3Vdc vab ‐vbc
c6 v0 3Vdc vab 2vbc
PWM MODULATION
A Pulse Width Modulation (PWM) technique was used to
translate the voltage commands va* , vb* and vc* in PWM
commands to the switches of the power inverter. This
technique is based on a geometric approach, adding a v0
signal, producing a line-to-line voltage with a maximum peak
value equal to the DC bus voltage, optimizing its use [7].
v0
max c1;c2;c3
min c4;c5;c6
2
(13)
(14)
The power inverter voltages are shown in Fig. 8. The
relationship between the output voltages vab and vbc and the
voltages on the lower switches vag , vbg and vcg is given by
(10) and (11). The signal v0 is defined as the sum of lower
switches voltages.
vab
vbc
v0
vag
vbg
vcg
1
0
1
1 2
‐1
3
‐1
‐1
1
1
0 vag
‐1 vbg
1 vcg
1
1
‐2
1 vab
1 vbc
1 v0
(10)
(11)
Figure 9. Constraints and the v0 signal
The signals vag , vbg and vcg – modulated signals, as
defined by (11), are then compared to a triangular high
frequency (15kHz) portrait waveform to generate the PWM1,
PWM2 and PWM3 commands for the power inverter
switches.
V.
The lower switches voltages must operate in the range of 0
to Vdc . This constraint is defined by (12).
0 vag Vdc
0 vbg Vdc
0 vbg Vdc
(12)
ELECTRIC DRIVE SIMULATION
The FOC algorithm, the designed controllers and the
power inverter were simulated to verify the performance of
the electric drive. The simulation of the complete system
before a practical implementation is a very important step and
potentially save a lot of effort and resources in the laboratory.
In an industrial basis, the effort to build models and learn
the physics before going to the implementation is called
Simulation Based Design – SBD and has been incentived by
companies in the effort for operational excelllence in the recent
decades.
The ambient chosen for this electric drivve simulation was
the PSIM® software as on it is possible too integrate native
power electronics simulation capability wiith a C language
DLL where the FOC algorithm was implem
mented. This way,
the power electronics and its switched w
waveforms can be
integrated in the motor control signals for verification. This
simulation is very close to the signals tthe electric drive
engineer might expect in real-world applicatiions. An overview
of the simulation code is given in Fig. 10.
Figure 11. Simulation
n Results
VI.
FPGA IMPLEM
MENTATION
The FOC algorithm is implemen
nted in a Labview FPGA
platform, as shown in Fig. 12.
Figure 10. Electric Drive PSIM® Simuulation
A simulation result is given at Fig. 111. The motor is
accelerated to 50rpm (typical washing macchine application).
Then a 20Nm load step is applied to the mottor shaft at t=0.2s.
The speed controller rapidly recovers the sspeed and then at
t=0.4s the motor is accelerated to 100rpm. Ann overshoot of the
same order that Fig. 5 is observed. At t=0.6s the motor speed
is reduced to 50 rpm and at t=0.8s the load iis taken out of the
motor shaft.
The operation of the id and iq controllerss can be observed
during all the transients, as well as the toque and current levels
that the motor presents. It is important to note that the current
levels do not reach the demagnetization limitt (8A) in any case.
A. Hardware Implementation
d is a CompactRIO, from
The Labview FPGA system used
National Instruments. It is composed of a PC based user
interface, a real-time controller, a FP
PGA chassis and C series
modules for I/O signals.
The NI9401 module is a 100kS/ss digital I/O that is used to
read incremental encoder A, A, B, B, Z and Z signals. The
NI9205 is an analog input module iss used to read the two Hall
effect current sensors feedback.
i intended to generate the
There is an interface board that is
5Vdc supply to the incremental enco
oder, ±15Vdc to supply the
Hall sensors and PWM drivers, acqu
uire and filters the encoder
signals by differential measurement as well as to amplify the
TTL level PWM signals from the NI9401
N
module to the 15V
signals to the IGBT switches drivers..
Figure 13. Labview Block Diagram
Figure 12. Experimental setup
B. Software Implementation
The Labview FPGA system can be programmed in three
layers of software: (i) FPGA (ii) Real Time Controller - RT
and (iii) Host PC. To program all these layers, the Labview
high level language is used. For the FPGA layer, there is a
compiler that translates the Labview code in VHDL logic, and
then synthesizes the logic gates to a Virtex5™, Xilinx®
FPGA chip. This process runs automatically, without any
interference of the programmer. This way, the Labview FPGA
system allow the programmer to abstract the complex
programming details in a high productivity, high level
programming language, accelerating the code development.
Inside the FPGA layer it is possible to run program loops
at 40MHz (for the chassis used in this paper), however there
are strong restrictions in the mathematical functions available,
and the variables data types are limited to single precision
floating point (32 bits). To reach such a high speed the code
must fit inside a Labview structure called single-cycle timed
loop - SCTL. The code inside this structure executes in one
FPGA clock cycle. In addition, in the FPGA layer it is
possible to execute code outside a SCTL with rates as high as
1MHz.
The RT controller has a dedicated RT operational system
that can execute Labview Code at rates as high as 1kHz and
improves the determinism as it has a dedicated processor that
is not shared with the Host PC operational system. There is a
limited set of functions that can run inside this layer. It is an
intermediate set between the Host PC and FPGA capabilities.
The Host PC uses the computer processor to execute the
code and is susceptible to fluctuations in the execution rate, as
it shares the processor with the PC operational system. The
non-deterministic tasks as the user interface – UI are
programmed in this layer of code.
In this paper an implementation of the FOC algorithm of
Fig. 3 under the FPGA layer is explained. Software in
Labview code is called Virtual Instrument – VI, and a VI can
be composed of various sub-VIs that executes well-defined
functions.
The VI that implements the FOC algorithm is shown at
Fig. 13. It receives the measurements of motor currents and
encoder and generates the PWM modulating signals for the
PWM driver sub-VI.
Differently from most of Digital Signal Processors – DSPs
and microcontrollers developed for motor control applications
the Labview FPGA does not have drivers for encoder reading
and PWM generation. Therefore, it is necessary to program
parts of the FPGA gates to perform such functionalities.
The encoder driver VI is shown at Fig. 14. It uses a SCTL
structure that executes at a rate of 40MHz. The A and B
signals are debounced for a “Nsamples debouncing” number
of samples. Then the current A signal is compared with the
past A signal by exclusive-OR gate to check for a change in
state. The same border detection technique is performed on B
signal. Each time a border is encountered (in A or B) the
electrical position is incremented or decremented according to
the direction of rotation (clock-wise - CW or counter-clockwise - CCW). The electrical position “Position” returns to zero
when a “LimitTetaE” value is reached. This value is expressed
in (15) and depends on the encoder resolution - PPR, the
number of borders that are being considered (low to high, high
to low or both) - Nborders and the number of pole pairs of the
motor - N. In this paper LimitTetaE=380.95 as the encoder
used is 2000 pulses per revolution, the motor has 21 pole pairs
and the 4 transitions of the A and B signals are considered.
LimitTetaE
PPR*Nborders
N
(15)
The speed is measured by the period between borders in A
and B signals. This “Period” information is measured in tick
counts of the FPGA processor that runs at 40MHz loop rate.
The conversion to RPM is done by (16).
RPM
60 40 10
Period*PPR*Nborders
(16)
The PWM modulator is shown at Fig. 15. It receives the
modulating signals vag , vbg and vcg from the FOC algorithm,
compares each one to a saw tooth waveform and generates the
PWM signals to the digital outputs S1 to S6. The dead-time
between upper and lower switches of an inverter leg is defined
by the hardware driver circuit and do not need to be
implemented by the FPGA software.
In order to verify the performance of the id and iq current
controllers presented in section III-D, step response curves on
i*d and i*q reference currents are shown at Fig. 17 and Fig. 18.
The rotor was kept at standstill by external fixture to not rotate
during the i*q step response test. Note that the effect of the
coupling between d and q axis currents is rapidly compensated
by the controllers.
Figure 14. Encoder driver block diagram
Figure 17. Step response in i*d signal (from 0 to 0.4 pu)
Figure 15. PWM Modulator VI
VII. EXPERIMENTAL RESULTS
In order to verify the power inverter modulation technique
of section IV, the power inverter was commanded to generate
three-phase voltages that were applied to the stator of the
BLAC motor (without the rotor). Therefore for a passive RL
load as this, the sinusoidal three-phase voltages must produce
sinusoidal three-phase currents – Ia, Ib, and Ic on the stator
coils. The three-phase modulating signals (in pu) and the 3phase currents are shown in Fig. 16. In this case, the Vdc
voltage was set to 40V using an external AC power source to
fed the three-phase rectifier.
Figure 18. Step response in i*q signal (from 0 to 0.4 pu)
The speed controller implementation can be verified on
Fig. 19. This experimental results shows the ωr , iq , id , Ia, Ib,
Ic and Vdc parameters. The motor runs at 20rpm and in
time=4s a load torque of 21Nm is imposed on the shaft. Note
that the speed controller requests more Iq current and rapidly
compensates the load step. In time=9.5s the motor is
accelerated to 40rpm. As an induction motor with DC current
applied in the stator was used as brake mechanism, the load
torque drops to approximately 17.5Nm. When time=13s the
rotor is decelerated to 20rpm and around time=16s the load is
take off.
CONCLUSIONS
Figure 16. Power inverter modulation experimental result
This paper described a new platform implementation
(Labview FPGA) of FOC algorithm to PMSM - BLAC
motors. The current and speed controllers design procedure as
well as a power inverter modulation scheme were explained in
details. Simulation results were shown to validate the design
methodology. Experimental results provided validated the
FOC algorithm implementation. This paper opens a new
investigation path to explore the Labview FPGA capabilities
on electric machines control and power electronics.
Figure 19. Speed control experimental result
ACKNOWLEDGMENT
The authors would like to thank Whirlpool Corporation,
specially the LAR Motors Team by the availability of
equipments to develop the experimental part of this paper. The
authors also would like to thank Marcelo Campos Silva, by
the valuable technical discussions on the motor control
software implementation.
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