What is an Active Low SR Latch
An active low SR latch (or active low SR Flip Flop) is a type of latch which is SET when S = 0(LOW). An active
low SR latch is typically designed by using NAND gates. The logical circuit for a SR latch is shown below
In the above logic circuit if S = 0 and R = 1, Q becomes 1. Let us explain how.
In the above logic circuit if S = 1 and R = 0, Q becomes 0. Let us explain how.
Active Low SR Latch Truth Table
The truth table for an active low SR flip flop (i.e. SR Latch) has been shown in the table below.
What is a Gated SR Latch
A gated SR latch (or clocked SR Latch) can only change its output state when there is an enabling signal along
with required inputs. For this reason it is also known as a synchronous SR latch. Conversely, latches that can
change its state instantaneously on the application of its required inputs conditions are known as
asynchronous latches. That means the inputs can only act upon when the latch is enabled otherwise there will
be no change in output state even required inputs are applied. In other words, the latch is active when
ENABLE signal is HIGH and it is inactive when ENABLE signal is LOW. This HIGH LOW enable signal is applied to
the gated latch in the form of clocked pulses.
Gated SR Latch
So, gated S-R latch is also called clocked S-R Flip flop or synchronous S-R latch.Since this latch responds to the
applied inputs only when the level of the clock pulse is high, this type of flip-flop is also called level triggered
flip flop. The logical circuit of a Gated SR Latch or Clocked SR Flip-Flop is shown below.
Gated SR Latch Truth Table