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Regenerative Payload Processor Architectures and Technology for DVB-RCS /
DVB-S(2) Satellite Systems.
Conference Paper · June 2004
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Regenerative Payload Processor Architectures
and Technology for DVB-RCS / DVB-S(2) Satellite Systems
C. K. Leong, P.C. Marston, B. L. Combridge, C.L. Topping, I. Cameron and S. Holroyd
EADS Astrium Ltd., Gunnels Wood Road, Stevenage, Hertfordshire SG1 2AS, U.K.
and
F. Petz and X. Maufroid
ESTEC, Keplerlaan, Postbus 299, 2200 AG Noordwijk, The Netherlands
EADS Astrium has developed the WeB20001 multimedia processor architectures within
the frame of ESA programmes. The processor architectures include a regenerative mesh link
packet router based on DVB-RCS2 uplinks and DVB-S3 downlinks. This paper describes the
implementation of this mesh link packet router known as OBMM (Onboard Multimedia
Multiplexer) and the enhancement to provide DVB-S24 downlinks and accommodate ACM
(Adaptive Coding and Modulation) techniques.
I.
Introduction
A. Astrium OBMM Processor
The OBMM processor is designed to provide the satellite payload with the capability to support flexible
connectivity between small gateways and user terminals as well as a mesh link between user terminals within a
multiple beam system. The uplink from the terminals consists of a large number of low data rate DVB-RCS carriers.
Onboard the satellite, the data packets from these carriers are then regenerated, switched and time multiplexed onto
a number of high rate DVB-S downlink carriers in what is sometimes referred to as a “micro-push” architecture.
Multiple Low Rate Carriers in DVB-RCS Format.
M uplink beams or channels
Single High Rate Carriers in DVB-S Format
into N downlink beams
Beam/CH 1
Be am/CH 1
Be am/CH 2
Beam/CH 2
Small Terminals eg
SNG, Studio,
Portable
Beam/CH N
Beam/CH M
Figure 1. Micro-push services supported by OBMM.
1
In the baseline configuration, the OBMM can support 18 active input ports and 18 active outputs, each of
37.125 MHz useful bandwidth. The uplink signals are based on the DVB-RCS standard while the downlink is
formatted according to DVB-S, both standards being compatible with the use of MPEG-2 data packets. The
difference in formats therefore requires a regenerative payload. DVB-RCS uses a TDMA format and so regeneration
of the uplink packets involves burst demodulation, which is followed by turbo decoding and descrambling. A SCPC
alternative is also supported on selected channels for users requiring a higher uplink availability. The downlinks are
transmitted in DVB-S format that uses a concatenated Reed-Solomon and convolutional code. Both links employ a
shaped QPSK waveform.
To provide high flexibility coupled with a wide range of data rates, the uplink TDMA structure is complemented
by an FDMA structure (within the DVB-RCS standard) with a choice of carrier bandwidths up to 4.125 MHz. The
sampling rate at each input port provides 37.125 MHz of useful bandwidth which is separated into individual
carriers by a two-stage demultiplexer. The second stage is programmable to allow processing of different carrier
bandwidths and data rates. The overall access scheme is therefore MF-TDMA, i.e. a single terminal may use a
combination of carriers and timeslots to reach a desired bandwidth. In the baseline system, the minimum user data
rate granularity is approximately 16 kbps.
Downlink services are transmitted as TDM streams on a single high rate carrier per output port. These carriers
are fully DVB-S compliant allowing reuse of existing set-top box technology with the ground receivers.
B. Future Downlink Standard DVB-S2
The application of DVB-S2 not only allows for extra capacity due to the flexible coding and modulation options
offered, but also supports ACM which greatly benefits the link margins required for a given performance. This
allows for minimising the over budgeting needed in varying link conditions by exploiting the spatial and temporal
variability of end-user channel conditions, thus increasing the average system throughput.
To adapt the current OBMM architecture to accommodate ACM on the downlink the following areas of
investigation are of interest:
• Physical layer adaptation loop methods for minimising packet loss and maintaining a high QoS.
• Switching methods for providing versatility in interconnect, while integrating such functionality as service
priority queues, QoS queues, physical layer queues, at the cost of minimising buffer requirements and packet
delay.
• Take into account any architectural decisions which may impact the terminal, gateway, or NCC buffer size
requirements.
• Address the impact of using HPA linearisation or data pre-distortion (dynamic and static) on the payload and
processor architectures, as well as link performance implications.
• Radio Resource Management architectures and their impact on the processor and NCC.
Work is already underway under ESA programs in proposing architectures which support DVB-S2 streams.
Modified OBMM architectures for servicing mixed broadcast and interactive streams have been proposed, with the
following regenerative architectures and operating scenarios investigated:
• Simple broadcast missions with fixed code rate and modulation everywhere employing DVB-S2
• Simple broadcast missions with beam dependent coding and modulation employing DVB-S2
• Simple broadcast missions employing separate DVB-S and DVB-S2 channels
• Simple broadcast missions employing backward compliant DVB-S/2
• Interactive systems with mixed unicast and broadcast users and fixed downlink code rates and modulation
• Interactive systems with mixed unicast and broadcast users and beam by beam variable downlink code rates
and modulation
• Interactive systems with mixed unicast and broadcast users and full ACM on downlink
Note that mixed broadcast and interactive streams represent an extension of the current DVB-S2 expected
practice. Also, in the cases where DVB-RCS has been employed, no assumption has being made on the possibility
of a DVB-RCS2 standard which can support ACM, although such architectures have also been proposed.
2
II.
The OBMM Processor Design
A. Processing Functions
The OBMM functional architecture is as shown in Figure 2. Uni-directional digital links are provided between N
input and N output channels, each of 37.125 MHz useful bandwidth. The processor has a modular design that allows
processing chains to be added a pair at a time to give a wide range of N for different mission capacity requirements.
The function of the digital processor is to provide flexible packet switching both spatially (between ports) and in
time (within the TDMA frame).
Each input channel, after analogue-to-digital conversion, is demultiplexed into nine 4.125 MHz channels, each
of which may contain 1, 2 or 8 carriers. The demodulators and decoders are capable of multi-carrier operation,
thereby improving the switching granularity. The uplink receive chains feed their packet streams to the switch
hardware which first routes data to the appropriate beams (spatial switching) and then formats the downlink TDM
frame (time switching). The suitably reorganised output streams are then encoded and modulated ready for
transmission on the downlink.
Sufficient flexibility has been designed into the digital devices to accommodate a variety of service types. Each
demodulator can operate in either SCPC or TDMA (burst) mode with multiple carriers and programmable burst
lengths of between 1 to 64 bursts/frame and 1,4,8 packets/burst with a 128 symbol preamble length. Turbo-decoding
is used on the uplink with a variety of DVB-RCS compliant code rates (1/3, 1/2, 3/4, 4/5, 6/7, 7/8) and interleaving
formats, as well as descrambling for spectral energy dispersion. The downlink modulation scheme is fully
programmable and provision is made for Reed-Solomon encoding, a programmable code rate (1, 1/2, 2/3, 3/4, 5/6,
7/8) convolutional encoder and a scrambler. In particular, the system is designed to be compatible with the DVB-S
format. The baseline output bandwidth corresponds to a symbol rate of 27.5 Msymbol/sec, but it is possible to
increase this to 41.25 or 55 Msymbol/sec or to decrease it to 13.75 Msymbol/sec.
(1)
A/D
decode
buffer
(1)
(1)
demux
(9)
demod
decode
buffer
encode/
modulate
D/A
encode/
modulate
D/A
(9)
(1)
37.125 MHz
to upconversion chains
from downconversion chains
(1)
37.125 MHz
demod
Spatial
and
Time
Switch
demod
(N)
37.125 MHz
A/D
decode
buffer
(N)
demux
(9N)
S/C
TC/TM
demod
decode
buffer
Processor
Control
(9N)
ASICS
(N)
37.125 MHz
Digital OBMM
Figure 2. OBMM functional architecture.
A selection of carrier bandwidths is provided to support different service data rates. The demultiplexing requires
carriers within an input channel to be on a regular grid. The coarse demultiplexing stage divides the input sampled
bandwidth ten ways, discarding the one output that falls in the pre-processor SAW filter transition band, to give nine
evenly spaced channels of separation 4.125 MHz. This bandwidth, allowing for the QPSK modulation scheme and
the TDMA burst overhead, is sufficient to carry a 4.224 Mbps useful data rate at code rates exceeding 3/4. The
subsequent fine demultiplexing stage is capable of splitting the channel 1, 2, 4, 8 or 16 ways. For the baseline
OBMM scenario, only 1, 2 and 8 carriers per channel are used, providing 4.224 Mbps, 2.112 Mbps and 528 kbps
rates. These services are designated High Rate (HR), Medium Rate (MR) and Low Rate (LR), respectively.
3
Useful rate
Symbol rate
Carrier spacing
Low rate
527.982 kbps
401.252 ksym/s
515.625 kHz
Medium rate
2111.928 kbps
1460.376 ksym/s
2062.5 kHz
High rate
4223.856 kbps
2870.200 ksym/s
4125 kHz
Table 1. OBMM uplink carrier data rate and bandwidth.
The total data rate on each channel has the same value, independent of the number of carriers, determined by the
downlink data rate. The HR, MR and LR data rates scale exactly in inverse proportion to the number of carriers per
channel. The TDMA burst overheads are designed to ensure this by adjustment of the coding rates and guard times.
Lower data rates can in principle be accommodated by insertion of null packets. This is performed by the processor
if, for example, carriers or bursts are missing on part of the uplink. However, in order to be routed correctly by the
Time Switches, the arrangement of valid data packets must be deterministic and must repeat every frame.
Each Time Switch is able to take up to 64 inputs, each at rate 1/8 of the downlink rate, and reorder the packets
into a continuous downlink stream. For systems up to size N = 20, the number of input streams totals less than 64
and so an individual Time Switch is entirely responsible for both spatial selection and temporal switching for each
downlink stream. In a more general system, an additional layer of dynamically reconfigurable Spatial Switches are
included before the Time Switches to get the necessary port-to-port connectivity. For full flexibility, these switches
are switched dynamically to share access to any one downlink between all the uplinks.
For potential mixed SCPC/TDMA applications, whereas the TDMA accesses are switched dynamically on a
packet-by-packet basis, each SCPC carrier is routed semi-permanently to a downlink channel. There is therefore no
need to synchronise the SCPC uplink packet timing with the TDMA frame.
Signalling information in DVB-S comprises a number of control tables broadcast to all terminals or directed to
specific receive terminals. The majority of this data is generated on the ground but there are certain instances where
the OBMM is the source of the information and these are inserted directly into the appropriate packets. An example
is PCR (Programme Clock Reference) insertion. The NCR (Network Clock Reference) time value required for
network synchronization must be inserted into the appropriate field of regular and frequent PCR TS packets received
on the uplink. This is performed by the Encoder-Modulator, which maintains its own local copy of the 27 MHz NCR
clock. This clock is regularly resynchronised by serial bus command to a master reference in the OBMM controller.
The satellite must also measure the time interval between PCR TS packets on each downlink and raise an error if
this exceeds a certain threshold. In this case, the payload generates and transmits its own PCR TS packet by
overwriting any existing packet received on the uplink.
B. Key Performance
The uplink performance for the demodulator and Turbo decoder in combination is specified in terms of a “quasierror-free” output, defined as a packet error rate of less than one per hour. This is taken to mean per HR channel,
which equates to a packet error rate of better than 1 × 10-7 (or better than 8 × 10-7 for a LR channel). Demodulation
errors generally result in the loss of an entire burst and the demodulator performance is generally quoted as a burst
loss rate (BLR) while decoding errors result in a single erroneous packet so decoder performance is specified as a
packet error rate (PER).
The PER achieved can be varied by changing the uplink code rate; the number of turbo decoder iterations is
fixed at five to fit the processing time available. The maximum input Es/N0 for quasi-error-free performance in
TDMA mode is also sensitive to the length of the unique word preamble which is an important factor in the burst
loss probability. The baseline unique word (best BLR) supported by the Burst Demodulator is 128 symbols. Table 2
summarises the relative performances of Demodulator and Decoder. Phase noise is included at levels specified in the
DVB-RCS standard. The figures include a 1 dB margin to account for the degradation introduced by the processor
from the input of the A/D to the output of the decoder. This includes a budget of approximately 30 dB NPR on the
combined performance of the A/D and demultiplexing stages. At the code rate of ¾, the figures show that the packet
loss rate of the Decoder is the limiting factor.
The downlink processing functions that introduce performance degradation are modulation and D/A conversion.
The modulator’s fixed precision filter multiplications and rounding introduces a constant, uniform noise floor on the
4
output signal. ISI will be produced due to the finite filter length. For QPSK modulation, the implementation margin
of the modulator is 0.12 dB. The additional contribution of the DAC due to jitter noise and passband ripple is
expected to increase this to 0.2 dB. For higher modulation modes, the implementation margin is slightly worse
(0.2 dB in the modulator for 8-PSK).
All data processing functional blocks implemented on the ASICs have been validated using an FPGA-based
demonstrator within an overall system testbed in the ARETHUSE5 programme funded by CNES.
Code rate
Es/N0 for PER of
1 × 10-7
Es/N0 for BLR of
8 × 10-7
Critical Es/N0
Critical stage
2/3
5.9
5.9
5.9
demod / decoder
3/4
7.0
5.9
7.0
decoder
Table 2. Performance of OBMM demodulator and decoder.
C. Implementation Architecture
The OBMM is designed using the second generation Astrium packaging technology, similar to that used for the
Inmarsat4 processor (see companion paper6). The unit is divided into modules. These modules are connected
electrically via a backplane at one side and thermally via a baseplate at the other. The baseplate has embedded heat
pipes to transfer heat out of the unit.
Each module consists of a dc-dc power converter, a PCB baseboard and up to 8 multi-chip modules (MCMs),
connected to the baseboard by means of flexible cables with cinch connectors. The baseboard has space for up to
about 30 BGA packaged devices. The largest BGA package currently qualified has a maximum of 483 pins. Each
baseboard can dissipate up to about 30 W. MCMs have their own thermal path to the baseplate and can dissipate a
maximum of 8 W each. An MCM can accommodate up to 10 ASICs, depending on the die sizes.
The key implementation features of the OBMM processor are:
• The overall processing functions are partitioned into 7 ASIC designs implemented in 0.35 micron radiation
hard technology: Coarse Demultiplexer, Fine Demultiplexer, Burst Demodulator, Turbo Decoder, Spatial
Switch, Time Switch and Encoder-Modulator.
• The processing chains are partitioned into two per module using a single “Mux Module” design. This
modular design allows easy tailoring to mission-specific capacity requirements. Additional modules are
required for power and control.
• The high power Burst Demodulator and Turbo Decoder are placed on MCMs.
• Transfer between modules (and switching) is performed at the baseband bit stream level. This is the point in
the processing chain at which the bandwidth is at its minimum and therefore minimises the interconnect
requirements. The arrangement of switches on the backplane depends on the number of Mux Modules
implemented.
Figure 3 shows the overall OBMM partitioning to modules for the case of N = 24 chains. Each Mux Module
processes two input and two output chains. The time and space switching function is distributed between spatial
switching on the backplane and time switching specific to each downlink on the Mux Module. Each module has
interfaces with the backplane at its Decoder outputs and its Time Switch inputs. Additional Decoder outputs are also
routed to the controller modules, the OCT (Operation Command & Telemetry) FPGA and the ECM (Embedded
Controller Module). These connections carry dedicated TC/TM channels.
The digital processor interacts with the rest of the payload via prime and redundant MIL-STD-1553B buses. This
is used primarily to control the equipment at top level, e.g. for switching internal DSP redundancy units. Lower level
(e.g. traffic routing) parameters are normally controlled using dedicated TC/TM channels within the uplink and
downlink communications.
5
Rx chain #1
IF in #2
Rx chain #2
12:9 pairs Tx and Rx
chain redundancy
FGU in
@ 110 &
82.5 MHz
clock
& sync
gen
(1)
(1)
Mux
Module
#1
(5)
1
(1)
clocks
syncs
(60)
Backplane
switch network
IF in #1
2:1 internal
IF out #1
Tx chain #1
(7)
IF out #2
Tx chain #2
(1)
8
SBI
ECM
ECM
s/c TC/TM
ded TM
(7)
ded TC
8
OCT
ECM
IF in #23
IF out #23
Rx chain #23
IF in #24
Rx chain #24
Mux
Module
#12
Tx chain #23
IF out #24
(1)
Tx chain #24
(7)
Figure 3. OBMM implementation architecture.
D. Hardware development
The Engineering Model of the OBMM Mux module and the unit backplane with interfaces for up to 3 Mux
modules have been developed. Each Mux module comprises 10 ASICs packaged in BGA, 5 MCMs each with 4
ASIC dies, 8 SRAMs, 1 twin ADC hybrid and 1 twin DAC mini PCB module. The Mux module baseboard and
frame is as shown in Figure 4 and Figure 5 shows the Mux module with an integrated MCM in the test
configuration. The unit backplane is as shown in Figure 6.
Testing of the hardware has been completed to show successful design of the Mux module and the backplane. A
flight OBMM processor can now be developed to process up to 36 uplink channels and downlink channels. The
power and mass of the OBMM unit is < 3 kg and <50W per channel including controller and dc-dc power
conversion.
Figure 4. OBMM Mux module hardware.
6
Figure 5. Mux module with integrated MCM.
Figure 6. OBMM backplane hardware.
III.
Future enhancement of OBMM for DVB-S2
A. Supporting DVB-S2
DVB-S2 is a very flexible standard, covering a variety of applications by satellite. It is characterised by:
• Flexible stream adapter, suitable for operation with single and multiple input streams of various formats
(packetised or continuous);
• Powerful FEC system based on LDPC (Low-Density Parity Check) codes, allowing Quasi-Error-Free
operation at about 0.7 dB from the Shannon limit (AWGN channel);
• Wide range of code rates (from 1/2 up to 9/10); 5 constellations, ranging in spectrum efficiency from 1 to 5
bit/second/Hz, optimised for operation over non-linear transponders;
• Set of three spectrum shapes with roll-off factors 0.35, 0.25 and 0.20;
• Adaptive Coding and Modulation (ACM) functionality, optimising channel coding and modulation on a
frame-by-frame basis.
In the simplest case, the OBMM architecture can be extended to include the DVB-S2 downlink protocol by
replacing the switch and DVB-S encoder/modulator designs with a DVB-S2 compliant encoder/modulator and a
modified switch and switch interface. The ACM downlink processor architecture developed, separately routes
uplink broadcast MPEG streams or interactive data packets as illustrated in Figure 7.
7
TS
M ux
Route
TS Packets
to
Port
Broadcast Users
Extended
Route r
Inte ractive Users
Route
Data Packets
to
Port
Arbitration
rules
Route
To
Code/M od
Class
Encode r/Modulato r
Sub System
Input
Stream
Buffer
Switch
Broa dcast/
Inte ractive
Input
Stream
Buffers
Encapsulate
Encoding/
M odulation
M ux
Code/M od
Classes
Encapsulate
Arbitration
Control
Capacity
Rules
Figure 7. Downlink ACM stream generator for mixed interactive and broadcast services
B. ACM stream generator architecture
The broadcast packets are routed using a frame switch. At the output of the frame switch the multiple outputs are
combined into a single transport stream transferred at a rate based on the broadcast code rate and modulation
alphabet. The transport stream is fed into an input stream buffer which compiles the data field for the mode
adaptation process. The broadcast stream input buffer is periodically routed to the encoder modulator on the basis of
one data field per access.
The interactive services are routed via a separate packet based switch, the packets being ATM cells, IP
datagrams or other data structures. The packet switch could be either a frame switch or a buffered switch (for
example an ATM switch) based on the mission demands. Following the spatial routing switch there is a switch for
each downlink beam to route individual packets to code and modulation specific processing. The code/modulation
class switch is controlled by an arbitration unit which takes into account the packet identity, its channel quality
requirements, and the queue status for the various coding and modulation classes. At the output of the class routing,
buffers feed the encapsulation units. In principle, the spatial routing and class routing can be combined to form a
general packet routing switch with multiple quality of service queues.
The classified packets are buffered before being encapsulated into MPEG packets, one encapsulation per class. A
simple data piping protocol can be used for the encapsulation. The encapsulation process will place MPEG packets
into the stream buffer for the class, which in turn compiles the data field for the stream adaptation of the
encoder/modulator.
The streams for the various code/modulation classes feed into a stream multiplexer which selects one of the
streams to fill the interactive services stream when the encoder modulator is to access interactive services. The
selection of which stream may require arbitration as some class stream buffers will be full at decision time.
Both composite interactive service stream and broadcast accesses would be connected to the encoder/modulator
via a switch under the management of the controller. The mixing of interactive and broadcast steams to a single
downlink is possible, although not recommended, due to the stringent demands of the broadcast stream packet jitter.
In the event that ample buffering is offered in the interactive service stream path and an intelligent arbitrator and
controller are used, in principle the mixing of such streams can be managed.
8
C. Processor Complexity and ACM
I. Uplink to Downlink data rate matching
Although ACM offers the benefits of improved capacity via fine granularity of physical layer schemes, this also
imposes problems in guaranteeing a continuous downlink stream with minimum buffer sizes and processor
overheads for a required maximum throughput.
In addition, as a consequence of ACM, there is the potential of a higher instantaneous uplink data rate with
respect to the maximum handled downlink rate. This can be due to the effects of large adaptation loop delays, where
a change in link conditions may result in the instantaneous uplink traffic overflow in the processor buffers. In
response, the processor course of action could be one of many, depending on the choice of ACM router management
strategies and processor architecture. The routing or deleting of an uplink packet could be based one of the
following criteria,
1.
2.
3.
4.
5.
Deleting of low priority (LP) packets;
Delete packets based on stream type, (e.g. delete interactive packet as opposed to broadcast packet);
Re-routing of packets to another QoS stream with less traffic;
Upgrading of packets to higher priority (HP) streams with less traffic;
Downgrading of packets to LP streams with less traffic.
In all OBMM architectures proposed, the issues of uplink to downlink rate adaptation are of concern, and
tradeoffs are made against the requirements of minimizing buffers sizes, reducing the end-to-end packet delays
through the system, and the versatility of architectures in handling varying stream data rates while maintaining a
high QoS.
II. ACM router/Router manager
The capacity of an ACM system, for a given available power, is higher than a non ACM system. In an interactive
system the throughput will be statistical due in part to the action of ACM. The users can be classed as either constant
or variable bit rate. The constant bit rate users will use a variable number of downlink symbols to transmit the
constant bit rate service. Variable bit rate (VBR) users on the other hand may have the possibility to maintain a
constant number of downlink symbols whilst varying their effective throughput. It must be realized however that the
uplink can present a capacity bottleneck to VBR systems unless some form of ACM reservation or BTP
management scheme is in operation. The basic question for an ACM system is how to efficiently manage the
statistically available capacity. The question is very similar to that of an ATM switch which must manage QoS
under statistically varying traffic. Queuing is inevitable in such situations in order to smooth out the instantaneous
variations in demand (ATM switch) or supply (ACM). In the case of queuing, the link arbitration systems may need
to weigh up delay and jitter as well as effective link margin when routing uplink packets to downlink
code/modulation queues.
Following investigations carried out thus far in the applicability of the OBMM processor architecture for ACM,
it has been determined that the complexity of ACM is primarily noticed in the arbitration and control of the DVB-S2
encoder modulator data streams. A multi-class streaming support facility is deemed to be required for any system
using downlink ACM. Since complicated arbitration is needed between the multiple classes, the encoder/modulator
accepts two multiplexed inputs for broadcast and non broadcast services, where the arbitration and control of the
streams is performed externally to the encoder/modulator.
The ACM router may interface with the DVB-S2 modulator via a Single Generic Stream input and the ACM
Command input, or via Multiple (Transport or Generic) Stream inputs. The choice between the different options has
a significant impact on the definition of the system architecture (intended as data processing, routing, buffering and
transmission strategy) and consequently on the overall system performance in terms of efficiency, dynamic
versatility, and complexity. Thus several processor architectures for DVB-S2 unicast systems supporting ACM have
been investigated based on some considerations regarding their QoS performance and complexity.
Also, the delay induced by switching or buffering of data is well understood to introduce concerns in the
physical layer adaptation loop efficiency and consequently the system capability of tracking channel variations.
Thus, the ACM router and router manager architecture options need to take into account these concerns.
The ACM enhanced OBMM architectures are defined to have efficient and flexible ACM arbitration and priority
service routers that are capable of handling the mean to peak variations in traffic yet maintaining the QoS, minimum
hardware overheads, maximum throughput, and routing flexibility.
9
III. HPA linearisation
The multilevel modulation alphabets offered by DVB-S2 require some form of HPA linearisation, either as data
pre-distortion or non-linear compensation of the waveform for reasonable link performance. However, the
advantages of using dynamic data pre-distortion as opposed to static, is directly related to the choice of using single
or multiple carrier amplification.
The benefits of using dynamic data pre-distortion for ISI reduction are well understood, however the choice in
selecting single carrier or multiple carrier HPA based payload architectures is mission specific. It is expected that
the decision criteria of payload and processor complexity against channel capacity and QoS will be the driving
factors.
IV. Physical Adaptation Layer Implementation
As aforementioned, the delay induced by switching or buffering of data is well understood to introduce concerns
in the physical layer adaptation loop efficiency, and consequently the system capability of tracking channel
variations. Thus the ACM router and router manager architecture options need to take into account these concerns.
The methods by which the OBP shall filter the channel quality information and relay this to the interested parties
is mission specific, and will directly impact the performance of the OBP with regards to QoS. This is expected
especially if the method used for channel quality reporting is such that loop delays are high. Also, the granularity by
which measurements and reporting is performed, i.e. at channel level, TDM level, or even slot level, has a
significant impact on loop delays.
The on-board switch of the processor has a key role in this respect, as the physical layer mode may be stored on
board as part of the switching functionality. In addition, as a consequence of the selected downlink physical layer
configuration, this may place constraints on the downlink capacity allocation, as the capacity may be exceeded. Thus
additional processor functionality is included for handling the possible protocols for deleting or re-organizing the
downlink queues.
D. DVB-S2 Encoder/Modulator Development
In support of the extension of the OBMM architecture to accommodate DVB-S2 downlinks, the principal new
datapath development required, the design of a DVB-S2 encoder/modulator (covering the full range of DVB-S2
coding and modulation options), has been carried out under an ESA ARTES-4 programme. A well instrumented
real-time prototyping environment has been developed to verify the encoder/modulator design performance, paying
particular attention to non-linearity compensation techniques such as linearisation, static pre-distortion and dynamic
pre-distortion, including real-time optimisation of the latter.
scrambler
padder
DVB-S2 Testbed
Random
data
generator
BCH
Enc oder
Adapti ve Su bsystem Contr oller
Bit
Interleaver
LDPC
Enc oder
S ymbol
Mapper
Data
Pre
Distort
Matche d
Filter
Farrow
Inter p
Nonlinear
Comp
HP A
Σ
Centr oi d
Est
Error
Signal
Ge n
Matche d
Filter
ML
Symbol
Det
Decoders
Noise
PC inter face logic
Modulato r
Logic Analyser
Data stream
gene rator
Recei ver com ponents
Adaptation
components
Figure 8. DVB-S2 Encoder/Modulator testbed
10
Digitally modell ed
components
B ER
The real-time testbed environment illustrated in Figure 8, is being used to verify the behaviour and quantify the
performance of the encoder/modulator under numerous configurations. The configurable aspects of the testbed
permit the testing of all modulation and code rate options supported by the DVB-S2 standard, including the options
of static data pre-distortion, dynamic data pre-distortion, and linearisation. Of particular interest is the ability of the
testbed to adapt to the non-linear response of the HPA, and by way of either data pre-distortion or linearisation
methods allow for driving the HPA closer to saturation. Sufficient flexibility is offered by the testbed to run realtime performance measures at a choice of HPA input backoffs and noise levels, such that a more thorough
performance evaluation of the encoder/modulator is performed. Included as part of the testbed, for a more overall
transmitter benchmark, an LDPC decoder is used which is capable of handling both short and long packet sizes and
all the code rate options offered by the DVB-S2 standard. The decoders (BCH and LDPC) in conjunction with a
very low implementation loss demodulator, constitute the ideal receiver.
The flexibility of the testbed is largely attributed to the GUI based interface environment developed, which
allows for the user monitoring and configuration of the implemented functions. The interface GUI is the client,
while the server interfaces directly with the hardware via a PCI interface. The server/client arrangement is such that
it allows the user to remotely control the hardware over the network, hence offering the potential of configuring and
monitoring the testbed regardless of the hardware physical location.
The client user interface permits the automation of the performance measurement cycles, since these
measurements may be time consuming, especially in low noise cases where the expected packet error rates are low.
Additionally, to improve the observability of the internal functions and operations of the encoder/modulator and
other related logic, numerous logic analyser cores are inserted throughout the testbed, which in turn capture and
relay information to the user interface for monitoring.
Figure 9 shows a 16-APSK example which illustrates the adaptation of the received symbol centroids for 1, 10,
20, and 60 iterations. It can be seen that there is a clear progression of the adaptation process in minimising the nonlinear effects of the HPA. To obtain these results, a dynamic data pre-distorter with a memory span of three symbols
was used, running over 60 iterations “real-time” for the 8192 distinct centroids. The specific HPA non-linear
response chosen is shown in Figure 10; an input backoff of 4dB was targeted. In response to this adaptation, Figure
11, which depicts before and after shots of the GUI received symbol monitoring window, shows the clear
improvement achieved in reducing ISI and minimising amplitude and phase distortions. It must be noted that the
results illustrated are obtained in “real-time” from the testbed and are not the product of lengthy post-processing or
computer simulation.
Figure 9. DVB-S2 Encoder/Modulator data pre-distortion GUI screen shots of received symbol centroids
(top left) iteration 1, (top right) iteration 10, (bottom left) iteration 20, (bottom right) iteration 60
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Figure 10. DVB-S2 Encoder/Modulator HPA response GUI screen shot
Figure 11. DVB-S2 Encoder/Modulator received symbol GUI screen shots
(left) before adaptation, (right) after adaptation of 60 iterations
It has been the intention of this testbed development activity to verify the functionality and quantify the
performance of the developed DVB-S2 compliant encoder/modulator design, with the additional prospect of this
testbed playing a significant role as part of a larger real-time processor testbed for demonstrating an OBMM
architecture capable of handling ACM on the downlink.
IV.
Conclusion
This paper has described the Astrium OBMM regenerative mesh link multimedia processor. The design and
implementation of the OBMM processor have been successfully completed. The development has demonstrated
Astrium’s capability to deliver power and mass efficient mesh multimedia processors with high level of performance
and operational flexibility to potential satellite operators. Development of encoder modulator algorithm design and
associated control for future enhancement of the OBMM processor architecture and functions to support DVB-S2
standard downlink is being undertaken.
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