Department of Electrical and Computer Eng’g
Course: Microcomputers and Interfacing (ECE4501)
Lectures: Introduction to 8086 uP
Architecture and Programming
Asrat Gedefa
FoET, ECE
October 20, 2019
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
1 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
THE 8086 MICROPROCESSOR
Introduction to the 8086 microprocessor
Internal Microprocessor Architecture
Addressing Modes
Data Addressing Mode
Program Memory-Addressing Mode
Stack Memory-Addressing Mode
Instruction Set and Assembly Language Programming
8086 Interfacing: Memory and I/O Interfacing
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
2 / 34
Contents
1
Chapter 1: Introduction to 8086 Internal Architecture
2
Chapter 2: Addressing Modes
3
Chapter 3: The 8086 Instruction Set and ALP
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Chapter 1: Intro to 8086 Internal Architecture
The Intel 8086 is a 16-bit microprocessor that is intended to be
used as the CPU in a microcomputer.
The term 16-bit means that its arithmetic logic unit, its internal
registers, and most of its instructions are designed to work with
16-bit binary words.
The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20-bit address bus, so it can address any one of
220, or 1,048,576, memory locations.
Each of the 1,048,576 memory addresses of the 8086 represent a
byte-wide location.
Sixteen-bit words will be stored in two consecutive memory
locations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Chapter 1: Intro to 8086 Internal Architecture
The Intel 8086 is a 16-bit microprocessor that is intended to be
used as the CPU in a microcomputer.
The term 16-bit means that its arithmetic logic unit, its internal
registers, and most of its instructions are designed to work with
16-bit binary words.
The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20-bit address bus, so it can address any one of
220, or 1,048,576, memory locations.
Each of the 1,048,576 memory addresses of the 8086 represent a
byte-wide location.
Sixteen-bit words will be stored in two consecutive memory
locations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
4 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Chapter 1: Intro to 8086 Internal Architecture
The Intel 8086 is a 16-bit microprocessor that is intended to be
used as the CPU in a microcomputer.
The term 16-bit means that its arithmetic logic unit, its internal
registers, and most of its instructions are designed to work with
16-bit binary words.
The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20-bit address bus, so it can address any one of
220, or 1,048,576, memory locations.
Each of the 1,048,576 memory addresses of the 8086 represent a
byte-wide location.
Sixteen-bit words will be stored in two consecutive memory
locations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
4 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Chapter 1: Intro to 8086 Internal Architecture
The Intel 8086 is a 16-bit microprocessor that is intended to be
used as the CPU in a microcomputer.
The term 16-bit means that its arithmetic logic unit, its internal
registers, and most of its instructions are designed to work with
16-bit binary words.
The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20-bit address bus, so it can address any one of
220, or 1,048,576, memory locations.
Each of the 1,048,576 memory addresses of the 8086 represent a
byte-wide location.
Sixteen-bit words will be stored in two consecutive memory
locations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
4 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Chapter 1: Intro to 8086 Internal Architecture
The Intel 8086 is a 16-bit microprocessor that is intended to be
used as the CPU in a microcomputer.
The term 16-bit means that its arithmetic logic unit, its internal
registers, and most of its instructions are designed to work with
16-bit binary words.
The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20-bit address bus, so it can address any one of
220, or 1,048,576, memory locations.
Each of the 1,048,576 memory addresses of the 8086 represent a
byte-wide location.
Sixteen-bit words will be stored in two consecutive memory
locations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
4 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
8086 Internal Architecture
The 8086 microprocessor is divided into two independent
functional units.
These are Bus Interface Unit (BIU) and the Execution Unit (EU).
These two functional unit can work simultaneously to increase
system speed and hence the throughput.
Throughput is a measure of number of instructions per unit time.
Bus Interface Unit(BIU)
The bus interface unit is the 8086’s interface to the outside
world.
It provides a full 16-bit bi-directional data bus and 20-bit
address bus.
The bus interface unit is responsible for performing all
external bus operations.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
5 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
6 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Functions of BIU
It sends address of the memory or Input-Output
It fetches instruction from memory
It reads data from memory/port
It writes data into memory/port
It supports instruction queuing
To implement these functions the BIU contains:
the instruction queue,
segment registers,
instruction pointers, and
address summer.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Architecture of intel 8086 microprocessor
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October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
8 / 34
Chapter 1: Introduction to 8086 Internal Architecture
Instruction Queue
To speed up program execution, the BIU fetches six instruction
bytes ahead of time from the memory.
These prefetched instruction bytes are held for the execution unit
in a group of register called Queue.
With the help of queue it is possible to fetch next instruction
when the current instruction is in execution.
For example, current instruction in execution is a multiplication
instruction.
In 8086, operands for multiplication operations are with in the
register that requires 100 clock cycles to execute it.
During this execution time the BIU fetches the next instruction or
instructions from memory into the instruction queue instead of
remaining idle- continues this process as long as the queue is not
full.
Due to this, the execution unit gets the ready instruction in the
queue and instruction fetch time is eliminated.
Asrat Gedefa (FoET, ECE )
8086uP
October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Queue Principle
The queue operates on the principle of first-in-first-out (FIFO)- i.e
the execution unit gets the instructions for execution in the order
they are fetched.
In case of JUMP and CALL instructions, instructions already
fetched in the queue are of no use.
Hence, in these cases queue is dumped and newly formed by
loading instructions from new address specified by JUMP or
CALL instruction.
Feature of fetching the next instruction while the current
instruction is executing is called pipelining.
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October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Segment Registers
The physical address of the 8086 is 20-bits wide to access 1 Mbyte
memory locations.
However, its registers and memory locations which contain logical
addresses are just 16-bits wide.
Using memory segmentation, it treats the 1 Mbyte of memory as
divided into segments, with a maximum size of a segment as 64
Kbytes.
Thus any location within the segment can be accessed using 16
bits. The 8086 allows only four active segments at a time.
For the selection of the four active segments the 16-bit segment
registers are provided within the BIU of the 8086.
These four registers are: Data Segment (DS), Code Segment (CS),
Stack Segment (SS), Extra Segment (ES)
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Chapter 1: Introduction to 8086 Internal Architecture
Fig. Arrangement of segment
registers
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October 20, 2019
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Chapter 1: Introduction to 8086 Internal Architecture
Instruction Pointer
The instruction pointer register holds the 16-bit address of the
next code byte within the code segment.
The value contained in the IP is referred to as an offset. This
value must be offset from (added to) the segment base address to
produce the required 20-bit physical address.
To generate the 20-bit physical address, the content of the CS
register is multiplied by 16 i.e. shifted by four to the left, and then
the offset i.e. the content of IP register are added to the shifted
contents of CS.
For example: If CS = 348AH and IP = 4214H then the physical
address is:
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Chapter 1: Introduction to 8086 Internal Architecture
Execution Unit (EU)
The execution unit of the 8086 tells the BIU where to fetch
instructions or data from, decodes instructions and executes
instruction.
The EU contains control circuitry which directs the internal
operations. A decoder in the EU translates the instructions fetched
from memory into a series of actions which the EU carries out.
ALU is a 16-bit which can add, subtract, AND, OR, XOR,
increment, complement and shift binary numbers.
Flag Registers: A flag is a flip-flop which indicates some
condition produced by the execution of an instruction or controls
certain operations of the Processor-has nine active flags.
After execution of addition (0110 0101 1101 0001 and 0010 0011
0101 1001), the flag registers are:
SF=1,ZF=0,PF=1,CF=0,AF=0,OF=1
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Chapter 1: Introduction to 8086 Internal Architecture
General Purpose and Pointers and Index Registers
The EU has eight general purpose registers labeled AH, AL,
BH, BL, CH, CL, DH, and DL. These registers can be used
individually for temporary storage of 8 bit data.
The AL register is also called accumulator. Certain pairs of these
general purpose registers are used together to store 16-bit data,
such as AX, BX, CX, and DX.
All segment registers are 16-bits. But it is necessary to put 20-bit
address (physical address) on the address bus. To get 20-bit
physical address one more register is associated with each segment
register like IP associated with CS.
These registers are the pointer and index and consist of IP, SP,
BP, SI, and DI registers.
The SP contains the 16-bit offset from the start to the top of stack
segment. BP can also be used for accessing the stack. SI can be
used to hold the offset of a data word in the DS. Destination Index
(DI) used in string instruction with ES.
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Chapter 2: Addressing Modes
Chapter 2: Addressing Modes
The Execution Unit (EU) has direct access to all registers and
data for register and immediate operands.
However, as the EU cannot directly access the memory
operands,the BIU segment registers are used to access memory
operands.
i.e., when the EU needs to access a memory location, it sends an
offset value to the BIU. This offset is also called the Effective
Address (EA).
Note that EA is displacement of the desired location from the
segment base.
The BIU generates a 20-bit physical address after shifting the
contents of the desired segment register four bits to the left and
then adding the 16-bit EA to it.
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Chapter 2: Addressing Modes
Data Addressing Modes
Register Addressing Mode
This mode specifies the source operand, destination operand, or
both to be contained in the 8086 register/s.
Example: MOV BX, CX; MOV CL, BL;
Immediate Addressing Mode
Transfer the source (immediate) byte or word of data into the
destination register or memory location.
Example: MOV BL, 26H ; MOV CX, 4567H;
Direct Addressing Mode
Here, the 16-bit effective address (EA) is taken directly from the
displacement field of the instruction.
Example: MOV CL, [9823H];
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Chapter 2: Addressing Modes
Register Indirect Addressing Mode
Transfers a byte or word between a register and memory location
addressed by an index or base register - The index and base
registers are BP, BX, DI, and SI.
Example: MOV [DI], BX;
Base-plus-index Addressing Mode:
Transfers a byte or word between a register and the memory
location addressed by a base register (BP or BX) plus index register
(DI or SI).
Example: MOV [BX + DI], CL;
Register Relative Addressing Mode
Moves a byte or word between a register and the memory location
addressed by an index or base register plus a displacement.
Example: MOV AX, [BX+4]; MOV AX, ARRAY[BX];
Register Relative Addressing Mode
Transfers a byte or word between a register and the memory
location addressed by a base and an index register plus
displacement.
Example: MOV AX, [BX+DI+4]; MOV AX, ARRAY[BX+DI];
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Chapter 2: Addressing Modes
Program Memory-Addressing Mode
Program memory-addressing modes, used with the JMP and CALL
instructions, consist of three distinct forms:
1 Direct Program Memory Addressing
This instruction stores the address with the opcode.
For example, if a program jumps to memory location 10000H for
the next instruction, the address (10000H) is stored following the
opcode.
This JMP instruction loads CS with 1000H and IP with 0000H to
jump to memory location 10000H for the next instruction. (We can
have an intra-segment or inter-segment jumps.)
The direct jump is often called a far jump because it can jump to
any memory location for the next instruction.
2
3
Relative Program Memory Addressing
Indirect Program Memory Addressing
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Chapter 2: Addressing Modes
Relative Program Memory Addressing:
The term relative means relative to the instruction pointer (IP)
(this is often an intrasegment instruction).
For instance, if a jump instruction skips the next two bytes of
memory, the address in relation to the instruction pointer is a 2
that adds to the instruction pointer.
Relative JMP and CALL instructions contain either an 8-bit or a
16-bit signed displacement that allows a forward memory reference
or a reverse memory reference.
Indirect Program Memory Addressing:
The 8086 microprocessor allows several forms of program indirect
memory addressing for the JMP and CALL instructions.
Acceptable program indirect jump instruction can use any 16-bit
register (AX, BX, CX, DX, SP, BP, DI, or SI); any relative register
([BP], [BX], [DI], or [SI]); and any relative register with a
displacement.
Example: JMP AX; JMP TABLE[BX];
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Chapter 2: Addressing Modes
Stack Memory-Addressing Mode
The stack plays an important role in all microprocessors. It holds
data temporarily and stores return addresses for procedures.
The stack memory is a LIFO (last-in, first-out) memory. Data are
placed onto the stack with a PUSH instruction and removed with a
POP instruction.
The CALL instruction also uses the stack to hold the return address
for a procedure and RET (return) instruction to remove the return
address from the stack.
The stack memory is maintained by two registers: the stack
pointer(SP) and the stack segment (SS)registers. Whenever a word
of data is pushed onto the stack, the higher-order 8-bits are placed
in the location addressed by SP-1 and low-order 8-bits by SP-2.
The SP is then decremented by 2 so that the next word of data is
stored in the next available stack memory location.
Whenever data are popped from the stack, the low-order 8-bits are
removed from the location addressed by SP and higher-order 8-bits
addressed by SP+1.
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Chapter 2: Addressing Modes
PUSH BX and POP CX
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Chapter 3: The 8086 Instruction Set and ALP
Chapter 3: The 8086 Instruction Set and ALP
A binary code uP uses as its instructions to control its operation.
The 8086 has 117 different instructions with about 300 opcodes.
Each of the 8086 instruction set can have no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations, with the exception of string operations.
The formats of the 8086-Core 2 machine language instructions is
shown below. (a) The 16-bit form and (b) 32-bit
form.
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Chapter 3: The 8086 Instruction Set and ALP
Chapter 3: The 8086 Instruction Set and ALP
A binary code uP uses as its instructions to control its operation.
The 8086 has 117 different instructions with about 300 opcodes.
Each of the 8086 instruction set can have no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations, with the exception of string operations.
The formats of the 8086-Core 2 machine language instructions is
shown below. (a) The 16-bit form and (b) 32-bit
form.
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Chapter 3: The 8086 Instruction Set and ALP
Chapter 3: The 8086 Instruction Set and ALP
A binary code uP uses as its instructions to control its operation.
The 8086 has 117 different instructions with about 300 opcodes.
Each of the 8086 instruction set can have no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations, with the exception of string operations.
The formats of the 8086-Core 2 machine language instructions is
shown below. (a) The 16-bit form and (b) 32-bit
form.
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Chapter 3: The 8086 Instruction Set and ALP
Chapter 3: The 8086 Instruction Set and ALP
A binary code uP uses as its instructions to control its operation.
The 8086 has 117 different instructions with about 300 opcodes.
Each of the 8086 instruction set can have no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations, with the exception of string operations.
The formats of the 8086-Core 2 machine language instructions is
shown below. (a) The 16-bit form and (b) 32-bit
form.
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Chapter 3: The 8086 Instruction Set and ALP
Chapter 3: The 8086 Instruction Set and ALP
A binary code uP uses as its instructions to control its operation.
The 8086 has 117 different instructions with about 300 opcodes.
Each of the 8086 instruction set can have no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations, with the exception of string operations.
The formats of the 8086-Core 2 machine language instructions is
shown below. (a) The 16-bit form and (b) 32-bit
form.
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Chapter 3: The 8086 Instruction Set and ALP
Chapter 3: The 8086 Instruction Set and ALP
A binary code uP uses as its instructions to control its operation.
The 8086 has 117 different instructions with about 300 opcodes.
Each of the 8086 instruction set can have no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations, with the exception of string operations.
The formats of the 8086-Core 2 machine language instructions is
shown below. (a) The 16-bit form and (b) 32-bit
form.
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Chapter 3: The 8086 Instruction Set and ALP
80386 and above assume all instructions are 16-bit mode
instructions when the machine is operated in the real mode (DOS).
in protected mode (Windows), the upper byte of the descriptor
contains the D-bit that selects either the 16- or 32-bit instruction
mode.
Opcode: Selects the operation (addition, subtraction, etc.,)
performed by the microprocessor. either 1 or 2 bytes long for most
instructions
Figure below illustrates the general form of the first opcode byte
of many instructions.
first 6 bits of the first byte are the binary opcode, remaining 2 bits
indicate the direction (D) of the data flow, and indicate whether
the data are a byte or a word (W)
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Chapter 3: The 8086 Instruction Set and ALP
80386 and above assume all instructions are 16-bit mode
instructions when the machine is operated in the real mode (DOS).
in protected mode (Windows), the upper byte of the descriptor
contains the D-bit that selects either the 16- or 32-bit instruction
mode.
Opcode: Selects the operation (addition, subtraction, etc.,)
performed by the microprocessor. either 1 or 2 bytes long for most
instructions
Figure below illustrates the general form of the first opcode byte
of many instructions.
first 6 bits of the first byte are the binary opcode, remaining 2 bits
indicate the direction (D) of the data flow, and indicate whether
the data are a byte or a word (W)
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Chapter 3: The 8086 Instruction Set and ALP
80386 and above assume all instructions are 16-bit mode
instructions when the machine is operated in the real mode (DOS).
in protected mode (Windows), the upper byte of the descriptor
contains the D-bit that selects either the 16- or 32-bit instruction
mode.
Opcode: Selects the operation (addition, subtraction, etc.,)
performed by the microprocessor. either 1 or 2 bytes long for most
instructions
Figure below illustrates the general form of the first opcode byte
of many instructions.
first 6 bits of the first byte are the binary opcode, remaining 2 bits
indicate the direction (D) of the data flow, and indicate whether
the data are a byte or a word (W)
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Chapter 3: The 8086 Instruction Set and ALP
Byte 2 of many machine language instructions, showing the
position of the MOD, REG, and R/M fields is depicted under.
MOD field: Specifies addressing mode (MOD) and whether a
displacement is present with the selected type.
If MOD field contains an 11, it selects the register-addressing mode
Register addressing specifies a register instead of a memory
location, using the R/M field.
If the MOD field contains a 00, 01, or 10, the R/M field selects one
of the data memory-addressing modes.
All 8-bit displacements are sign-extended into 16-bit displacements
when the processor executes the instruction.
if the 8-bit displacement is 00H-7FH (positive),it is sign-extended to
0000H-007FH before adding to the offset address
if the 8-bit displacement is 80H-FFH (negative),it is sign-extended
to FF80H-FFFFH
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Chapter 3: The 8086 Instruction Set and ALP
MOD field for the 16-bit instruction mode is shown:
When MOD selects a data memory addressing mode, it indicates
that the addressing mode contains no displacement (00), an 8-bit
sign-extended displacement (01), or a l6-bit displacement (10).
The MOV AL,[DI] instruction is an example that contains no
displacement, a MOV AL,[DI+2] instruction uses an 8-bit
displacement (+2), and a MOV AL,[DI+1000H] instruction uses a
16-bit displacement (+1000H).
All 8-bit displacements are sign-extended into 16-bit displacements
when the microprocessor executes the instruction.
If the 8-bit displacement is 00H-7FH (positive), it is sign-extended
to 0000H-007FH before adding to the offset address. If the 8-bit
displacement is 80H-FFH (negative), it is sign-extended to
FF80H-FFFFH.
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Chapter 3: The 8086 Instruction Set and ALP
Register Assignments
Table under lists the register assignments for the REG field and
the R/M field (MOD=11).
This table contains three lists of register assignments: one is used
when the W bit=0 (bytes), and the other two are used when the
W bit=1(words or double-words).
Note that double-word registers are only available to the 80386
through the Core2.
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Chapter 3: The 8086 Instruction Set and ALP
Suppose that a 2-byte instruction, 8BECH, appears in a machine
language program.
Since neither a 67H (operand address-size override prefix) nor a 66H
(register-size override prefix) appears as the first byte, the first byte
is the OPCODE.
If the microprocessor is operated in the 16-bit instruction mode,
this instruction is converted to binary and placed in the instruction
format of bytes 1 and 2, as illustrated in figure below.
The opcode is 100010, which is the opcode for a MOV instruction.
Notice that both the D and W bits are a logic 1, which means that a
word moves into the destination register specified in the REG field.
The REG field contains a 101, indicating register BP, so the MOV
instruction moves data into register BP. Because the MOD field
contains a 11, the R/M field also indicates a register.
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Chapter 3: The 8086 Instruction Set and ALP
Suppose that a 668BE8H instruction appears in an 80386 or
above, operated in the 16-bit instruction mode.
The first byte (66H) is the register-size override prefix that selects
32-bit register operands for the 16-bit instruction mode.
The remainder of the instruction indicates that the opcode is a
MOV with a source operand of EAX and a destination operand of
EBP. This instruction is a MOV EBP,EAX.
R/M Memory Addressing: if the MOD field contains a 00, 01,
or 10, the R/M field takes on a new meaning.
Table below lists the memory-addressing modes for the R/M field
when MOD is a 00, 01, or 10 for the 16-bit instruction mode.
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Chapter 3: The 8086 Instruction Set and ALP
Figure below illustrates the machine language version of the 16-bit
instruction MOV DL,[DI] or instruction (8AI5H).
This instruction is 2 bytes long and has an opcode 100010,D=1 (to
REG from R/M ), W=0, MOD=00,REG=010 (DL) and
R/M=101 (DI).
If the instruction changes to MOV DL,[DI+1], the MOD field
changes to 01 for an 8-bit displacement, but the first 2 bytes of the
instruction otherwise remain the same. The instruction now
becomes 8A5501H instead of 8A15H.
Notice that the 8-bit displacement appends to the first 2 bytes of
the instruction to form a 3-byte instruction instead of 2 bytes.
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Chapter 3: The 8086 Instruction Set and ALP
There is a special addressing mode that does not appear as
depicted in the former tables.
It occurs whenever memory data are referenced by only the
displacement mode of addressing for 16-bit instructions.
Ex: MOV [1000H],DL; (fig shown below) and MOV NUMB,DL;
The first instruction moves the contents of register DL into data
segment memory location 1000H.
The second instruction moves register DL into symbolic data
segment memory location NUMB.
Whenever an instruction has only a displacement, the MOD field is
always a 00 and the R/M field is always 110. Clearly, the
instruction contains no displacement and uses addressing mode
[BP]-which can’t be without a displacement in machine language.
The assembler takes care of this by using an 8-bit disp.(MOD=01).
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Chapter 3: The 8086 Instruction Set and ALP
An Immediate Instruction
Suppose that the MOV WORD PTR [BX+1000H ],1234H
instruction is chosen as an example of a 16-bit instruction using
immediate addressing.
This instruction moves a 1234H into the word-sized memory
location addressed by the sum of 1000H, BX, and DSx10H.
The WORD PTR directive indicates to the assembler that the
instruction uses a word-sized memory pointer.
The MOV [BX],AL instruction is clearly a byte move; the MOV
[BX],9 instruction is not exact, and could therefore be a byte-,
word-, or doubleword-sized move.
Here, the instruction must be coded as MOV BYTE PTR [BX],9,
MOV WORD PTR [BX],9, or MOV DWORD PTR [BX],9. If not,
the assembler flags it as an error because it cannot determine the
intent of the instruction.
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Chapter 3: The 8086 Instruction Set and ALP
Figure: MOV WORD PTR[BX+1000H], 1234H instruction
converted to binary machine language.
This 6-byte instruction uses 2 bytes for the opcode, W, MOD, and
R/M fields. Two of the 6 bytes are the data of 1234H; 2 of the 6
bytes are the displacement of 1000H.
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Chapter 3: The 8086 Instruction Set and ALP
Segment MOV Instructions
If the contents of a segment register are moved by the MOV,
PUSH, or POP instructions, a special set of register bits (REG
field) selects the segment register.
This type of MOV instruction is different for the prior MOV
instructions. Segment registers can be moved between any 16-bit
register or 16-bit memory location.
*Note: MOV CS,R/M and POP CS are not allowed.
EX. MOV [DI],DS; It stores the contents of DS into the memory
location addressed by DI in the data segment.
An immediate segment register MOV is not available in the
instruction set. To do this, first load another register with the
immediate data and then move it to a segment register.
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Chapter 3: The 8086 Instruction Set and ALP
Figure: MOV BX,CS; instruction converted to binary machine
language.
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