Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (1/10)
[Technical Paper]
Warpage Mechanism of Thin Embedded LSI Packages
Yoshiki Nakashima*, Katsumi Kikuchi*, Kentaro Mori*, Daisuke Ohshima**, and Shintaro Yamamichi*
*Device Platforms Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara 229-1198, Japan
**System Jisso Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara 229-1198, Japan
(Received June 29, 2010; accepted October 1, 2010)
Abstract
The warpage mechanism of a thin embedded LSI package with a thick Cu plate was investigated for various Cu plate
thicknesses. The package warpage increased gradually as the Cu plate was made thinner. Even structures with a balanced
Cu and resin layer configuration for the top and bottom portions of the embedded chip showed substantial warpage, especially in the chip region, that was greater than that for an unbalanced layer configuration. This indicates the existence
of other warpage factors as well as unbalanced residual stress between the top and bottom of the chip. A ‘Birth & Death’
finite element method simulation showed that the thermal residual stresses induced by the coefficient of thermal expansion mismatch for the LSI chip and embedding resin were concentrated in the resin surrounding the lateral sides of the
chip and that the stresses increased with decreasing Cu thickness. The release of these tensile stresses resulted in package warpage.
Keywords: Advanced Packaging, Embedded Device Technology, SiP, Simulation, Residual Stress
and SIRRIUS packages are shown in Table 1. While
1. Introduction
LSI packaging technologies are needed for fabricating
several organizations have been developing packaging
thinner and higher-pin-count LSI packages to meet the
technologies that have structures similar to that of
market demands for thinner, smaller, and more functional
SIRRIUS,[6–9] SIRRIUS features the ability to embed a high-
mobile devices.[1] One way to achieve a thinner, higher-
pin-count LSI with a comparably thin structure and suffi-
pin-count LSI packaging structure is to realize a thinner
cient reliability.
alternative
to
conventional
flip-chip
ball-grid
array
A reference FCBGA package and a SIRRIUS package
(FCBGA) packaging. Our ‘SIRRIUS’ (seamless intercon-
were prepared for LSI chips with the same specifications.
nect for re-routing LSI using substrate) technology,[2–5]
The total vertical thicknesses of these packages were 1.9
for example, is well suited to fabricating those alternatives,
and 0.71 mm, respectively. This remarkable reduction in
as shown in Fig. 1. The specifications of the embedded LSI
thickness was achieved by using a thinner LSI chip (only
50 μm), a coreless structure, and seamless copper posts
Table 1 SIRRIUS package specifications.
Size (mm)
LSI
Thickness (μm)
LSI pad count
LSI pad pitch (μm)
Size (mm)
BGA pad count
Package BGA pad pitch (mm)
Fig. 1
Comparison of (a) Structure A, reference FCBGA
package and (b) Structure B, our SIRRIUS package.
Wiring layer
BGA ball size (mm)
9×9
50
1500
160 (staggered area array)
27 × 27
625
1.0 (area array)
3
0.6
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Transactions of The Japan Institute of Electronics Packaging
Vol. 3, No. 1, 2010
for the interconnections instead of solder bumps.
than half the original thickness. There are two factors that
However, the continuing market trend makes it neces-
make Structure C susceptible to warpage: the structure is
sary to examine the possibility of making the SIRRIUS
vertically asymmetric, so there is a vertical imbalance in
structure even thinner. Thinning or removing the charac-
the residual thermal stresses caused by the coefficient of
teristic 500-μm-thick Cu plate is a valid approach to making
thermal expansion (CTE) mismatch; and there is little in
the package thinner. However, since the plate is used to
the structure besides the Cu plate to keep the package flat
control package warpage and remove LSI heat, research
and stiff.
into ways to make the SIRRIUS package thinner must
The next structure fabricated, Structure D, is not
address the control of package warpage with a thinner Cu
affected by these two warpage factors. It is compared with
plate.
Structure C on the same scale in Fig. 3. Vertical asymme-
We have now investigated several SIRRIUS package
try was eliminated by introducing ‘balance resin’ and
structures with thinner Cu plates or without any Cu plate
‘remaining Cu’ layers above the chip. The remaining Cu
in order to clarify the warpage mechanism. We performed
layer was only 10 μm thick, approximately the same thick-
a ‘birth & death’ finite element method (FEM) analysis for
ness as that of the first wiring layer. A glass cloth (GC)
further discussion on fabrication process flows and struc-
sheet was added to the same layer as the LSI chip to
tures, though this thermal stress analysis is conventionally
reinforce that layer so as to improve flatness and stiffness.
used to predict reliability after fabrication.[10, 11] We
The fabrication process flow for Structure C is shown in
found that the Cu plate thickness reduction created resid-
Fig. 4. Note that the direction of the cross-sectional illus-
ual tensile stress in the resin layers surrounding the chip,
trations is upside-down compared with Figs. 1 to 3. The
mainly in the areas lateral to the chip. The release of these
LSI chips were pre-processed to form Cu posts on the LSI
tensile stresses, along with the release of the compressive
pads by semi-additive metallization. This was followed by
stress in the chip, caused the package to warp.
back-grinding to make them 50 μm thick, 20-μm-thick
adhesive layer lamination on the backside, and dicing to
2. Structures and Experimental Processes
form 9-mm-square chips. The first process step was LSI
As mentioned above, one approach to thinning the struc-
chip mounting, as shown in Fig. 4 (a). The chips were sta-
ture is to thin or remove the Cu plate while retaining the
bilized by curing the adhesive layer. The CTE for the adhe-
embedding resin and wiring structure, as shown in Fig. 2.
sive layers was 80 ppm. The chips were then embedded in
We used this approach to fabricate several structures for
90-μm-thick epoxy resin using a simple vacuum lamination
evaluation. The first structure, ‘Structure C’ in Fig. 2 (b),
process, as shown in Fig. 4 (b). The CTE for the epoxy
had three wiring layers on the lower side of the LSI chip
layer was 60 ppm. The Cu posts were then exposed by
and a thinner or no Cu plate on the upper side of the chip,
grinding the epoxy resin surface, as shown in Fig. 4 (c). A
with an adhesive layer between the plate and the chip. The
microscopic photo of the exposed Cu posts is shown in
thickness of the thinned Cu plate was set to slightly less
Fig. 5 (a). Next, the wiring layers were fabricated. The first
Fig. 2 Comparison of (a) Structure B, our initial SIRRIUS
Fig. 3
package and (b) Structure C, our SIRRIUS package with
with thinned or removed Cu plate and (b) Structure D, anti-
thinned or removed Cu plate.
warpage structure.
48
Comparison of (a) Structure C, our SIRRIUS package
Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (3/10)
Fig. 4 Steps in fabrication of Structure C.
forcement layer,’ which had a CTE of 24 ppm. The epoxy
resin sheet, which is called the ‘cover resin’ layer, was
composed of the same material as the ‘balance resin’ layer.
Once the LSI chips had been embedded into the resin layers, the Cu posts were exposed using the same grinding
process as that used for Structure C, as shown in Fig. 6
(d). A microscopic photo of the posts is shown in Fig. 7 (a).
The cover resin layer thickness is the same as the Cu post
Fig. 5 Photos of Structure C: (a) microscopic photo of
exposed Cu posts; (b) photo of first wiring layer.
thickness between the surface of the chip passivation film
(PF) resin and the surface of the cover resin. We measured the cover resin layer thicknesses at the center of
four chips after the grinding. The thicknesses of the four
fan-out wiring layer was fabricated using semi-additive
chips selected near the four edges of the work were 10.5,
metallization, as shown in Fig. 4 (d). A photo of the wiring
12.1, 13.1 and 13.4 μm respectively. The variation of the
layer is shown in Fig. 5 (b). Then, the second and third fan-
thickness is within approximately 3 μm. Next, the first wir-
out wiring layers were fabricated, with resin layers that
ing layer was fabricated using the same process as that
had the same physical properties as the cover resin and
used for Structure C, as shown in Fig. 6 (e). A photo of the
balance resin layers. This process was followed by solder
layer is shown in Fig. 7 (b). We omitted the second and
resist (SR) formation and package dicing, as shown in
third wiring layer formation processes for Structure D
Figs. 4 (e) and (f), respectively. The last process was Cu
because the vertical balance effect was the focus in this
plate etching, as shown in Fig. 4 (g).
experiment. In the last step, the Cu plate was etched so
The fabrication process flow for Structure D is shown in
that a Cu layer about 10 μm thick remained, as shown in
Fig. 6. The first step was balance resin layer lamination, as
Fig. 6 (f). The resulting structure is basically unsusceptible
shown in Fig. 6 (a). The same resin used for chip embed-
to the warpage factors.
ding with Structure C was laminated on the Cu plate by
We measured the average thicknesses of the balance
simple vacuum lamination to a thickness of 20 μm. Next
resin layer, cover resin layer, reinforcement layer, adhe-
was LSI chip mounting. The chips were the same as those
sive layer, and LSI layer with PF resin in Structure D at the
used for Structure D. The next step, resin-GC sheet and
center, at the chip edge, and at the package edge after the
cover resin lamination started with the formation of square
process flow. As shown in Table 2, the cover resin layer
holes for the chips on 50-μm-thick resin-GC sheets, or
was thicker at the package edge than at the center while
epoxy resin sheets reinforced by GC. Then the resin-GC
the balance resin layer was thicker at the center than at the
sheet and a 20-μm-thick epoxy resin sheet were laminated,
package edge. This tendency is explained by the shrink-
and the LSI chips were embedded in the layers, as shown
age of the Cu plate, which causes the chips to take an arch
in Fig. 6 (c). The laminated resin-GC sheet created a ‘rein-
form, after step (c) in Fig. 6.
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Transactions of The Japan Institute of Electronics Packaging
Vol. 3, No. 1, 2010
Fig. 6 Steps in fabrication of Structure D.
Fig. 8
Two partial warpage definitions: (a) package warpage
Wp is larger than chip region warpage Wc; (a) Wc is larger
Fig. 7 Photos of Structure D; (a) microscopic photo of
than Wp.
exposed Cu posts; and (b) photo of first wiring layer.
Table 3 Average warpage for Structures C and D after Cu
Table 2
Average layer thicknesses for Structure D.
Layer
Cover Resin
Thickness (μm)
Structure
PKG Edge Chip Edge Center Average
16.2
16.8
12.7
plate etching.
15.3
Cu plate thickness (μm)
Structure-C
250
100
Structure-D
0
135
362
316
Warpage [Wp or Wc] (μm)
[Wp] [Wp] [Wc]
10
370
[Wc]
LSI (w/PF)
–
62.8
61.7
62.3
Adhesive
–
20.1
19.8
19.9
Reinforcement
84.0
82.9
–
83.4
pages differed for the fabricated Structure C and Structure
Balance Resin
13.8
18.7
19.3
17.2
D samples. When warpage Wp exceeds warpage Wc, the
113.9
118.4
113.6
115.3
warpage for the package was defined as Wp, as shown in
Total
Fig. 8 (a), and vice versa, as shown in Fig. 8 (b). The warpages for Structures C and D, as measured after Cu plate
3.
Results and Discussion
3.1 Structures C and D
etching using the shadow Moiré technique and a stylus
surface profiler, respectively, are shown in Table 3. The
To enable detailed discussion of the warpage, we defined
common warpage measurement line for both structures is
two partial warpage values (Fig. 8). Warpage ‘Wp’ is com-
shown in Fig. 9. In these measurements, the fan-out wiring
plete-package warpage and is the vertical distance between
layer side was up, as shown in Figs. 4 (g) and 6 (f).
the highest and lowest points, excepting the embedded LSI
The warpage profiles after Cu-plate etching for Structure
chip region. Warpage ‘Wc’ is embedded-chip-region war-
C, with Cu plate thicknesses of 250, 100, and 0 μm, and for
page and is the vertical distance between the highest and
Structure D, with a 10-μm-thick copper layer, are shown in
lowest points of the region. The directions of the two war-
Figs. 10 (a) and (b), respectively.
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Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (5/10)
Fig. 9
Common warpage measurement line.
Fig. 11 Other two warpage factors investigated: imbalance in
thermal history and thermal stress in adhesive layer.
Fig. 10
Warpage forms for (a) Structure C and (b) Structure
D samples.
during the cooling phase following curing. Moreover,
there was no stiff material to suppress the warpage after
the Cu plate etching. These configuration and physical
The warpage for Structure C with Cu plate 100 μm thick
or less was significant. When the Cu plate thickness was
properties explain the observation of the large concave
Wc.
100 μm or more, the concave warpage, Wp, exceeded the
For Structure D, the resin layers for the chip-embedding
convex warpage, Wc. This indicates that, with Cu plates,
region were on the upper and lower sides of the chip and
the CTE mismatch between the resin for the three fan-out
had the same thickness. Therefore, if the resin layers
wiring layers and the Cu plate was the dominant factor
shrank during the cooling phase, the shrink force should
causing warpage. In contrast, without the Cu plate, the
have been balanced. Moreover, the chip layer was rein-
concave warpage, Wc, exceeded convex warpage, Wp.
forced to suppress warpage. Therefore, the larger warpage
This indicates that the CTE mismatch between the LSI
than for Structure C needed more explanation.
chip and the resin in the three fan-out wiring layers was
We thus considered other factors which might explain
the dominant factor causing the warpage. These results for
the results for Structure D.
Structure C were as expected.
3.2 Factor Analysis and Discussion of Other Possi-
The warpage for Structure D was also remarkable, as
ble Warpage Factors
shown in Fig. 10 (b). Convex warpage, Wc, exceeded con-
We considered two other possible warpage factors for
cave warpage, Wp. Comparing warpage Wc for Structure C
Structure D, which are illustrated in Fig. 11: the imbalance
without the Cu plate with that for Structure D, we see that
in the thermal history of the resin layers and the thermal
the warpage for Structure D, 370 μm, was larger than that
stress in the adhesive layer. The balance resin layer was
for Structure C, 316 μm, as shown in Table 3. In our dis-
first laminated and cured on the Cu plate. Next, after LSI
cussion here of warpage Wc, we focus on the thermal
mounting, the reinforcement layer and cover resin layer
residual stress factors of the chip-embedding 9 × 9 mm
were laminated and cured, as was the balance resin layer.
central region of the 27 × 27 mm package.
Therefore, the balance resin layer was cured twice while
For Structure C, the main warpage factor, especially for
the upper two layers were cured only once, resulting in an
the chip-embedding region, should be the imbalance
imbalance in the thermal history. The thermal stress in the
between the Si for the LSI chip and the resin for the three
adhesive layer likely caused the layer to shrink, resulting
fan-out wiring layers. The resin for the fan-out layers was
in convex warpage of the chips. To investigate the effect of
140 μm thick, and they were only on the upper side of the
these two factors, we performed an additional factor analy-
LSI chip, as shown in Figs. 4 (g) and 6 (f). The CTE for the
sis experiment in which the wiring layer was not included.
resin is much larger than that for the Si, which would
Cross-sectional illustrations of the two structures fabri-
result in comparable shrinkage for the three resin layers
cated for the experiment are shown in Fig. 12. Both struc-
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Transactions of The Japan Institute of Electronics Packaging
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Table 4
Pros and cons of three possible structures for FEM
analysis.
Pros
➘ Realization
for the
fabrication
Cons
➘ Known warpage
mechanism
discussion
Fig. 12 Cross-sectional illustrations of (a) Structure E and
(b) Structure F.
➘ Realization for
the fabrication
➘ Further warpage
➘ Remaining two
mechanism
factors’ and further
discussion
warpage mechanism
discussion
➘ No realization
for the wiring
fabrication
Obviously, Structure D was warped by another mechanism. To identify candidate factors, we performed a FEM
simulation.
4.
Fig. 13 Results of factor analysis experiment: (a) warpage
form for Structure E and (b) for Structure F.
FEM Simulation
First, we identified an appropriate structure for the FEM
simulation. The pros and cons for possible structures are
listed in Table 4. Structure E was not considered because
its process flow and resin configuration are the same as
tures had embedded bare Si chips, simulating LSI chips.
those for Structure D. As shown in Table 4, the fabrication
They were the same thickness and size as the LSI chips
process flow for Structure C has already been developed,
used for Structures C and D. The control sample structure,
so fabrication is not a problem. However, the measured
‘Structure E,’ is shown in Fig. 13 (a). It had the same resin
warpage is basically explained already, so this structure is
configuration and was fabricated in the same way as Struc-
not suitable for further warpage investigation. The fabrica-
ture D. The experimental structure, ‘Structure F,’ is shown
tion process flow for Structure D has also been developed.
in Fig. 13 (b). It was fabricated using a ‘simultaneous lam-
Moreover, the warpage factor for this structure is not fully
ination’ process to eliminate the two remaining factors.
explained by a known mechanism. Additionally, with this
First, bare Si chips and a reinforcement layer with chip
structure, we can discuss the other two factors. The war-
holes were set in place. Then, the two resin layers were
page mechanism for Structure F is also unknown, but a
laminated onto the upper and lower sides of the chip and
fabrication process with wiring has not been developed.
reinforcement layer simultaneously. Next, the entire pack-
We thus used Structure D for our thermo-mechanical FEM
age was cured all at once. As a result, the thermal history
simulation using ANSYS mechanical.
was balanced, and there was no need for an adhesive layer.
The model used for the simulation is illustrated in Figs.
The warpage profiles for Structures E and F are shown
14 and 15. The subject of the simulation was a work of sev-
in Fig. 13. As these warpage were too large for a stylus sur-
eral 27 × 27 mm packages, and by setting symmetric
face profiler or the shadow Moiré technique, we used a
boundaries in the simulation model, we calculated the
microscope that enabled us to measure the vertical level of
model of one package in a practical manner.
the focus point and focused on certain points on the mea-
We set the fan-out wiring layer on the top, just as illus-
surement line (Fig. 9). The warpages for the two struc-
trated in Fig. 6. As shown in Fig. 14, we divided the first
tures were almost the same. They exceeded warpage Wc
fan-out wiring layer (CAD design shown in Fig. 14 (a)) in
for both structures. These results indicate that these two
the model into nine parts, and set the physical properties
other factors, imbalance in the thermal history of the resin
of the parts between Cu and air on the basis of the area
layers and thermal stress in the adhesive layer, were not
ratio of the wirings, as shown in Fig. 14 (b). The cross-
the main factors in the package warpage.
section line on the model shown in Fig. 14 (b) defines the
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Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (7/10)
there is no insulation material but air between the Cu wirings.
We used the ‘birth & death’ method [12] to simulate the
fabrication process flow. In this method, insulator materials such as resin and adhesive layers appear (are ‘born’) at
the same time that these components are cured in the
actual procedure, as shown in Table 5. The Cu plate disappears (‘dies’) when it is etched out in the actual procedure.
Fig. 14
(a) Top view of Structure D package wiring layer and
Other materials, such as Cu and Si, appear (are ‘born’)
(b) top view of FEM model for ANSYS mechanical analysis,
with the insulator materials, or between processes. In this
which is divided into nine parts on basis of Cu area ratio of wir-
simulation, the physical properties of the material, such as
ing.
Young’s modulus, the CTE values, the Poisson ratio, and
the glass transition temperature, were used as parameters
in the calculation. However, the chemical shrinkage factors of the resins were not parameterized. Therefore, we
were unable to verify the thermal history imbalance in this
simulation. The points labeled I–VII on the thermal condition chart in Table 5 are the process points at which the
residual stresses were observed. Three observation points
were set for the Cu plate etching process to enable
detailed analysis of the warpage mechanism.
Contour maps of the residual stresses at the observation
points (I–VII) are shown in Figs. 16 and 17 as seen from
the cross section line in Fig. 14 (b). The scale for the residual stress is shown to the right of Fig. 16. The black and
white shadings correspond to compressive and tensile
residual stress, respectively.
Fig. 15 Cross-sectional views of embedded LSI components:
The first residual stress map, Fig. 16 I, is for the room
(a) material configuration defined using ANSYS mechanical
temperature point after curing the balance-resin layer. The
and (b) actual component configuration.
resin layer showed about 300–400 MPa tensile stress due
to shrinkage. The second map, Fig. 16 II, is for the room
cross-sectional maps of the residual stress contour maps.
temperature point after mounting the LSI. Due to the CTE
Figure 15 shows cross-sectional views of (a) the actual
gap between Cu and Si, the Cu plate showed 0–600 MPa
components in the LSI chip margin area and (b) the mate-
tensile stress, and the LSI chip showed −100 to 0 MPa
rials defined for the simulation. The first fan-out wiring
compressive stress. The third map, Fig. 16 III, is for the
layer, labeled ‘9’ in Fig. 15 (a), corresponds to the ‘Cu + air’
room temperature point after lamination and curing of the
material in Fig. 15 (b), which means that, in this layer,
reinforcement and cover-resin layers. The reinforcement
Table 5 ‘Birth and Death’ simulation processes for Structure D.
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Transactions of The Japan Institute of Electronics Packaging
Vol. 3, No. 1, 2010
Fig. 18
Residual stress contour maps of cross-sectional views
Fig. 16 Residual stress contour maps of cross-sectional views
with enhanced vertical deformation for last two process points
for process points I (balance resin layer lamination), II (LSI
shown in Fig. 17: (a) VI and (b) VII.
mounting), and III (LSI embedding).
Fig. 17 Residual stress contour maps of cross-sectional views
for process points IV–VII (Cu plate etch-out).
Fig. 19
Overhead views of Structure D at process point after
Cu plate etch out: (a) complete package simulation model, (b)
layer showed 0–100 MPa tensile stress.
Maps IV–VII show the residual stress distributions for
the Cu plate-etching process. At the earlier points of the
maximum principal stress vector map for central region, middle layer meshes of chip and surrounding resin, and (c)
enlarged and simplified figure of nearside edge of (b).
process (IV-V), there was 100–200 MPa tensile stress for
the reinforcement layer. At the following point (VI), 100–
chip showed tensile stress of between 600 and 700 MPa for
200 MPa tensile stress remained in almost all regions of
both maps, so this part also had little effect on the war-
the reinforcement layer; however, in the vicinity of the LSI
page.
chip, tensile stress was greater than 400 MPa. At the last
However, lateral to the chip, the tensile stress distribu-
point (VII), there was almost zero stress in the reinforce-
tion was clearly different. Along with the Cu-etching pro-
ment layer while there was stress greater than 500 MPa
cess, the upper parts of the lateral sides of the chip showed
near the LSI chip.
stronger tensile stresses while the lower parts of the lateral
These results indicate that compressive stress in the LSI
sides showed weaker tensile stresses. This means that the
chip and/or Cu plate, caused by reinforcement layer
tensile stresses on the lateral sides of the chip were
shrinkage, gradually concentrated in the vicinity of the LSI
released in the lower parts. This caused the chip to warp
chip as the Cu plate was etched. The compressive stresses
convexly on its lateral side, as shown in Fig. 18 (b).
were mainly balanced by the reaction force of the thick Cu
plate before point V.
To discuss the directions of the stress in the chip itself
and in its vicinity, as shown in Fig. 18 (b), we use Fig. 19
Figures 18 (a) and (b) shown enlarged images of the VI
(a), which shows an overhead view of the ANSYS simula-
and VII contour maps, with vertically enhanced deforma-
tion model for the entire Structure D package after Cu-
tion or warpage. Figure 18 (a) shows the contour map for
plate etching. The chip and its surrounding region are
a sample with a Cu plate one-third the original size, and
enlarged in Fig. 19 (b) and shown as a map of the maxi-
Fig. 18 (b) shows the map for a sample without a Cu plate.
mum principal stress vectors for each mesh of the model.
The lower side of the LSI chip showed tensile stress of
The meshes in the map are located in the central region of
around 600–700 MPa for both maps, meaning that this part
the middle layer of the package, including the LSI chip
had no effect on the warpage. The upper side of the LSI
meshes. The principal stress vectors are set to be positive
54
Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (9/10)
in tensile, and negative in compressive, just as for Figs. 16,
that the stresses increased with decreasing Cu-plate thick-
17, and 18. Figure 19 (c) shows an enlarged and simplified
ness, and that the warpage was caused by the release of
illustration of four meshes at the near edge of the map in
these tensile stresses, along with the compressive stress in
Fig. 19 (b). The mesh with ‘Vector A’ is for a part of the
the chip. Therefore, simple structural considerations are
chip, and the other three meshes are for parts of the sur-
insufficient for obtaining a reduced-warpage structure. In
rounding resin-GC area. As these vectors in Fig. 19 (c)
this study, when the Cu plate thickness was 100 μm or
show, the resin-GC meshes have tensile stresses parallel
less, we did not find a package without substantial war-
to the chip side as maximum principal stresses. In con-
page, which was the case with Structures D and F as well.
trast, the maximum principal stress for the chip mesh is
The material properties should also be considered, which
compressive stress in the vertical direction (‘Vector A’).
could change these balanced structures into reduced-
This means that the minimum and middle principal
warpage structures. One possible consideration for the
stresses for the chip, which should be larger compressive
material properties is the use of a resin with less tensile
stresses than the maximum principal stress shown as
stress in the areas lateral to the LSI chips. The resin could
‘Vector A’, are in horizontal directions.
be stiffer to reduce the CTE mismatch or softer to reduce
In short, these tensile stresses were caused by the
the elastic modulus.
shrinkage of the resin and GC surrounding the LSI chip.,
For the stress balance of these tensile stresses, the com-
Acknowledgments
pressive stresses were generated in the chip horizontally.
We thank Dr. Yasunori Mochizuki, Mr. Kazuhiro Baba,
Therefore, from Fig. 18 (b), we can understand that the
Mr. Tomoo Murakami, Mr. Masanobu Hashimoto, and Dr.
tensile stresses surrounding the chip (Figs. 19 (b) and (c))
Takashi Harada of NEC Corporation, and Dr. Hideki
were partially released in the lower parts of the structure
Sasaki of Renesas Electronics Corporation for their
lateral to the chip after Cu-plate etching. This stress
encouragement and useful feedback and suggestions. We
release created substantial convex warpage in the region
also thank Mr. Seiicihro Ohkawa and Ms. Keiko Kishino of
surrounding the chip. Also, the compressive stresses cre-
NEC Informatec Systems Ltd. for their guidance on the
ated in the chip caused the entire chip to warp convexly,
simulation.
as shown in Fig. 18 (b).
We thus conclude that for Structure D, the Cu-plate
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