Introduction
The 16-bit up-counter is a 16-bit wide counter that counts from
20 to 216 − 1 or all ones, as shown in the table. Here we have a D-latch that is used to create a
master slave D flip flop that we used in our design.
This master-slave D flip flop uses 2 D-latches in series. The data enters in the negative edge of
the clock and the output responds on the positive edge of the clock. The Q outputs correspond
to every bit of the 16-bit wide counter from Q0 to Q15 as shown in the table.
Design of Synchronous 16-bit counter transmission gate schematic
Here we have the D flip flop master-slave design using transmission gates, the master stage is
shown in blue and the slave stage is shown in orange. We chose to do a positive-edge triggered
D flip-flop, mainly because is the standard design.
Transmission Gate Master-Slave D Flip Flop
In the right we have the transistor level schematic for the transmission gate D master-slave flip
flop, we have four transmission gates, four inverters and a clock which also uses an in inverter
to invert the signal for the transmission gates. The output for that bit is at the top.
Design 4-Bit counter
To simplify the design we used the counter shown in the image on the right. This is a four bit
counter which is attached to an incrementer circuit. This incrementer circuit is made of AND and
XOR gates which takes the enable bit = 1, and it cascades through the AND gates until it
reaches the end when all the bits are 1, this creates a carry out bit which serves as the enable
input signal to make the counter bigger than 4 bits. So attaching 4 4-bit counters with
incrementers we created the 16 bit counter.
Here is the schematic for the incrementer circuit for one D flip flop. Here is the XOR, the AND
gate and the ENABLE bit.
Transistor level 1-bit counter transmission gate
Here is to show the schematic of one D flip flop with its corresponding incrementing gates.
Transmission Gate 16-Bit Synchronous Counter Schematic
Here is the design of the 16-bit counter, we see the enable signal and the clock and the cout on
bit 4 that feeds to the next four enable signal.
16-bit counter Transmission gates Schematic Simulation
This is the view of the entire schematic simulation. To show more detail we zoomed in 4 bits at
a time.
We Have the first 8 bits from Q0 to Q7, and we see how each wave stretches doubling the time
of the previous bit so the counter is going up.
Here we have the last 8 bits from Q8 to Q15
Design of Synchronous 16-bit counter Layout
Just like the schematic, here we have the incrementing circuit with the AND, XOR, clock and
enable signals. Next to it is the flip flop, here we can see the 4 inverters and 4 transmission
gates.
Here is the entire layout for the 16-bit Counter