INSTRUCTION SET & ARCHITECTURE
OF
CISC & RISC PROCESSORS
BY
JYOTIRMOTY BERA
Contact Us : www.linkedin.com/in/jyotirmoybera
History of CISC & RISC
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1950s IBM instituted a research program.
1964 Release of System/360.
Mid-1970s improved measurement tools demonstrated on CISC.
1975 801 project initiated at IBM's Watson Research Centre .
1979 32-bit RISC microprocessor (801) developed led by Joel Birnbaum.
1984 MIPS developed at Stanford, as well as projects done at Berkeley.
1988 RISC processors had taken over high-end of the workstation market.
Early 1990s IBM's POWER (Performance Optimization With Enhanced
RISC) architecture introduced w/ the RISC System/6k
AIM (Apple, IBM, Motorola) alliance formed, resulting in Power PC
What is CISC ?
A complex instruction set computer is a computer where
single instructions can execute several low-level operation’s
(such as load from memory, an arithmetic operation, and a
memory store) or are capable of multistep operation or
addressing modes with in single instructions.
Need of CISC
▰ In the past, it was believed that hardware design was easier than
compiler design.
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Most programs were written in assembly language.
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Hardware concerns of the past:Limited and slower memory
Few registers
CISC Characteristics
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A large number of instructions.
Some instructions for special tasks used infrequently.
A large variety of addressing modes (5 to 20).
Variable length instruction formats.
CISC Architecture
▰ The essential goal of a CISC architecture is to attempt to
provide a single machine instruction for each high level
language instruction .
Ex: -IBM/370 computers
Intel Pentium processors
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Advantages of CISC :Microprogramming is easy assembly language to implement,
and less expensive than hard wiring a control unit.
▰ Disadvantages of CISC:The performance of the machine slows down due to the amount of
clock time taken by different instructions will be dissimilar.
What is RISC ?
A reduced instruction set computer is a computer which
only use simple instructions that can be divide into multiple
instructions which perform low level operation with single
clock-cycle.
RISC Characteristics
▰ Relatively few instructions 128 or less .
▰ Relatively few addressing modes. Memory access is limited to LOAD and
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STORE instructions.
All operations done within the registers of the CPU.
This architectural feature simplifies the instruction set and encourages the
optimization of register manipulation.
An essential RISC philosophy is to keep the most frequently accessed
operands in registers and minimize register-memory operations.
Fixed Length, easily decoded instruction format Typically 4 bytes in length.
Single cycle instruction execution .
Done by overlapping the fetch, decode and execute phases of two or three
instructions known as Pipelining.
Large number of registers in the processor unit.
Use of overlapped Register Windows.
RISC Architecture
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Advantages of RISC :RISC architecture has a set of instructions, so high-level
language compilers can produce more efficient code.
The speed of the operation can be maximized and the
execution time can be minimized.
Disadvantages of RISC :The first level cache of the RISC processors is also a disadvantage
of the RISC, in which these processors have large memory
caches on the chip itself. For feeding the instructions, they
require very fast memory systems
Comparison Between CISC & RISC
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