Gate-oxide reliability and failure-rate reduction of
industrial SiC MOSFETs
T. Aichinger1, and M. Schmidt2
1. Technology Development SiC, Infineon Technologies Austria AG, Siemensstraße 2, 9500, Villach, Austria
Phone: +43 5 1777 18602, e-mail: thomas.aichinger@infineon.com
2. Reliability & Qualification, Infineon Technologies AG, Am Campeon 1-15, 85579, Neubiberg, Germany
I.
INTRODUCTION
High numbers of initial gate-oxide failures have hampered
the commercialization of SiC MOSFETs for many years, and
provoked skepticism whether SiC MOS switches would ever be
as reliable as their Si counterparts. During the last decade, SiC
technology has substantially matured and SiC MOS devices
have exhibited gradual improvements in gate-oxide reliability.
This has opened the door for their successful introduction into
the mass market.
In the field of gate-oxide reliability, there is much expertise
that can be transferred from Si to SiC, however, there are also
some SiC-specific features which need to be taken into account.
One important difference between SiC and Si is the typically
much higher early (“extrinsic”) failure probability of SiC MOS
structures. To make SiC MOSFETs as reliable as their Si
counterparts, one has to minimize the gate-oxide defect density
during processing, and implement clever screening techniques
that identify and eliminate potentially weak devices, e.g. in the
electrical end test. In this study, we discuss the ability of gatevoltage pulse screening to reduce the early failure probability
of industrial SiC MOSFETs. We also verify the effectiveness
of this screening by means of extensive reliability tests. The
proposed screening procedure is similar to the so-called gate
stress test known from silicon technology [1-2].
The enabler for a fast and efficient gate-voltage screening is a
much thicker bulk-oxide than what is typically needed to fulfill
intrinsic lifetime-targets [3]. The thicker bulk-oxide allows the
use of screening voltages much larger than the typical device
use-voltage. In this way, SiC MOSFETs can reach the same
excellent level of gate-oxide reliability as Si IGBTs [4].
II.
INTRINSIC AND EXTRINSIC GATE-OXIDE RELIABILITY
Intrinsic gate-oxide reliability depends on the physical
breakdown strength of SiO2 as well as on temperature and
electric field during operation. The larger bandgap of SiC with
respect to Si reduces charge injection barriers into the SiO2. As
a consequence, Fowler-Nordheim tunneling emerges at lower
Typically, gate-oxide reliability during a single chip life
(e.g. 20 y) is not governed by intrinsic but by extrinsic failures
[8], cf. Fig. 2. Extrinsic failures are “early” failures due to tiny
distortions in the gate-oxide, which act as local oxide thinning,
cf. Fig. 3. Such distortions may originate from EPI or substrate
defects [9], metallic impurities, particles or other extrinsic
inclusions in the gate-oxide incorporated during device
fabrication. Devices with extrinsic defects fail early because of
a locally enhanced electric field at the defect site. The time to
failure depends mainly on the properties of the defect and is
widely independent of the bulk-oxide thickness.
(b) 1.E+10
(a) 1.E+10
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
20y
t63% (s)
Index Terms--Dielectric breakdown, Semiconductor device
reliability, Silicon carbide, Power MOSFET, Weibull distribution
electric fields in comparison to Si MOS systems. It was
speculated in the past that higher gate tunneling currents could
be a built-in weakness of SiO2 fabricated on SiC that
presumably leads to reduced intrinsic gate-oxide lifetimes [5].
To investigate that we performed time-dependent dielectricbreakdown (TDDB) measurements of thick-oxide (40-80 nm)
SiC and Si power MOSFETs, cf. Fig. 1. Consistent with [6] and
in contrast to the concerns raised in [5], we found similar
intrinsic breakdown characteristics of SiC and Si MOS
technologies. The breakdown dynamics can be well described
by the thermochemical linear E-model [7] indicating that the
electric field and not the tunneling current governs TDDB in
thick-oxide power devices. To guarantee very low (ppm range)
intrinsic failure probabilities within 20 y at typical operation
conditions ( , =15-20 V at 150°C), gate-oxide thicknesses
in the range of 40 nm and higher would be sufficient. However,
this does not automatically imply that reliability is secured
overall for SiC MOSFETs with gate-oxides in this range and
slightly above.
t63% (s)
Abstract—We discuss various gate-oxide reliability aspects of
silicon carbide (SiC) MOSFETs and highlight similarities and
differences of SiC and silicon (Si) technology. Basic concepts of
electrical gate-oxide defect screening are introduced and failure
probability and the failure-rate after screening is studied based
on Weibull statistics. To be able to quantify very low extrinsic
failure probabilities (e.g. after electrical screening), we present a
new kind of test procedure which we call the “marathon stress
test”. The results of this test demonstrate that excellent gate-oxide
reliability of commercially available SiC trench MOSFETs can be
achieved after applying a sufficiently precise electrical screening.
0 10 20 30 40 50 60 70 80
Gate-voltage [V]
1.E+10DMOS
TrenchMOSFET
1.E+00SiC-Technology
Si-Technology
4.00
6.00
8.00
GOX thickness ≈30nm
GOX
thickness
≈40nm
10MV/cm
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
1.E+01
1.E+00
20y
4 5 6 7 8 9 10 11 12 13 14
Electrical Field in GOX [MV/cm]
TrenchMOSFET
TrenchMOSFET
Si-Technology
SiC-Technology
12.00
14.00
16.00
GOX thickness ≈60nm
GOX thickness ≈70nm
10.00
Figure 1. TDDB analysis of commercially available SiC and Si power
MOSFETs; all measurements were performed at stress temperatures between
140-150°C. (a) t63% measurement results versus applied gate-voltage. The
dashed box represents typical use-voltages of SiC power devices in industrial
applications. Intrinsic reliability is secured by a gate-oxide thickness in the
range of 40 nm. (b) t63% data normalized to the electrical field in the gate-oxide.
Both Si and SiC MOSFET technologies can be modeled by the linear E-model
in the regime of high electrical fields where lifetime critical extrinsic defects are
expected to fail during electrical screening. The dielectric field strength of SiO2
on SiC is in the same range as on Si, i.e. ≈ 10 MV/cm.
978-1-7281-3199-3/20/$31.00 ©2020 IEEE
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− (1 − )
intrinsic branch
In Equation (1), we define the reduction of the extrinsic
field-failure probability due to electrical screening as screening
efficiency (
).
chip lifetime
critical
+
uncritical
=
∙
(1)
SiC MOSFET
-6
( )
Figure 2. Schematic representation of the extrinsic and intrinsic Weibull
distributions for SiC MOSFETs and Si MOSFETs having the same oxide
thickness and area. Due to a higher electrical defect density, SiC MOSFETs
exhibit 3-4 orders of magnitude higher extrinsic defect densities in the gateoxide. The chip lifetime is the time the device has to survive in the application
under normal use conditions.
Figure 3. Schematic representation of extrinsic defects in SiO2. Extrinsic
defects can be physical oxide thinning due to, for instance, a distorted oxide
on top of an EPI/substrate defect or electrical oxide thinning caused by a
degraded dielectric field strength due to inclusions of metallic impurities,
particles or porosity.
Assuming a currently typical electrical defect density in SiC
of 0.1 up to 1 defect/cm2, one would expect roughly 1-10 %
early failing devices in an ensemble of SiC MOSFETs with an
electrically active gate-oxide area of 10 mm2. This means that
we can expect that 90-99 % of the devices are free of extrinsic
defects, and show excellent gate-oxide reliability. The key to
achieving Si-like gate-oxide reliability is to screen the original
population for the 1-10 % early failing devices with critically
thin extrinsic defects, sort them out and throw them away. The
remaining good devices can be delivered with a much reduced
failure probability. In the next paragraph we are going to
elaborate on the basic principles, parameter dependences, and
the effectiveness of electrical gate-oxide screening.
III.
SCREENING OF CRITICAL EXTRINSIC DEFECTS
During electrical screening, each device is subjected to a
gate-voltage stress pulse with defined amplitude and time. The
stress pulse is designed to destroy devices with critical extrinsic
defects while devices without extrinsic defects or with only
non-critical extrinsic defects survive. Devices which fail in the
screening test show a significantly increased gate leakage
current and can be removed from the original population. The
remaining surviving, respectively screened, population shows a
significantly improved gate-oxide reliability.
The screening efficiency depends on the precise screening
conditions, i.e. the screening voltage ( , ), the screening
) and the screening time (
), and on the
temperature (
mission profile of the device in the application, i.e. the use) and the use time
voltage ( , ), the use temperature (
). It can be derived from the linear E-model that the
(
screening efficiency strongly depends on the ratio of screening
voltage to use-voltage. The larger the screening voltage with
respect to the gate use-voltage, the more efficient is the
screening and the lower is the field-failure probability after
screening.
Fig. 4 shows an example plot of screening efficiency vs.
screening voltage to use-voltage ratio. The curve was derived
assuming screening at room temperature and a simplified
device mission profile of 20 y operation at 150°C. The
acceleration factors used were determined by measured failure
data. To improve from an original lifetime failure probability of
=1 % (10-2) toward the ppm range (10-6), screening
with gate over-voltages of a factor of only 2 is typically not
sufficient. Using only double of the use-voltage as screening
=36 V if devices are normally operated at
voltage, e.g.
,
=18 V, reduces the lifetime failure probability only by
,
≈ 0.1). Higher screening
roughly one order of magnitude (
for use-voltage ratios are needed to make the screening more
efficient.
)
extrinsic branch
Si MOSFET
+
is the field-failure probability within the next
upcoming chip lifetime after having “aged” the surviving
population by the screened use time (
). We define chip
) as the time that the device has to survive in the
lifetime (
application under normal use conditions, e.g. 20y at
and
,
. The screened use time is defined as the equivalent time at
use-voltage and use temperature which is consumed for the
screened population due to the gate stress pulse.
is the
hypothetical field-failure probability of the unscreened original
population within one chip lifetime.
screening efficiency (
-2
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0
1.5
2.0
2.5
,
/
3.0
3.5
4.0
,
Figure 4. Screening efficiency (reduction of extrinsic failure probability) as a
function of screening voltage to use-voltage ratio. The calculation was done
assuming screening at room temperature and a simplified device mission
profile.
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It should be noted that screening efficiency can be improved
to a limited extent by increasing the screening temperature
and/or increasing the screening time. Stressing at elevated
temperatures for much longer times would then be called a
burn-in and is not a classical screening approach. Compared to
a short gate-voltage screening at room temperature, a burn-in at
elevated temperatures involves several disadvantages. It is
time-consuming, costly, and may cause severe degradation of
threshold voltage and on-resistance due to long-lasting gate
stress at high bias and high temperature, which is known to
trigger bias temperature instabilities [10].
IV.
RELIABILITY VS. PERFORMANCE
In this section, we discuss the trade-offs between gate-oxide
reliability and device performance, which have to be faced
when aiming for efficient gate-oxide screening. As discussed in
the previous section, the key to efficient gate-oxide screening is
a high ratio of screening voltage to use-voltage. This can be
achieved by using a low gate use-voltage and/or a high
screening voltage. Both measures affect either directly or
indirectly the channel resistance of the SiC MOSFET.
In a first order approximation, the channel resistance of a
SiC MOSFET is given as
=
∙
∙
∙
∙
∙(
)
,
.
(2)
is the channel resistance, is the width of
In Equation (2),
the channel, is the length of the channel, is the free electron
is the gate use-voltage,
is the threshold
mobility,
,
is the bulk gate-oxide thickness.
voltage of the device and
Lowering the gate use-voltage directly decreases the on) and therefore increases the
state overdrive ( , −
channel resistance of the device. Normally, the on-state gatevoltage is given by design. SiC power MOSFETs typically
operate at gate use-voltages in the range of 15-20 V, maximal
ratings are typically around 20-25 V.
Using higher screening voltages requires the use of a thicker
bulk-oxide than what is normally needed to fulfill intrinsic
lifetime targets at typical gate-use-voltages (≥40 nm). The
thicker bulk-oxide limits the electric field during high voltage
screening and ensures that devices which pass the screening test
are not electrically degraded, i.e. do not show a permanent
threshold voltage shift and/or a degraded channel mobility.
Following (2), a thicker bulk-oxide increases the channel
resistance of the device in a similar way as lowering the gate
use-voltage.
Fig. 5 shows schematic cross sections of a SiC DMOSFET
(a) and a SiC trench MOSFET (b) power device. Also shown
are different contributions to the total on-resistance (
). In
a power MOSFET, the channel resistance ( ) is only one
part of the total on-resistance of the device
=
+
+
+
is the JFET resistance,
In Equation (3),
epitaxial layer resistance of the drift region, and
resistance of the highly doped SiC substrate.
.
(3)
is the
is the
Figure 5. Schematic drawing of a SiC DMOSFET (a) and a SiC trench
MOSFET (b). The total on-resistance of a SiC power device typically consists
of channel, JFET, epitaxial layer and substrate resistance.
can be major portion of the total onIn SiC MOSFETs,
resistance, in particular, for devices of lower voltage classes
which provide a comparatively small drift-zone resistance.
Ultimately, high screening efficiency, and hence excellent
gate-oxide reliability, is not entirely for free, but comes at the
cost of a slightly enhanced on-resistance which needs to be
compensated by a somewhat larger device area.
V.
FAILURE PROBABILITY AND FAILURE-RATE AFTER
SCREENING
After screening, the chance of failing during the next chip
lifetime is significantly reduced, but not to zero.
The cumulative distribution function (CDF) of the Weibull
distribution [11] describes the probability of failure before a
given time
( ) = 1−
−
.
(4)
In Equation (4),
is the scale parameter representing the
characteristic time when 63.2% of all devices have failed and
is the shape parameter representing the slope of the extrinsic or
intrinsic Weibull distribution.
The failure-rate (also known as hazard function) ℎ( ) is the
probability of a sample to fail in the next moment, given that
the sample has not failed until now
( )
ℎ( ) =
( )
=
.
(5)
The so-called bathtub curve is the graphical representation of
the hazard function as a function of the use time. Fig. 6 (a)
schematically illustrates the shapes of the bathtub curves of
screened and unscreened SiC MOSFET device populations.
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(b) Failure probability
ℎ( )
>1
( )
>1
unscreened
<1
screened
≈1
unscreened
<1
In Reference [3] the time evolution of the Weibull
distribution after screening is derived from the conditional
probability of failure at +
, given that the device has
survived for the time
.
screened
≈1
( )
Fig. 6 (b) schematically illustrates the failure probability of
screened and unscreened devices. Within the time of constant
failure hazard after screening ( ≪
), the failure probability
is reduced by several orders of magnitude, and increases nearly
linearly with time. This corresponds to a shape parameter of
≈ 1 in the Weibull distribution.
VI.
( )
Figure 6. Schematic representation of the hazard function (a) and the cumulative
distribution function (b) of unscreened (dashed) and screened (dotted) device
populations. Electrical screening cuts into the early failure regime where the
hazard function is decreasing over time ( < 1). The failure-rate after screening
is nearly constant ( ≈ 1) yielding a linear increase of the failure probability
over time.
Note that the bathtub curves in Fig. 6 (a) are drawn without
a flat plateau [12] of constant failure hazard ( = 1) which is
often included between the region of early failures ( < 1) and
the wear-out phase ( > 1). Indeed, such a plateau does not
exist when assuming a variety of extrinsic defects within a large
number of samples with a uniform distribution of oxide
thicknesses that may range from a few nanometers up to nearly
the ideal bulk-oxide thickness.
In the area of early failures, where the shape parameter is
below 1, Weibull statistics predict a decreasing failure hazard
over time. In the wear-out regime of the bulk-oxide, where the
shape parameter is larger than 1, Weibull statistics predict an
increasing failure hazard over time.
Electrical screening cuts into the early failure regime of the
bathtub curve by eliminating weak devices which are destroyed
by the gate pulse. Because of the decreasing failure-rate over
time ( < 1), the failure hazard of the surviving population is
significantly reduced after screening. The lifetime consumed by
the screening (
) is typically negligible in comparison to the
intrinsic gate-oxide lifetime.
ℎ( +
)=
∙(
)
1+
.
(6)
1.E+15
1.E+14
1.E+13
1.E+12
1.E+11
1.E+10
1.E+09
1.E+08
stress time (s)
The hazard function of the screened population can be
written as
EXTRINSIC GATE-OXIDE RELIABILITY EVALUATION
Depending on the applied gate-voltage and stress time, there
are different operation regimes that may trigger extrinsic or
intrinsic failures. Fig. 7 schematically illustrates these regimes
for SiC devices with an assumed gate-oxide thickness of about
70 nm. The extrinsic failure regime, which is relevant for
normal device operation and burn-in, is confined by an intrinsic
high-voltage breakdown limit (dashed line) with strong voltage
acceleration due to impact ionization and by an intrinsic lowvoltage breakdown limit (dotted line) with weaker voltage
dependence due to the interaction of molecular dipoles with the
electric field. The high voltage limit is well studied and can be
characterized relatively easily by standard wafer or package
level time-dependent dielectric-breakdown (TDDB) tests. The
trend and slope of the low voltage limit is much harder to
investigate, because very long (even unfeasible) stress times are
needed to see intrinsic failures at gate biases close to use
conditions. As a consequence, there are only a few studies on
low-voltage acceleration factors and the reported values show
a large spread. Nevertheless, even using the smallest reported
acceleration factors, intrinsic failures of devices with 60-70 nm
gate-oxide thickness remain far out of reach at typical use
conditions and times.
typical
parameters for
marathon test
1.E+07
1.E+06
1.E+05
devices in
application
(a) Hazard rate
1.E+04
1.E+03
1.E+02
1.E+01
typical
parameters
for burn-in
(not performed)
1.E+00
Equation (6) predicts a nearly constant failure hazard after
, cf. Fig. 6 (a). Note that a
screening for times ≪
sufficiently high gate pulse, even when applied for only a short
time, may already correspond to multiple chip lifetimes under
use condition (
≫
). This is because of the exponential
electric field acceleration of gate-oxide breakdown.
The failure probability of the screened population is finally
given as the integral over the hazard function
( >
)=
ℎ( )
.
(7)
final test after
device fabrication
1.E-01
1.E-02
1.E-03
0
1
2
3
4
scaled gate-voltage [VGS,use = 1]
Figure 7. Illustration of intrinsic (white region) and extrinsic (grey region)
failure regimes as a function of gate-voltage and stress time (assumed gateoxide thickness 70 nm). Failures during normal device operation and during
burn-in typically fall into the extrinsic breakdown regime. To investigate
extrinsic failure probabilities, a new “marathon stress test” is suggested which
tests a large number of devices at moderate gate biases for long periods. The
intrinsic failure regime is typically tested under highly accelerated stress
conditions using standard TDDB tests.
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For the following experimental study, we used 1200 V SiC
trench MOSFETs with an area of about 10 mm2. The hardware
was electrically screened prior to the marathon stress test. To
reach a total stress test capacity of >3000 devices, we used 3
furnaces in parallel. In one test run we stressed 1000 devices at
3 different gate bias levels (-15 V/+25 V/+30 V) for 100 days at
150°C. The gate bias levels were chosen far below the intrinsic
breakdown limit of these devices (>50 V) but still harsh enough
to trigger a few extrinsic failures within the duration of the test.
Fig. 9 shows number of failures out of 1000 tested devices.
In sum, we performed in this study 3 independent marathon test
runs on 3 sample groups of electrically screened devices with
different extrinsic defect densities. The purpose of the
experiment was to monitor and quantify the efficiency of
various improvements in cleaning, processing and electrical
screening. Within 100 days at 150°C, the best group (group 3)
showed only 1 failure out of 1000 devices at VGS=+30 V and 0
failures at VGS=+25 V and VGS=-15 V.
The Weibull distributions of the marathon stress tests
performed at VGS=+30 V are depicted in the upper left corner
of Fig. 10. To get the Weibull distributions at use condition, we
converted the times to failure at VGS=+30 V to times to failure
at VGS=+18 V. This was done using the linear E-model and
considering a locally thinner gate-oxide at the location of the
extrinsic defect spot where the breakdown occurred. The result
of the conversion is depicted in the upper right corner of Fig. 10.
Note that all failures observed in the 30 V marathon test run
would have happened far beyond the specified product lifetime
(20 y) at a nominal gate bias of 18 V.
6 MOSFETs
in 1 package
21 packages
on 1 stress
board
3 furnaces for 3 diff. gate biases
1
8 stress boards
in 1 furnace
2
3
Figure 8. Marathon stress test setup capable of stressing 3 x 1000 SiC
MOSFETs in parallel. Devices are packaged and mounted on stress boards.
Stress tests are performed in a furnace at elevated temperatures using different
stress biases.
10
failures within 100 days @ 150°C
failures out of 1000 DUTs
9
8
VGS=+30V
VGS=+25V
7/1000
7
VGS=-15V
6
5
4
3
2/1000
2
1/1000
1/1000 1/1000
0/1000 0/1000
1
0/1000 0/1000
0
group 1
group 2
group 3
Figure 9. Number of failures out of 1000 tested SiC MOSFETs using 3 split
groups with different extrinsic defect densities. In sum, 9000 DUTs (3000 per
group) were tested for 100 days at 150°C using 3 different gate biases
(+30 V/+25 V/-15 V).
1.0E-01
30V
1.0E-02
1.0E-03
-ln(1-F)
Thus, to make reliable predictions about failure probabilities
under normal device operation conditions, one has to perform
stress tests that explore the extrinsic breakdown regime (grey
area in Fig. 7). In addition, one needs to test large numbers of
samples because extrinsic failures are usually rare, in particular,
after electrical screening. For this purpose, we have developed
a new kind of test procedure, which we call the “marathon stress
test”. In this test we stress large numbers of samples (>1000) in
a parameter range (voltage, temperature) as close as possible to
use conditions and comparable to typical burn-in conditions,
c.f. Fig. 7. However, contrary to burn-in, we use much longer
stress times (100 days) in order to increase the probability to
see extrinsic failures. To manage the large sample quantities
required for the marathon stress test, we have developed a
special test setup where we put 6 devices in one package, 21
packages on 1 stress board and 8 stress boards in 1 furnace, cf.
Fig. 8. In this way, we can test more than 1000 devices in
parallel in one furnace.
linear E-model
group1
group2
group3
20y
18V
group1
group2
group3
1.0E-04
100ppm
1.0E-05
10ppm
1.0E-06
1.0E-07
1ppm
=1
0.1ppm
1.0E-08
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09
time [days]
Figure 10. Weibull plots of failure probabilities for the 3 different sample
groups with different extrinsic defect densities. The marathon test results
obtained at VGS=30 V overstress were converted to a gate use-voltage of
VGS=18 V using the linear E-model.
The lifetime failure probabilities in Fig.10 can be deduced
by extrapolating the measurement data to an assumed
maximum operation time of, for instance, 20 y. For the
extrapolation we assumed a Weibull slope of = 1 since the
hardware was electrically screened prior to the marathon test. It
was explained in the previous section and in Fig. 6 that after the
electrical screening of multiple chip lifetimes, a nearly linear
increase in failure probability was expected over time due to a
virtually constant risk of failure. The final result of the shown
marathon test is that two out of the three split groups provide
single digit ppm failure probabilities for 20 y operation at 18 V
and 150°C, values fully comparable to established Si
technologies.
VII. CONCLUSIONS
Gate-oxide reliability of SiC MOSFETs has substantially
improved. However, due to larger defect densities of the SiC
material, it is still challenging to advance toward the “Si
standard”, i.e. a single digit ppm-rate. In this work, we have
demonstrated a methodology of electrical gate-oxide screening
for SiC MOSFETs with the potential for efficiently eliminating
devices with critical extrinsic defects without degradation of the
surviving population that is later delivered. In this way, a
potential reliability thread for the customer can be converted
into minor yield loss for the device manufacturer. To verify the
efficiency of our screening approach, we have introduced a new
marathon stress test, which we applied to industrial SiC trench
MOSFET devices to extract their maximum field-failure
probability for 20 y operation at 18 V and 150°C. The results of
the marathon stress test indicate that excellent gate-oxide
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reliability (comparable to Si devices) can be achieved with
industrial SiC MOSFETs using optimized device processing
and efficient electrical screening. Since efficient electrical
screening requires using high screening voltages, and thus a
thicker bulk-oxide, excellent reliability of SiC MOSFETs is to
a certain degree a trade-off with electrical performance.
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