# 1905027 A2 Merged compressed-2

```DIGITAL ELECTRONICS PRACTICALS
Bachelor of Technology
Computer Science and Engineering
Submitted by:
Paramveer SINGH
CSE A2
1905027
GURU NANAK DEV ENGINEERING COLLEGE
LUDHIANA -141006
PRACTICAL 4
Experiment
AIM : To design and verify truth table of half adder using basic
and XOR gate.
APPRATUS : Regulated power supply,trainer kit,IC’s
THEORY : Alogic circut for addition of 2-one bit members is
referred to as a half adder. As there are two inputs A and B
then according to the formula 2^n =M. Here n=2,we get M=4.
A Half Adder is defined as a basic four terminal digital device
which adds two binary input bits. It outputs the sum binary bit
and a carry binary bit
A
0
0
1
1
B
0
1
0
1
A+B
0+0
0+1
1+0
1+1
DECIMAL
OUTPUT
BINARY
OUTPUT
0
1
1
2
0
1
1
10
SUM
0
1
1
0
CARRY
0
0
0
1
From the above truth table, we can see that the sum digit of two
binary inputs is the outcome of XOR operation and we can
realize it by using an XOR gate.Carry digit of those two binary
inputs is the outcome of AND operation and we can realize it
Experiment
AIM: To design and verify truth table of full adder using basic
and XOR gate.
APPRATUS: Regulated power supply ,trainer kit ,IC’s
THEORY:
A logic circuit for the addition of 3-one bit number is referedto
as full adder. A half adder has only two inputs and there is no
provision to add a carry coming from the lower order bit when
multibit addition is performed.For this purpose a third input
terminal is added and this circuit is used to add An,Bn and
Cn+1 =C where An,Bn and the nth order bit of numbers A and
B and Cn+1 =C is the carry generator from the addition of (n-1)
the order bits.This circuit is refered to as full adder.After the
generated out of which one is sum and other is carry out.As
Full adder circuit deal with three inputs, the Truth table also
updated with three input columns and two output columns
Carry In
0
0
0
0
1
1
Input A
0
1
0
1
0
1
Input B
0
0
1
1
0
0
Sum
0
1
1
0
1
0
Carry Out
0
0
0
1
0
1
For the case of SUM, We first XOR the A and B input then we again XOR the output with Carry in.
So, the Sum is A) XOR B) XOR C
PRACTICAL – 7
Paramv eer Singh
CRN =1915056
URN=1905027
AIM: 4-Bit Binary-to- Gray and Gray-to- Binary Code Converter:
Realization using basic, XOR gates and universal gates.
THEORY:
BINARY TO GRAY CODE CONVERTER
The Binary to Gray code converter is a logical circuit that is used to convert the
binary code into its equivalent Gray code. By putting the MSB of 1 below the axis
and the MSB of 1 above the axis and reflecting the (n-1) bit code about an axis
after 2n1 rows, we can obtain the n-bit gray code.
Realization of 4-bit Binary to gray Code Converter
Here the gate used is XOR gate which is defined as follows: XOR gate (sometimes
EOR, or EXOR and pronounced as Exclusive OR) is a digital logic gate that gives a
true (1 or HIGH) output when the number of true inputs is odd. An XOR gate
implements an exclusive or; that is, a true output results if one, and only one, of
the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a
false output result. XOR represents the inequality function, i.e., the output is true
if the inputs are not alike otherwise the output is false. A way to remember XOR
is, must have one or the other but not both.
●
In the Gray code, the MSB will always be the same as the 1'st bit of the
given binary number.
●
To perform the 2nd bit of the gray code, we perform the exclusive-or (XOR)
of the 1'st and 2nd bit of the binary number. It means that if both the bits are
different, the result will be one else the result will be 0.
●
To get the 3rd bit of the gray code, we need to perform the exclusive-or
(XOR) of the 2nd and 3rd bit of the binary number. The process remains the same
for the 4th bit of the Gray code.
GRAY TO BINARY CODE CONVERTER
Binary Numbers is default way to store numbers, but in many applications binary
numbers are difficult to use and a variation of binary numbers is needed. This is
where Gray codes are very useful. Gray code has property that two successive
numbers differ in only one bit because of this property gray code does the cycling
through various states with minimal effort and used in K-maps, error correction,
communication etc.
Realization of 4-bit Gray to Binary Code converter
Here also the with the use of XOR gate we perform the code conversion from gray
to binary.
●
The Most Significant Bit (MSB) of the binary code is always equal to the
MSB of the given binary number.
●
Other bits of the output binary code can be obtained by checking gray code
bit at that index. If current gray code bit is 0, then copy previous binary code bit,
else copy invert of previous binary code bit.
PRACTICAL NUMBER- 8
Paramveer Singh
CRN =1915056
URN=1905027
AIM: Realization of 4-bit and 8-bit comparator using logic gates.
APPARATUS: Active HDL.
THEORY:
4-BIT COMPARATOR:
A comparator used to compare two binary numbers each of four bits is called a 4-bit
magnitude comparator. It consists of eight inputs each for two four bit numbers and three
outputs to generate less than, equal to and greater than between two binary numbers.
TRUTH TABLE:
Boolean Expressions:
X(A&gt;B) = A3.B3′ + x3.A2.B2′ + x3.x2.A1.B1′ + x3.x2.x1.A0.B0′
Y(A&lt;B) = A3’.B3 + X3.A2’.B2 + X3.X2.A1’.B1 + X3.X2.X1.A0’.B0
Z (A=B) = A3B3 . A2B2 . A1.B1 . A0.B0 = x3.x2. x1.x0
8-BIT COMPARATORThe 74HC688 is an 8-bit magnitude comparator. It performs comparisons of two 8-bit binary
or BCD words. Inputs include clamp diodes. This enables the use of current limiting resistors to
interface inputs to voltages in excess of VCC.
Pin Description:
Functional Description:
Features and benefits:
•
•
•
•
•
•
•
•
Compare two 8-bit words
Wide supply voltage range from 2.0 to 6.0 V
CMOS input levels
Complies with JEDEC standard: no. 7A ESD protection:
HBM JESD22-A114-F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 &deg;C to +85 &deg;C and from -40 &deg;C to +125 &deg;C
REALIZATION OF 4-BIT COMPARATOR USING LOGIC GATES AND THEIR TRUTH
TABLES ON LHS
GURUNANAK DEV ENGINEERING COLLEGE, LUDHIANA
DIGITAL ELECTRONICS
NAME – LOVEPREET SINGH
SECTION – CSE -A
U.R.N. – 1905016
C.R.N. – 1915047
EXPERIMENT-1
AND gate
Definition – A HIGH output (1) results only if all the inputs to the AND
gate are HIGH (1). If none or not all inputs to the AND gate are HIGH,
LOW output results.
Symbol –
Truth table: C = A AND B
I.C. used AND gates are available in IC packages. The 7408 IC is a well-known
QUAD 2-Input AND GATES and contains four independent gates each
of which performs the logic AND function.
For gate1
Inputs – 1A ,1B
Outputs – 1Y
For gate2
Inputs – 2A ,2B
Outputs – 2Y
For gate3
Inputs – 3A ,3B
Outputs – 3Y
For gate4
Inputs – 4A ,4B
Outputs – 4Y
Ground pin – 7
Voltage supply pin - 14
OR gate
Definition – A HIGH output (1) results if one or both the inputs to the
gate are HIGH (1). If neither input is high, a LOW output (0) results.
Symbol –
Truth table: C = A OR B
I.C. used –
OR gates are basic logic gates, and are available
in TTL and CMOS ICs logic families. The standard 4000
series CMOS IC is the 4071, which includes four independent twoinput OR gates.
For gate1
Inputs – A1 ,B1
Outputs – Q1
For gate2
Inputs – A2 ,B2
Outputs – Q2
For gate3
Inputs – A3 ,B3
Outputs – Q3
For gate4
Inputs – A4 ,B4
Outputs – Q4
NOT gate
Definition – In digital logic, an inverter or NOT gate is a
logic gate which implements logical negation.
Symbol –
Truth table: C = A NOT B
I.C. used The inverter is a basic building block in digital electronics. Multiplexers,
decoders, state machines, and other sophisticated digital devices may
use inverters.
The hex inverter is an integrated circuit that contains six (hexa-)
inverters. For example, the 7404 TTL chip which has 14 pins and the
4049 CMOS chip which has 16 pins, 2 of which are used for
power/referencing, and 12 of which are used by the inputs and outputs
of the six inverters (the 4049 has 2 pins with no connection).
NAND gate
Definition – A LOW (0) output results only if all the inputs to the gate
are HIGH (1); if any input is LOW (0), a HIGH (1) output results.
Symbol –
Truth table: C = A NAND B
I.C. used NAND gates with two or more inputs are available as integrated
circuits in transistor-transistor logic, CMOS, and other logic families.
The standard, 4000 series, CMOS IC is the 4011, which includes
four independent, two-input, NAND gates.
For gate1
Inputs – A1 ,B1
Outputs – Q1
For gate2
Inputs – A2 ,B2
Outputs – Q2
For gate3
Inputs – A3 ,B3
Outputs – Q3
For gate4
Inputs – A4 ,B4
Outputs – Q4
Ground pin – 7
Voltage supply pin - 14
NOR gate
Definition – A NOR gate is a logic gate which gives a positive output only
when both inputs are negative.
Symbol –
Truth table: C = A NOR B
I.C. used NOR Gates are basic logic gates, and as such they are recognised
in TTL and CMOS ICs. The standard, 4000 series, CMOS IC is the
4001, which includes four independent, two-input, NOR gates.
Input A1
Input B1
Output Q1
Output Q2
Input B2
Input A2
Vss
Input A3
Input B3
Output Q3
Output Q4
Input B4
Input A4
Vdd
X-OR gate
Definition – XOR gate is a digital logic gate that gives a true (1 or HIGH)
output when the number of true inputs is odd. An XOR gate implements
an exclusive or; that is, a true output results if one, and only one, of the
inputs to the gate is true. If both inputs are false (0/LOW) or both are
true, a false output results.
Symbol –
Truth table: C = A X-OR B
I.C. used –
The Exclusive-OR Gate is widely available as a standard quad twoinput 74LS86 TTL gate or the 4030B CMOS package, which includes
four independent two-input OR gates.
For gate1
Inputs – 1 ,2
Outputs – 3
For gate2
Inputs – 4 ,5
Outputs – 6
For gate3
Inputs – 8 ,9
Outputs – 10
For gate4
Inputs – 11 ,12
Outputs – 13
Ground pin – 7
Voltage supply pin – 14
PRACTICAL NUMBER-10
Paramv eer Singh
CRN =1915056
URN=1905027
AIM: Realization of Demultiplexer using logic gates.
APPARATUS: Active HDL.
THEORY:
DEMULTIPLEXER:
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of
several digital output lines. A demultiplexer of 2n outputs has n select lines, which are used to
select which output line to send the input. A demultiplexer is also called a data distributor.
Demultiplexers can be used to implement general purpose logic. By setting the input to true,
the DEMUX behaves as a decoder.
The reverse of the digital demultiplexer is the digital multiplexer Diagram:
IC 74139(Dual four input DEMUX):
IC 74139 is most commonly used dual 1-to-4 demultiplexer. It has two independent demultiplexers and
each DEMUX accepts two binary inputs as select lines and four mutually exclusive active-low outputs.
Both demultiplexers share a common set of selection lines so they are selected in parallel. Also,
each demultiplexer consists of enable pin or data input, for one demultiplexer it is active high
data input and for other it is active low data input.
PIN DESCRIPTION:
Features:• Designed specifically for high speed: Memory decoders Data transmission systems
• 74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers
• Schottky clamped for high performance
• Typical propagation delay (3 levels of logic) is 21 ns
• Typical power dissipation is 34 mW
TRUTH TABLE:
REALIZATION OF 4:1 DEMULTIPLEXER USING LOGIC GATES
```