Materials Today Volume 17, Number 4 May 2014
RESEARCH: Review
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Emerging challenges and materials for
thermal management of electronics
Arden L. Moore1,* and Li Shi2
1
IBM Corporation, 11400 Burnet Road, Austin, TX 78758, United States
Department of Mechanical Engieering and Texas Materials Institute, The University of Texas at Austin, 204 East Dean Keeton Street, Mail Stop C2200, Austin,
TX 78712-0292, United States
2
The rapid development of faster, cheaper, and more powerful computing has led to some of the most
important technological and societal advances in modern history. However, the physical means associated
with enhancing computing capabilities at the device and die levels have also created a very challenging set
of circumstances for keeping electronic devices cool, a critical factor in determining their speed, efficiency,
and reliability. With advances in nanoelectronics and the emergence of new application areas such as
three-dimensional chip stack architectures and flexible electronics, now more than ever there are both
needs and opportunities for novel materials to help address some of these pressing thermal management
challenges. In this paper a number of cubic crystals, two-dimensional layered materials, nanostructure
networks and composites, molecular layers and surface functionalization, and aligned polymer structures
are examined for potential applications as heat spreading layers and substrates, thermal interface
materials, and underfill materials in future-generation electronics.
Introduction
Over the past half-century, the drive for faster, cheaper computing
and its long-associated requirements of increasing device density
and progressive device miniaturization have served to push scientists and engineers to continually develop new and ever-improving materials, tools, processes, and design methodologies. As a
result, electronic devices and their applications have been among
the fastest advancing fields, with the characteristic dimensions of
devices shrinking past the microscale and into the nanoscale
within the matter of just two decades [1,2]. Today, many modern
electronic devices operate with critical dimensions in the tens of
nanometers. Moreover, minimum feature sizes of 14 nm and
below are being targeted for next-generation technology nodes
[1,2]. At the same time, new approaches at the die and package
integration levels such as many-core architectures and threedimensional (3D) chip stacking [3,4] are emerging as potential
means of increasing computing performance without relying on
reduced feature scaling alone. In addition, the rise of mobile
devices and touchscreen applications has driven new research
and development efforts into devices and materials compatible
with transparent and/or flexible substrate design requirements.
However, these exciting technological advances and emerging
applications are also creating thermal challenges that may serve
to ultimately limit their effectiveness, scope of implementation, or
overall feasibility.
It has been well documented that the shrinking size and escalating density of transistors and other integrated circuit devices
over time has enhanced computing capabilities at the cost of
increasing power dissipation across the device, die, and system
levels [5–7]. The power required for high performance computing
applications on some modern processor modules can reach 200–
250 W or more [8], leading to heat loads approaching as much as
1 kW for the processors alone in a four-socket computing system.
While the high magnitude of the power dissipation certainly has
implications at the system and data center levels, the power
density and its spatial distribution at the die level is also of concern
and can have important reliability and thermal management
implications. The power dissipation in modern chip architectures
*Corresponding author: Moore, A.L. (amoore@latech.edu)
1369-7021/ß 2014 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mattod.2014.04.003
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can be highly non-uniform across the die surface, with localized
functional areas where the power density is a factor of five to ten
higher than the die average [9–12]. These power-dense regions can
produce ‘hot spots’ – regions where local temperatures are significantly higher than the die average temperature [6,10–13]. Dielevel hot spot sizes may range anywhere from 500 mm2 up to 5
mm2. For electronics the overall reliability is determined by the
hottest region on the die rather than the average die temperature.
As a result, hot spots can often dictate the required higher-level
packaging and thermal management solutions including material
selections, heat sink and cold plate design, and required pumping
power at the system and facility levels. Thus, the thermal state at
the device and die levels can have a far-reaching influence all the
way up to the data center cooling requirements and environmental impact. In addition, if the required cooling cannot be delivered
to keep the hottest region of a die under its stated temperature
threshold the performance may be throttled down to reduce
power. This unwanted reduction in performance is viewed as a
last resort to be avoided if at all possible. Hence, there is a great
desire to have enhanced, efficient heat spreading capabilities at
both the ‘local’ single transistor device level as well as at the
‘global’ die and packaging levels in order to minimize the severity
and influence of these hot spots.
The effectiveness of a heat spreading material is directly related to
its thermal conductivity. As shown in Fig. 1, the room temperature
thermal conductivity of known bulk materials used in electronics
applications spans from about 3450 W m1 K1 in isotopically purified diamond [14] to on the order of 0.2 W m1 K1 for polymers
FIGURE 1
Representative temperature-dependent thermal conductivity values for
various bulk solids: isotope-enriched diamond [14], boron arsenide [49],
pyrolytic graphite [100], copper [101], crystalline silicon [46], amorphous
silicon dioxide [199], poly(methyl methacrylate) (PMMA) [15], and two types
of polyimide [200].
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such as poly(methyl methacrylate) (PMMA) [15]. In solids, heat may
be transported by atomic lattice vibrations, the energy quantum of
which is known as a phonon, as well as by charge carriers such as
electrons and holes. For insulators and semiconductors the thermal
conductivity is dominated by the contribution from phonons,
while in metals the electronic contribution greatly outweighs the
lattice component. The lattice thermal conductivity, kL, can be
obtained from
X
kL ¼
Cl vl ll
(1)
l
where Cl is the volumetric specific heat contribution from a
phonon mode, vl is the phonon group velocity component along
the temperature gradient direction, and ll is the mean free path
component along the temperature gradient direction of phonons
due to scattering with other phonons, defects, and grain boundaries. The summation is over all phonon modes l = k, i with
wavevector k and polarization i. A similar expression can be used
to calculate the thermal conductivity contribution from electrons
that dominate the thermal conductivity in metals. When the film
thickness, line or channel width, or grain size of thin-film and
nanostructured materials in electronic devices is reduced to be
comparable to or smaller than the intrinsic mean free path of
the dominant heat carriers in the corresponding bulk materials,
enhanced boundary scattering reduces the thermal conductivity to
be significantly lower than the bulk value [16–18]. This thermal
conductivity suppression becomes more pronounced as the characteristic dimension decreases, which in turn may exacerbate the
formation and severity of hot spots in electronics with sufficiently
small feature sizes. The reduction in thermal conductivity with
decreasing characteristic dimension is evident for the silicon (Si)
material data plotted in Fig. 2.
In addition to reductions in feature size, another important
trend lies in the increasing number of interconnect layers [19] with
FIGURE 2
Room-temperature thermal conductivity of Si nanowires and thin films (inplane) as a function of characteristic size compared to bulk values. The
indicated black and gray dashed lines represent the Casimir limit for Si
nanowires calculated for boron doping concentrations of 1 1013 and
1 1019 cm3, respectively [201].
Materials Today Volume 17, Number 4 May 2014
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the number of metal layers identified in the International Technology Roadmap for Semiconductors (ITRS) microprocessor interconnect technology requirements progressively increasing from
seven in 2001 [20] to thirteen for 2014. This introduces a higher
density of interfaces and boundaries within the die structure, each
of which can act as a thermal impedance to heat flow [16,18].
Similarly, at the device level the move from traditional planar
metal–oxide semiconductor field-effect transistors (MOSFETs)
(Fig. 3a) to 3D FinFET/multigate designs [2] (Fig. 3b) and vertical
nanowire wrap-gated devices [21–23] (Fig. 3c) represents a shift
toward more complex device geometries and interface configurations.
Electronics packaging is becoming more intricate and thermally
challenging as well. For example, in the traditional single die flip
chip package schematic illustrated in Fig. 4a, the Si die is attached
to the heat sink or cold plate via a thermal interface material (TIM).
Additional TIM layers may be used if the package includes a lid
situated between the die and the heat sink solution, in which case
FIGURE 4
Illustrations of representative (a) single die flip chip package and (b) 3D chip stack lidless modules with select conceptual heat flow paths shown. For
modules with a lid between the topmost die and the package-level thermal solution (heat sink, cold plate, and so on) an additional thermal interface
material (TIM) is required. Detail in (b) provided courtesy of International Business Machines Corporation. Unauthorized use not permitted. Details include
front-end-of-line (FEOL) and back-end-of-line (BEOL) device and interconnect layers as well as controlled collapse chip connections (C4) and smaller m-C4
features.
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FIGURE 3
(a) A traditional MOSFET design built on SOI wafer with 2D, top-gated planar channel. The associated buried oxide (BOX) layer is also noted. (b) Recently
utilized 3D FinFET/multigate design. (c) Cross-section illustration of a vertical nanowire device with wrap-around gate. In this image, the term ‘high-k
dielectric’ refers to a material with high dielectric constant (k) rather than high thermal conductivity (k).
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the TIM between the die and the lid is typically referred to as TIM1
while the additional TIM between the top of the lid and the heat
sink solution is known as TIM2. TIMs are typically compliant
greases, gels, metallic solders or foils, or phase change materials
(PCMs) that work to compensate for the roughness of the interfacing surfaces by filling in the non-contacting areas that would
otherwise be occupied by poorly conducting air gaps. Besides these
interfaces, additional thermal challenges are introduced at the
package level when separate planar dies are stacked in 3D architectures [3,24,25] as illustrated in Fig. 4b. Here the stacking of
power-dissipating dies on top of one another can induce even
higher power densities than found in single die packages. Further
complications are the additional materials, interfaces, and complex conduction paths that lie between the power-dense regions
and the available thermal management resources, including heat
sinks, cold plates, microchannels, and so on. In many 3D packaging schemes, the individual dies are stacked vertically and connected together using solder bumps or some other type of
interconnect. While these connections are typically metallic materials with high thermal conductivity and can act as a good die-todie thermal linkage, they interface with only a fraction of the total
die area thus limiting their overall transport cross-section while
also not presenting a viable means of spreading heat within the
plane of the die surfaces. In the case of solder bumps or interconnects with non-zero height the remaining interstitial spaces
between the connections may be occupied by an underfill material. This is done to prevent contamination and provide structural
support. The underfill is typically an epoxy-like material with low
intrinsic thermal conductivity (0.1–0.2 W m1 K1) [26,27],
thereby making inefficient use of the available transport crosssection for thermal management. Hence, new underfill materials
or composites with isotropically high thermal conductivity are
needed to provide a means of enhancing cross-plane, die-to-die
thermal transport while simultaneously improving in-plane
spreading of highly localized heat originating from the die faces
as well. It is important to note that thermal challenges have been
identified as a limiting factor for 3D chip stack technology
[3,12,28–30] and are driving significant research and development
efforts into new materials and cooling strategies [29–33] in order to
allow full utilization of the performance potential of 3D integration.
While the power levels associated with mobile and touchscreen
devices are much more modest (typically <10 W for the CPU) than
those found in server or high performance computing hardware,
their dense packaging and limited space for thermal management
components such as fans or heat sinks put a premium on efficient
heat spreading materials and approaches that may function as a part
of product packaging. One such area of opportunity lies in the
transparent touch screens which have become an indispensable
part of smart phones, tablet computers, and other electronics interfaces. Their rising popularity, however, has also resulted in increasing demand for transparent conducting materials. Amongst these
the most well-known is indium tin oxide (ITO) which has historically been the material of choice but is now feeling pressure due to its
lack of flexibility and rising costs [34]. As a result, many researchers
have been investigating the use of carbon nanotubes (CNTs) [35–
37], graphene [38–40], thin Si membranes [41], and silver nanowires
[42–44] on or within various transparent substrate materials as a
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means of realizing alternative, sustainable transparent conducting
materials and displays [34]. Although these materials are opaque in
their bulk form, as nanostructures they may appear transparent
depending on size and loading. While circuit elements composed of
these or similar nanomaterials may have amenable thermal and
optical properties, many of the transparent substrate materials upon
which they are supported do not. Amorphous glasses and oxides
typically have room temperature thermal conductivity of around
1–2 W m1 K1, compared to traditional electronics substrates such
as crystalline Si at 120–150 W m1 K1. This low substrate thermal
conductivity greatly limits heat spreading. Moreover, a potentially
severe challenge is faced in the rising field of flexible electronics.
Here the circuit elements are built upon flexible polymer substrates
such as polyimide (PI) as in Fig. 5a, polydimethylsiloxane (PDMS),
polyetheretherketone (PEEK), polyetherimide (PEI), polyethylene
terephthalate (PET), or other similar materials. Kapton is another
material name commonly found in flexible electronics literature,
but is in fact a trademarked brand name for a family of commercial
polyimide materials of which type-HN is the most widely used. Like
many polymers, the materials mentioned above have very low
thermal conductivity in the 0.1–0.3 W m1 K1 range. As a result,
although the power levels associated with these types of devices are
much smaller than those found in high performance computing the
low conductivity of the substrate material could cause thermal
management issues or device damage [45] as shown in Fig. 5c to
occur at much lower powers than would occur in other applications.
The use of a high thermal conductivity ultrathin material such as hBN for the gate dielectric is illustrated in Fig. 5d.
The above discussion highlights the importance of power dissipation, materials, and structure in determining the thermal
characteristics and challenges associated with electronic devices.
While each of these areas is worthy of detailed examination, this
article focuses on the thermal properties of emerging materials
that might prove promising in improving the thermal management characteristics of next generation electronics. The materials
discussed include cubic crystals, two-dimensional (2D) layered
materials, nanostructure networks and composites, molecular
layers and surface functionalization, and aligned polymer structures. Specifically, the discussion is focused on the potential
benefits and limitations of utilizing these materials as active
channel layers with enhanced heat spreading capability, heat
spreading layers in close proximity to the channel layer, high
thermal conductivity rigid or flexible substrates, TIMs with superior performance characteristics, and novel underfill materials for
use in thermal management of 3D chip stacks.
High thermal conductivity cubic crystals
Certain cubic crystals are known to possess the high, isotropic
thermal conductivity that is desirable for heat spreading application. For example, with its diamond lattice structure the Si used for
substrates in most modern electronic devices is considered a
relatively good thermal conductor with a room temperature thermal conductivity of about 140 W m1 K1 [46,47]. This pales in
comparison, however, to diamond which holds the record for high
thermal conductivity among known bulk solids with reported
values of 2270 and 3450 W m1 K1 at room temperature for
natural diamond and isotopically enriched 99.9% 12C diamond,
respectively [14]. At a temperature of 104 K, the value of
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Materials Today Volume 17, Number 4 May 2014
FIGURE 5
(a) 3D cross-sectional illustration of a flexible electronic device fabricated on polyimide (PI) with graphene channel and atomic layer deposited (ALD) Al2O3 gate
dielectric, source (S) and drain (D) metallic contacts, and buried metal gate as shown. (b) Top-down view of a flexible graphene field effect transistor (GFET)
fabricated on PI that uses a 10 nm ALD Al2O3 gate dielectric. (c) Same device as in (b) after sustaining thermal damage operating at higher drain field. Scale
bars in the lower left images of (b) and (c) are both 3 mm. (d) 3D cross-sectional illustration of a similar GFET to in (a) but with the ALD Al2O3 replaced with a
potentially thermally advantageous h-BN gate dielectric. Images provided courtesy of the Deji Akinwande group, University of Texas at Austin [202].
41 000 W m1 K1 reported for 99.9% 12C diamond has remained
the highest experimental thermal conductivity ever reported for
any solid, as shown in Fig. 1. An even higher peak value of nearly
60 000 W m1 K1 has been predicted for 99.9% 12C diamond at
about 75 K, but this value was beyond the capability of the thermal
wave mirage technique used in the measurement due to a rapidly
decreasing signal to noise ratio with increasing thermal conductivity [14]. Such superior thermal transport performance has
motivated the synthesis and integration of diamond thin films
and substrates into high power density electronic devices to
mitigate local hot spots and enhance the device performance
and reliability. However, natural diamond is scarce and expensive
while further research is needed to improve the growth rate,
enhance the crystal quality, and reduce the cost of synthetic
diamond [48].
Recently, Lindsey, Broido, and Reinecke employed first-principles calculations to predict that cubic boron arsenide (BAs) may
exhibit remarkably high thermal conductivity exceeding
2000 W m1 K1 at room temperature (Fig. 1) [49]. The surprising
theoretical result is related to the large atomic mass difference
between the two constituent elements. Such difference results in a
large energy gap between acoustic phonon branches and optical
phonons branches. This feature drastically reduces the scattering
between propagating acoustic phonons with high group velocities
and high-frequency localized optical phonons of low group velocities. In addition, there exists only one isotope of arsenic atoms,
which dominates the atomic motion of relatively short wavelength phonons that make a large contribution to the BAs thermal
conductivity. Consequently, the BAs thermal conductivity
becomes insensitive to the isotopic impurities of the lighter boron
atoms. Together these features considerably reduce the scattering
rate and result in long mean free paths for the acoustic phonons in
BAs important to thermal transport. It is interesting to note that
these mechanisms associated with the predicted high conductivity
of BAs are different from the commonly accepted criteria for
observing high thermal conductivity in a solid such as diamond
or cubic boron nitride (c-BN). These include simple crystal structure, low atomic mass, strong atomic bonding, and low anharmonicity in the interatomic potentials.
Besides c-BN, other cubic nitride crystals such as aluminum
nitride (AlN) and gallium nitride (GaN) possess relatively high
room-temperature thermal conductivity in the 200–
400 W m1 K1 range depending on purity and defects [50,51].
These values are several times higher than Si and other III–V
compound semiconductors [52]. Because of the high thermal
conductivity and desirable electronic properties, both AlN and
GaN have received increased attention for use in light-emitting
diodes, optoelectronics, high-power switches, dielectric layers,
and as thermally conducting substrates for electronic devices.
Moreover, compared to the amorphous glasses and polymers
currently used as substrates or backplanes for transparent or flexible electronics, cubic AlN and GaN provide two to three orders of
magnitude higher thermal conductivities and can be transparent if
produced with few impurities or defects [53–55]. Stringent crystal
quality is required to achieve the highest thermal conductivity
values reported in literature [50,51,55–57], though sintered AlN
composites have been reported with thermal conductivity greater
than 100 W m1 K1 [58,59] and have been successfully used in
high-power electronics packaging since the mid-1980s [56,60]. In
addition, Wieg et al. [61] reported translucent samples of sintered
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polycrystalline terbium-doped AlN with k = 94 W m1 K1 at
room temperature. A requirement of high quality to achieve both
transparency and high thermal conductivity would seemingly put
bulk nitrides currently out of reach as a viable material for transparent electronics as high quality crystals are typically difficult to
achieve in large sizes or quantities. The cost associated with such
production is another concern compared to currently used materials. Thus, a low-cost, scalable mean of producing transparent
materials with even a passable thermal conductivity in the tens of
W m1 K1 would likely generate interest for use in transparent
electronics as an improvement over current state-of-the-art.
It should also be noted that the long phonon mean free path in
these cubic crystals can give rise to strong size effects on the
thermal conductivity. The mean free paths of those phonons that
make important contribution to the bulk thermal conductivity
span a large range from the nanometer to the micrometer scale, as
shown in the calculated [62–66] and measured [67] thermal conductivity accumulation function of Fig. 6a for bulk Si. Consequently, even characteristic feature sizes on the micron level
can result in suppression of the thermal conductivity in Si thin
films and nanowires, as shown in the Si data of Fig. 2. Besides Si
[17,68–74], size-dependent thermal conductivity reduction has
been observed experimentally in other electronics materials
including compound semiconductors [75,76] and copper [77]
among others. For thin films or nanostructures made from diamond, graphite, BN, or BAs, which possess even higher bulk
thermal conductivities and longer phonon mean free paths than
Si, the onset of thermal conductivity suppression would be
expected to occur at even larger feature sizes.
Many of the measurement results showing conductivity suppression with decreasing size can be explained with theories of
diffuse surface scattering of heat carriers established several decades ago by Casimir [78], Ziman [79], and others. In the case of a
circular rod the Casimir limit for diffuse surface scattering yields an
average boundary scattering mean free path equal to the rod
diameter. Some recent thermal measurements on rough Si nanowires have yielded thermal conductivity values well below the
Casimir limit [80–82], as indicated in Fig. 2. When the characteristic dimension is reduced further to be comparable to the wavelength of phonons that dominate the thermal conductivity, as
plotted in Fig. 6b for Si, additional size effects affecting phonon
velocities, specific heat, and phonon-phonon scattering can come
into play. However, the diameters of the measured rough Si
nanowires are still relatively large compared to the wavelength
of phonons that dominate the thermal conductivity at room
temperature so that the phonon group velocity and spectral
specific heat are not expected to be altered considerably from
the bulk values. Hence, it remains to be better understood whether
the abnormally low thermal conductivity was influenced by interior defects or microstructural changes [82,83], interference
between phonons scattered by multiple points on the surface
roughness [81,84], or other effects. A clear understanding of the
actual origin of the observed abnormally low thermal conductivity
of the Si nanostructures is necessary for reestablishing the adequate theoretical capability for predicting the thermal conductivity of nanostructures of other high thermal conductivity cubic
crystals where experimental data on the size dependent thermal
conductivity is still lacking.
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FIGURE 6
(a) Normalized accumulated contribution to the thermal conductivity of
bulk Si versus phonon mean free path near room temperature. (b)
Normalized accumulated contribution to the thermal conductivity of bulk Si
versus phonon wavelength near room temperature. Data taken from Dames
et al. [62,63], Henry and Chen [64], Esfarjani et al. [65], Li et al. [66], and
Regner et al. [67]. The nanowire (NW) data in (b) is based on the
assumption that all phonons are scattered by the nanowire surface
diffusely.
Two-dimensional (2D) layered materials with
anisotropic thermal conductivities
The unique transport properties associated with 2D materials such
as atomically thin films have made them a focus area of theoretical
and experimental research into next generation electronics for
well over a decade. More recently, the isolation and identification
of single-layer graphene (SLG) and few-layer graphene (FLG) has
produced an explosion of research [85–90] into their physical
properties, synthesis and processing methods, and evaluations
of their performance in electronic devices [39,91–93], sensors
[94–96], and composites [97–99]. Besides electrical transport and
device performance characteristics, thermal transport within graphene in various technologically relevant forms has also been an
area of intense research in part due to the high basal plane thermal
conductivity of 1500–2000 W m1 K1 at room temperature
reported for pyrolytic graphite [100–103], the relatively abundant
3D carbon allotrope made up of stacked graphene sheets. Measurements on suspended SLG have produced thermal conductivity
values near room temperature of 1500–4600 W m1 K1 [104–
106]. Most of the higher values in this range were obtained based
on micro-Raman spectroscopy methods, which are subject to large
uncertainties in the optical absorption and poor temperature
sensitivity. Nevertheless, elimination of inter-layer phonon scattering in suspended graphene is expected to result in a higher basal
plane thermal conductivity for graphene than graphite [107] as
well as a trend of increasing thermal conductivity with decreasing
layer thickness for FLG thinner than about five layers [106,108].
Besides more accurate measurement results of graphene thermal
conductivity, it remains to be better understood whether the high
basal plane thermal conductivity in suspended graphene and even
in graphite consists of a large contribution from the out-of-plane
polarized, in-plane propagating flexural phonons (ZA modes)
[107,108].
Despite the high thermal conductivity of suspended SLG and
FLG, the small cross section of SLG and FLG for in-plane transport
limits the thermal conductance of these materials. Encompassing
the thermal conductivity of a body and its geometry, it is the
thermal conductance that dictates the amount of heat a structure
can transport for a given temperature difference. For use as a heat
spreading layer in electronic devices [109], the thickness or number of layers may need to be increased to obtain sufficient thermal
conductance for effective heat spreading in some applications. On
the other hand, for using multi-layer graphene (MLG) as a nanofiller to enhance the thermal conductivity of a composite where
the nanofiller volume fraction can be constrained by other requirements such as the mechanical compliance, the effective medium
theory [110] can be used to show that it is desirable to increase the
surface-to-volume ratio by decreasing the MLG layer thickness so
long as the thermal conductivity is not reduced with decreasing
thickness.
In many applications, graphene is supported on or embedded in a
medium rather than freely suspended. The impact of the supporting
medium on thermal transport must be understood in order to be
able to design for and achieve the optimum performance. Recent
measurements have found that the thermal conductivity of SLG on
SiO2 is suppressed to 600 W m1 K1 near room temperature,
higher than bulk Cu but much lower than that reported for suspended and clean graphene [111]. The suppression is attributed to
the scattering of phonons – especially the ZA phonons – by the SLGoxide interface. Based on this experimental data, the average phonon mean free path in supported SLG at room temperature was
estimated to be 90–100 nm, much smaller than the 300–600 nm
mean free path estimate for suspended SLG [91,112]. Oxide encasement [113] and polymer residue [114] have also been shown to
significantly suppress thermal transport in SLG and FLG. For both
oxide-encased [113] as well as oxide-supported graphene [115], it
has been shown that the thermal conductivity increases with the
number of layers to approach graphite values. This trend is attributed to the decreasing influence of interface scattering with increasing layer thickness of the encased or supported multi-layer graphene
(MLG). Because of long intrinsic phonon mean free paths in graphite, even along the cross-plane direction phonons in MLG as thick
as 34 layers can reach the interface with an amorphous support
before being scattered [115]. Consequently, it takes more than 30
layers for the thermal conductivity of MLG supported on SiO2 to
recover the basal plane thermal conductivity of graphite [115].
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Besides substrate effects, scattering at patterned edges of supported graphene nanoribbons can result in additional reduction of
the thermal conductivity [112]. The thermal conductivity of patterned SLG nanoribbons 260 nm in length was reduced with
decreasing ribbon width from 230 W m1 K1 at 130 nm to
80 W m1 K1 at 45 nm near 300 K due to phonon scattering with
edge disorder, while the thermal conductance increased with
decreasing length to approach the limit of ballistic phonon transport [112].
Recently, greatly improved electron mobility values have been
achieved in graphene supported on atomically flat hexagonalboron nitride (h-BN) compared to graphene supported on amorphous oxide [116]. The basal plane thermal conductivity of fewlayer h-BN contaminated with polymer residue has been found to
increase with layer thickness [117], similar to the trend revealed by
supported FLG [115] and opposite to that reported for suspended
FLG [106]. Because the phonon mean free path in h-BN is somewhat shorter than those in graphite, the basal plane thermal
conductivity of 11-layer contaminated h-BN sample already
reaches 380 W m1 K1 near 300 K and is close to the reported
bulk basal plane values. The thermal conductivity is suppressed to
about 250 W m1 K1 when the layer thickness is reduced to about
5 layers [117]. In comparison, the cross-plane (parallel to c-axis)
thermal conductivity of h-BN is around 1.5–2.5 W m1 K1 at
300 K [118]. The basal plane thermal conductivity values given
above for h-BN are two orders of magnitude higher than that of the
amorphous buried oxide layer currently used in silicon-on-insulator (SOI) devices. Hence, if h-BN, which is a dielectric, can be
used to replace the buried oxide for either silicon-based or graphene-based devices it could greatly enhance lateral heat spreading and reduce the occurrence or severity of hot spots. Moreover,
the atomically flat interface and similar 2D crystal structures
between graphene and h-BN in the heterostructure can potentially
give rise to distinct in-plane and cross-plane phonon transport
behaviors compared to graphene supported on an amorphous
substrate. Despite the device-level thermal management potential
of graphene/h-BN heterostructures, the transport properties of this
system remain to be studied.
In addition to h-BN and graphene, which have large and vanishingly small band gaps, respectively, silicene [119–123], germanane
[123,124], MoSe2 [123], MoS2 [125], and other 2D layered materials
[123] with different band gap values have received increasing
interest for device applications. Their device performance may
depend in part on their thermal transport properties, which are
expected to deviate from the bulk behaviors but have not yet been
investigated.
Although the basal-plane thermal conductivity of 2D layered
materials can be exceptionally high, the cross-plane value can be
more than an order of magnitude lower. For example, the crossplane thermal conductivity of graphite is about 6 W m1 K1
[100], over 300 times lower than the 2000 W1 m1 K1 in-plane
value found for high-quality graphite. The cross-plane thermal
conductivity of disordered layered WSe2 thin films has been
reported to be as low as 0.05 W m1 K1 [126], which is only about
twice of that of air and is a factor of 30 lower than the measured inplane values [127]. The highly anisotropic thermal conductivity is
associated with the anisotropic phonon dispersion in these 2D
materials that consists of weak van der Waals bonding between
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layers. In particular, the phonon group velocity has a much larger
basal-plane component than the cross-plane or c-axis component.
Together with the high basal plane thermal conductivity, the low
cross-plane thermal conductivity of a lateral heat spreader based
on a 2D layer such as h-BN may be used to reduce the local
substrate temperature right beneath a hot spot. For the case of
flexible devices on a low thermal conductivity, low glass transition
temperature polymer substrate, this feature may actually be
employed to prevent the local melting of the substrate directly
underneath a region of high power density.
The interface thermal resistance that exists between a 2D layered
material and its supporting material is another limiting factor for
vertical heat spreading from the 2D material into the substrate. This
can even dominate the cross-plane thermal resistance when the
thickness of the 2D stack is reduced to be comparable to the crossplane phonon mean free path, which is estimated to be more than
10 nm for graphite [115,128]. There have been measurement
results of the thermal interface thermal resistance between SLG
and different materials including silica and metal. The measurement values are in the range of 1.2 108–4 108 m2 K W1
[93,129–131], comparable to or somewhat higher than the reported
thermal resistances for various metal–dielectric interfaces
[132,133]. When the graphene layer thickness increases, the FLG
can become stiff and less conformal to the surface roughness as
evident from the reduced interface adhesion energy measured in
FLG and SLG [134]. Interface thermal transport across the 2D
materials is intimately connected to the interface adhesion, which
is a critical issue to be addressed in the integration of different 2D
layered materials on a substrate for the fabrication of novel electronic device [91]. However, the reported thermal interface conductance between FLG and silica does not exhibit a clear
dependence on the layer thickness [129,130]. Currently, there is
still a lack of detailed understanding of mechanisms for coupling
between phonons in 2D graphene and the surface and bulk phonon
modes in the substrate. This is a critical aspect of thermal transport
in supported 2D materials that must be understood.
Thermally conducting nanostructure networks and
composites
There has been a number of efforts exploring nanoparticles [135–
138], nanowires [136,139], nanotubes [99,140–142], nanoplatelets
[98,99,143], and 2D layers [141,144] for enhancing the thermal
performance of TIMs as well as polymeric materials to be used as
underfills in 3D chip stacks or flexible electronic substrates. The
high thermal conductivity reported for suspended carbon nanotubes (CNTs) [145,146] in particular have motivated the investigation of vertical CNT arrays as compliant TIMs [140,142,147–149].
However, there are considerable challenges in employing vertical
CNT arrays as TIMs, including low filling fraction and a small
percentage of CNTs contacting both mating surfaces, both of
which may be overcome with engineering innovation. For example, a recent work has reported a ninefold improvement in the
thermal interface conductance after a vertical CNT TIM array was
modified with pyrenylpropyl phosphonic acid [150]. Other challenges include a fundamental issue of possible thermal conductivity suppression by inter-tube phonon scattering within the CNT
arrays [140,142,147]. Alternatively, arrays of copper nanosprings
were recently developed as a mechanically compliant TIM [151].
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Materials Today Volume 17, Number 4 May 2014
Compared to CNT arrays, the thermal conductivity of the individual copper nanosprings is expected to be relatively insensitive to
surface scattering because of a short mean free path of electrons
that dominate the copper thermal conductivity.
Compared to vertical CNT or metal nanowire arrays, creating
polymeric nanocomposite TIM materials by loading a matrix with
high thermal conductivity microfillers and nanofillers is a common approach that can be readily accepted for practical use. Such
polymeric nanocomposites could also conceivably be employed as
substrates for flexible electronics or the underfill layers in 3D
packaging. Fundamentally, the goal of these composites is to
greatly enhance the effective thermal conductivity keff of the
resulting composite material compared to that of its neat matrix,
km. For spherical particles with thermal conductivity kp in a matrix
and interfacial thermal resistance neglected, keff can be calculated
via the Maxwell–Garnett expression:
ke f f
k p þ 2km 2fðkm k p Þ
¼
k p þ 2km þ fðkm k p Þ
km
(2)
where f is the volume fraction of particles [152]. Other more
complex expressions for non-spherical inclusions and which
account for interfacial thermal resistance are also available
[110,153].
Microfiller and nanofillers investigated have included alumina
[26,154], silica [26,154,155], boron nitride [26,27,154,156,157],
aluminum nitride [158], silicon carbide [159], graphite [154], diamond [26,154,156], graphene nanoplatelets [99,157], carbon nanotubes [99,159,160], carbon fibers [155], and few-layer materials
[97,144,161]. A number of studies have reported large increases
in thermal conductivity for composites at high loading over that of
the neat matrix material. However, given the low thermal conductivity of the neat matrix the effective thermal conductivity is still
often less than 10 W m1 K1 [162] and more commonly in the
0.5–2.0 W m1 K1 range even with heavy loading [26,158,160].
Among the few exceptions, a thermal conductivity value of
32.5 W m1 K1 was reported for 78.5 vol.% boron nitride-loaded
polybenzoxazine [163]. A number of studies have pointed out that
the levels of improvement may be limited by the high thermal
interface resistance [164,165] for nanofillers such as CNTs, graphene
platelets, and metal nanostructures, which often form van der Waals
bonded networks after the loading is increased beyond the percolation threshold. Other factors include agglomeration, structural
deformation, defects, and support or medium interaction
[111,114,165] of the fillers.
One challenge for these particle-laden materials is that while the
thermal conductivity increases with increased filler content, the
rheological properties of the composite change as well [26,166],
with the viscosity rising sharply for high loading values. This is
important because many underfills are dispensed in a liquid form
along the periphery of attached die, with capillary forces relied on to
pull the material into the spaces between solder balls [26]. The
limitations associated with high filler loading and capillary integration strategies have been addressed in recent works [154,156,166], in
which densely packed thermally percolating composites were
formed in cavities similar to the C4 solder ball layer(s) of a flip chip
or 3D package (Fig. 7). This was accomplished by using a centrifugal
force method to first introduce microparticles into the cavity
followed by the dispensing, solvent evaporation, and sintering of
FIGURE 7
(a) Left: Illustration of the apparatus used for centrifugal incorporation of
microparticles into cavity space. Right: Microscopic image through top glass
of a 35 mm-high cavity with representative C4 solder ball pattern (large
circles) and spherical silica percolating thermal matrix. Both images
reproduced with permission from Ref. [166]. (b) SEM image of the spherical
microparticle/nanoparticle percolation network formed in a cavity. (c) SEM
detail of the neck structure formed by the annealed silver nanoparticles
between adjacent silica microparticles. Images in (b) and (c) reproduced
with permission from Ref. [154].
RESEARCH
like BN or AlN. In principle the solid struts of the foam material are
similar to the microparticle/nanoparticle networks [154,156,166]
discussed above but as a single, inherently connected structure
without particle–particle interfaces. Thus, in contrast to composites with randomly dispersed filler structures where high thermal
resistance at van der Waals interfaces has limited the effective
thermal conductivity of the composites, 3D porous matrices do
not require a high loading of filler material to reach a percolation
threshold and thermal interface resistance is minimized within the
covalently bonded networks. These types of 3D matrices also offer
the ability to enhance in-plane heat spreading as well as die-to-die
thermal transfer especially if the pores are able to be impregnated
with a secondary component such as a phase change material
[167], thermal grease, or even standard underfill epoxy. This
isotropic conduction characteristic is also an advantage compared
to highly anisotropic materials such as those composed of aligned
nanotubes or nanofibers. The effective thermal conductivity of
unimpregnated ultrathin graphite foams (UGFs) has been measured to be 0.27–3.44 W m1 K1 depending on processing methods, with the extracted conductivity of the ultrathin graphite
struts themselves in the 500–1000 W m1 K1 [167,168] range.
Similar to UGFs concerning a carbon-based 3D porous architecture, CNT networks [169] or CNT struts serving as links between
aligned graphene sheets have been proposed [91,170]. However,
for any of these materials to find wide-spread use significant
integration challenges would need to be addressed such that
the 3D matrix does not interfere with interconnects either physically or electrically. Thus, 3D porous materials that have high
thermal conductivity but are electrical insulators such as h-BN
foams [171] would likely be more desirable than those made of
metal or graphite. Moreover, the thermal conductivity of existing
ultrathin h-BN and graphite foams is still limited to be less than
10 W m1 K1 by the low density, which is in turn limited by the
large pore size on the order of 500 mm. Although high-density
carbon foams exist, they usually have a similarly large pore size
and strut wall thickness on the order of hundreds of nanometers or
thicker. For a given density, a smaller pore size of the foam fillers is
more desirable than a thicker wall for the use of the foam as fillers
in a PCM for thermal management [172]. Hence, there is a need to
establish new manufacturing methods that can be used to control
the pore size and wall thickness of the foam structures.
Organic materials with enhanced thermal performance
a silver nanoparticle-loaded suspension, with epoxy backfilling via
capillary or pressurized introduction as a final step [154,166]. The
structure of the composite is made up of microparticles linked by
sintered silver nanoparticle ‘necks’ to enhance thermal connectivity
all within an epoxy matrix [154,166]. The measured effective thermal conductivity of the composites realized in this way without the
nanoparticle-enhanced contacts were in the range of 1.7–
2.5 0.1 W m1 K1 and were reported to be a factor of two better
than commercial state-of-the-art thermally conductive underfills
for the same package conditions [156]. With the silver nanoparticles
necks in place the thermal conductivity increased further to
3.8 0.3 W m1 K1 [154,166].
Another promising area lies in 3D porous foams of high thermal
conductivity materials like metals, graphite, or certain dielectrics
Besides filler-loaded polymeric nanocomposites, a more fundamental approach to improving heat spreading in polymers focuses
on the causes of poor thermal conduction. The low thermal
conductivity of amorphous materials stems from the lack of
ordering at the atomic scale. Thus, if a given glass or polymer
were to be synthesized in an ordered, crystalline or even quasicrystalline form with few defects the thermal conductivity could
potentially see significant improvement. For example, extrusion,
gel-spinning, or melt drawing can help to align crystallite regions
within a polymer [173–180] with significant gains in mechanical
properties and thermal conduction in the aligned direction. In one
study, polyethylene and polybenzobisoxazole fibers were reported
to have thermal conductivities of between 55 W m1 K1 and
60 W m1 K1 near room temperature [180]. At the highest draw
ratios, thermal conductivity values of 75–125 W m1 K1 were
171
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Materials Today Volume 17, Number 4 May 2014
RESEARCH
RESEARCH: Review
reported for polyethylene nanofibers [181]. A recent time domain
thermal reflectance (TDTR) measurement of microfibers of various
polymer materials have obtained room-temperature thermal conductivity values of 20 W m1 K1, [182] which is lower than the
earlier thermal conductivity measurement results of similar samples [180]. However, the TDTR measurements reveal decreasing
thermal conductivity with increasing temperature, which is an
indication that the thermal conductivity has reached the intrinsic
limit dictated by anharmonicity instead of defect or boundary
scattering. Based on these findings, it has been speculated that
some earlier microfiber measurement results could contain errors
due to radiation loss [182]. Although the existing results are
already remarkable and potentially useful for transparent or flexible electronics, further work is needed to investigate the limit in
enhancing the thermal conductivity and mechanical properties of
polymers via enhanced chain alignment and other approaches.
Organic materials have also been investigated for enhancing
interface thermal conductance. Although voids are not typically
present at the interface between deposited thin films, such interfaces are still subjected to thermal interface resistance that
depends on the bonding strength, interface atomic mixing and
roughness, and mismatch of acoustic impedances that are proportional to the density and phonon group velocity of the materials in
contact. There have been a number of studies of interface thermal
transport by both phonons and electrons [183–189]. Besides the
role of electron–phonon coupling and the effect of structure
anisotropy [190–192], new experimental studies of thermal transport through single molecules [193,194], organic–inorganic nanocrystal arrays [195], and molecular monolayers [196,197] have
been reported. In one recent work [197], a strongly bonding
organic nanomolecular layer (NML) was used as an intermediary
within an otherwise weakly bonded Cu/SiO2 interface with a
fourfold increase in the measured interfacial thermal conductance, that is, from 90 15 MW m2 K1 to 430 + 230/
70 MW m2 K1. Additional data from other material interfaces
and NMLs reveal that the interfacial thermal conductance
increases with stronger interfacial toughness. Oxygen functionalization has also been found to enhance the interface thermal
conductance between graphene encased between aluminum and
SiO2 [198], although it is possible that the basal plane electronic
and thermal properties of graphene can be negatively impacted by
the oxygen plasma treatment. These findings suggest a potential
new approach of choosing process-compatible NMLs or other
organic compounds to enhance interfacial bonding and reduce
thermal interface resistances at some of the physical interfaces
present in electronics.
Conclusions and outlook
The majority of this discussion focused on the thermal conductivity of 3D cubic crystals, 2D layered materials, nanostructure
networks and composites, aligned polymer fibers, and molecular
layers as well as the property dependence on structure, size
scaling, physical state, or environment. The respective potential
of each material class for enhanced electronics thermal management was discussed. However, to make the leap from the lab
bench and into wide-spread use, these new materials must offer a
closed-form solution for the electronics device or package. An
indicative example of this need would be the incorporation of a
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Materials Today Volume 17, Number 4 May 2014
3D metal foam structure into a functioning 3D chip stack, which
may work well for thermal management but also may cause
shorting or wreak havoc on signal integrity. Other important
considerations for true viability include cost, scalable manufacturing, repeatability of performance, electrical resistivity,
dielectric constant, and coefficient of thermal expansion, just
to name a few. Obviously the most direct means in which
materials science researchers can make an impact in this field
is to identify and synthesize materials with the potential for high
thermal conductivity guided by current understanding of thermal transport physics. However, significant contributions can
also be made by developing synthesis or manufacturing methods for existing highly conductive materials to reduce cost,
improve quality, ensure uniformity, and allow for industrial
scale production.
Though the thermal management challenges facing modern
electronics are considerable in both magnitude and scope, a
diverse new set of cutting-edge materials are rising up to meet
them. The works described in this review do not represent incremental improvements on established mainstays but feature many
non-traditional materials or established materials being used in
non-traditional ways, which shows that (a) thermal issues are
pushing scientists and engineers past conventional approaches
and forcing rapid adaptation to critical thermal bottlenecks in
electronics cooling, and (b) that the materials research world is
attacking these challenges in some very creative ways. With a
compelling technological motivation, a set of interrelated but
distinct application areas, and an ever-growing field of tools
and processes, modern materials researchers have an exciting
opportunity to make a meaningful impact on thermal management of electronics.
Acknowledgements
ALM would like to thank IBM as well as Annie Weathers and the
Deji Akinwande group at the University of Texas at Austin for
providing materials and assistance in the preparation of this
review. LS acknowledges funding support from U.S. National
Science Foundation (NSF) Thermal Transport Processes program
(award CBET-1336968) and NSF Nanosystems Engineering
Research Center: Nanomanufacturing Systems for Mobile
Computing and Energy Technologies (award EEC-1160494),
Department of Energy Office of Basic Energy Science (DE-FG0207ER46377), and Office of Naval Research (N00014-14-1-0258).
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