2C
2C
n
2C
2C
p
C
C
C
p
n
C
0.5C 0.5C
n
p
p
n
n
p
C
0.5C 0.5C
C
Vinn
2C
2C
p
n
2C
n
2C
p
C
C
p
n
C
C
n
p
0.5C 0.5C
p
n
n
p
0.5C 0.5C
Vinp
C
C
2C
Sample (NDAC as example):
2C
p
n
2C
C
2C
C
p
n
C
C
n
p
0.5C 0.5C
p
n
n
p
0.5C 0.5C
C
C
Q= (Vin-Vcm)8
Vcm=(Vrefn+Vrefp)/2
Resolve (NDAC up as example):
Q= (Vx-Vcm)4+(Vx-Vbot)4 where: Vbot=(Vcm+Vrefn)/2
Vx=Vin-1/2(Vcm-Vbot)=Vin-1/2(1/2(Vcm-Vrefn))
Compare with Vin-1/2(Vcm-Vrefn) reference attenuate by half
Reference 1
•
[1] V. Hariprasath, J. Guerber, S. -. Lee and U. -. Moon, "Merged capacitor switching based SAR ADC with highest switching energyefficiency," in Electronics Letters, vol. 46, no. 9, pp. 620-621, 29 April 2010, doi: 10.1049/el.2010.0706.
•
[2] Y. Zhu et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6,
pp. 1111-1121, June 2010, doi: 10.1109/JSSC.2010.2048498.
•
[3] H. Tai, Y. Hu, H. Chen and H. Chen, "11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS," 2014
IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 196-197, doi:
10.1109/ISSCC.2014.6757397.
•
[4] P. Lee, J. Lin and C. Hsieh, "A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching,"
in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp. 2149-2157, Dec. 2016, doi:
10.1109/TCSI.2016.2617879.
•
[5] J. Lin and C. Hsieh, "A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS," in IEEE Transactions on
Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 70-79, Jan. 2015, doi: 10.1109/TCSI.2014.2349571.
•
[6] C. Liou and C. Hsieh, "A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm
CMOS," 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, 2013, pp. 280-281,
doi: 10.1109/ISSCC.2013.6487735.
Reference 2
•
[7] S. Hsieh and C. Hsieh, "A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 12, pp. 1171-1175, Dec. 2016, doi:
10.1109/TCSII.2016.2605139.
•
[8] W. Wu et al., "A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS," 2013 IEEE
International Symposium on Circuits and Systems (ISCAS), Beijing, 2013, pp. 2239-2242, doi: 10.1109/ISCAS.2013.6572322.
•
[9] C. Liu, S. Chang, G. Huang and Y. Lin, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process," 2009 Symposium on VLSI
Circuits, Kyoto, Japan, 2009, pp. 236-237.
•
[10] S. Hsieh and C. Hsieh, "A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC," in IEEE Journal of SolidState Circuits, vol. 53, no. 9, pp. 2595-2603, Sept. 2018, doi: 10.1109/JSSC.2018.2847306.
•
[11] C. Liu, S. Chang, G. Huang and Y. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE
Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010, doi: 10.1109/JSSC.2010.2042254.
•
[12] L. Chen, A. Sanyal, J. Ma and N. Sun, "A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique,"
ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC), Venice Lido, 2014, pp. 219-222, doi:
10.1109/ESSCIRC.2014.6942061.
Merged Capacitor Switch [1][2]
 Commenly used
• Sample: top input; bottom Vcm
• Switch: top residue; bottom reference
• High switching energy
• Relaxed matching requirement
Three level switching
Direct switching (DS) [3]
 Applied to Subrange SAR ADC
• Coarse SAR resolve the n-bit
MSB
• Fine DAC switch skip
unnecessary switch to save
switching energy
Additional coarse fine circuits
• Note: coarse switch use split-cap switching
method to keep the common mode voltage
constant comparator dynamic offset does
not affect the linearity.
• Fine switch use monotonic switching
method to save the switching energy
input-range adaptive switching procedure [4]
 Applied to early/late comparator
(two-bit per cycle)
• Save MSB switching comparator result,
(01 in the example, 11 doesn’t apply)
Additional time domain quantizer added
to comparator
• Split cap method modification
Charge-Average switching (CAS) [6]
 Charge-Average switching
• Reduce the switching energy of
the DAC without an extra voltage
reference and common-mode
shift
Reset energy required (reset
to equivalent bottom plate
Vcm)
• Split cap method modification
Merge and split switching (MAS) [5]
 Modified CAS
• Further reduce the
switching energy
Same as CAS
Shifted Monotonic switching (SMS) [7]
 Modified monotonic switching
• Further reduce the switching
energy
Comparator input common
mode voltage not constant
Three level reference needed
Monotonic switching, set and down [9] [11]
 Same as set and down
switching
• Low switching energy
• Two reference needed
Comparator input common
mode voltage not constant
Bidirectional [12]
 Bidirectional
 Similar as
monotionic
Monotonic Multi-Switching (MMS) [8]
 Modified monotonic switching
• Further reduce the switching
energy
Comparator input common
mode voltage not constant
Three level reference needed
Semi-Resting (SR) Switching Method [10]
 Developed for low VDD SAR
ADC
• Double the conversion range
(VDD as Vcm)
• Low switching energy
Comparator input common
mode voltage not constant
Need two DAC