CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS
Chapter Outline
10.1 The Two-Stage CMOS Op Amp
10.2 The Folded-Cascode CMOS Op Amp
10.3 The 741 Op-Amp Circuit
10.4 DC Analysis of the 741
10.5 Small-Signal Analysis of the 741
10.6 Gain, Frequency Response, and Slew Rate of the 741
10.7 Modern Techniques for the Design of BJT Op Amp
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10-1
10.1 The Two-Stage CMOS Op Amp
Multi-stage amplifiers
Practical transistor amplifiers usually consist of a number of stages connected in cascade
Input stage:
 High input resistance to avoid signal loss due to high-resistance source
 Voltage gain
 Large CMRR for differential amplifiers
Middle stages:
 Voltage gain
 Shifting of the dc level for required voltage swing
 Differential to single-ended
single ended conversion if necessary
Output stage:
 Low output resistance to avoid loss of gain due to low-resistance load
 Current supply required by the load
 Sufficient voltage swing required by the load
 Small-signal approximation may not apply
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Circuit Configuration
Most widely used op amp in VLSI circuits
Bias circuit: IREF and Q8
Input stage: Q1-Q5
 Active-loaded MOS differential pair
 Differential input and single-ended output
 Provides voltage gain and high input resistance
Output stage: Q6-Q7
 Active-loaded common-source amplifier
 Provides voltage gain
 High output resistance (not suitable for low-impedance loads)
DC arrangement:
 The bias current of the input differential pair is provided by Q5
 The bias current of the second stage is provided by Q7
 To avoid systematic (predictable) offset:
(W / L) 6
(W / L) 7
2
(W / L) 4
(W / L)5
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Input common-mode range and output swing
The transistors are supposed to be in saturation for proper circuit operation
ICMR:  VSS  VOV 3  Vtn  Vtp  VICM  VDD  Vtp  VOV 1  VOV 5
Output swing:  VSS  VOV 6  vO  VDD  VOV 7
Voltage gain
Low-frequency small-signal gain:
Gm1  g m1  g m 2
R1  ro 2 || ro 4
A1  Gm1 R1   g m1 (ro 2 || ro 4 )
Gm 2  g m 6
R2  ro 6 || ro 7
A2  Gm 2 R2   g m 6 (ro 6 || ro 7 )
Av  A1 A2  g m1 (ro 2 || ro 4 ) g m 6 (ro 6 || ro 7 )
Amplifier prototype:
 Input resistance: Ri  
 Output resistance: Ro  ro 6 || ro 7
 Transconductance: Gm   g m1 (ro 2 || ro 4 ) g m6
Common-mode rejection ratio:
CMRR  g m1 (ro 2 || ro 4 )  2 g m 3 RSS
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Frequency response
Poles and zeros
C1  C gd 2  Cdb 2  C gd 4  Cdb 4  C gs 6
C2  Cdb 6  Cdb 7  C gd 7  C L
f P1 
1
1
2 R1Gm 2 R2CC
fP2 
1 Gm 2
2 C2
f Z1 
1 Gm 2
2 CC
fP2 decreases for a capacitive load
May result in stability issue
Unity-gain frequency for a dominant pole case
1 Gm1
2 CC
G
G
 m1  m 2 and Gm1  Gm 2
CC
C2
f t  Av f P1 
Phase margin
P 2   tan 1 ( f t / f P 2 )
Z   tan 1 ( f t / f Z )
total  90  tan 1 ( f t / f P 2 )  tan 1 ( f t / f Z )
PM  180  total  90  tan 1 ( f t / f P 2 )  tan 1 ( f t / f Z )
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Phase margin improvement technique
 Adding a series resistance in the feedback path
 The zero is defined by
Vi 2
R
1
sC
 Gm 2Vi 2
s
1
 1

CC 
 R 
 Gm 2

 The zero can be moved toward higher frequencies for better phase margin
Slew rate
Slew rate is defined as the maximum voltage change rate at output
Associated with charging/discharging time of CC
Extreme cases:
 Limited by bias current of Q5 (typical case): SR = I/CC
 Limited by bias current of Q7: SR = I7/CC
Relationship between SR and ft
 SR = 2 ftVOV = tVOV
 Slew rate is determined by the overdrive voltage
for a given unity-gain frequency
 PMOS devices are preferred for the differential pair
with a fixed current I at the cost of lower gain
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Power-supply rejection ratio (PSRR)
PSRR is defined as the ratio of the amplifier differential gain to the gain from the supply voltage
PSRR  
Ad vo / vid

A vo / vdd
PSRR  
Ad vo / vid

A vo / vss
Design trade-offs
CMOS two-stage op amp performance is determined by
 The channel length of the MOSFETs
 The overdrive voltage of the MOSFETs
Performance benefit for a larger channel length: gain, CMRR, PSRR
Performance benefit for a smaller overdrive voltage: gain, CMRR, PSRR, ICMR, output swing and offset
Performance benefit for a larger overdrive voltage: high-frequency characteristics (gain)
fT 
1
gm
1 1.5 nVOV

2 C gs  C gd 2
L2
For modern submicron CMOS technologies:
 Typical VOV between 0.1 to 0.3 V
 Channel length is at least 1.5 to 2 times minimum length (Lmin)
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10.2 The Folded-Cascode CMOS Op Amp
Circuit Configuration
Cascode topology to increase the gain of the input differential pair
Folded topology to improve the ICMR and to reduce the required supply voltage
Is generally considered a single-stage amplifier
Also called operational transconductance amplifier (OTA)
DC bias:
 Bias current for Q1-Q2 is I/2
 Bias current for Q3-Q8 is I/2  IB
 IB can be realized by MOS current mirrors
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Input common-mode range and output swing
ICMR:  VSS  VOV 11  VOV 1  Vtn  VICM  VDD  VOV 9  Vtn
Output swing:  VSS  VOV 5  VOV 7  Vtn  vO  VDD  VOV 10  VOV 4
Voltage gain
Gm  g m1  g m 2
Ro  Ro 4 || Ro 6  [ g m 4 ro 4 (ro 2 || ro10 )] || ( g m 6 ro 6 ro8 )
Av  Gm Ro  g m 2 {[ g m 4 ro 4 (ro 2 || ro10 )] || ( g m 6 ro 6 ro8 )}
High voltage gain due to increased output resistance
Not desirable for applications where low output resistance is needed for the op amp
F
Frequency
response
Dominant pole at the output node
Excellent high-frequency response
Vo
Gm Ro

Vid 1  sC L Ro
ft 
1 Gm
2 CL
Slew rate
The slew rate is limited by the bias current I and the load CL
Slew rate SR = I/CL = 2 ftVOV1 for IB > I
Typically IB is set 10% ~ 20% larger than I
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Increasing the ICMR: rail-to-rail input operation
NMOS and PMOS differential pairs in parallel
ICMR exceeds the power supply voltage
Differential output voltage provided
ICM in the middle:
 Both pairs operate simultaneously
 Av = 2GmRo
ICM near supply voltage:
 Only one of the pairs is operational
 Gain drops to half
Increasing the output voltage range: wide-swing current mirror
Modified cascode current mirror
Output swing increased by Vt
Output resistance remains the same
A proper dc bias voltage VBIAS is needed
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The BJT Device
High-frequency hybrid- model:
 The base-charging or diffusion capacitance Cde:
Cde   F g m   F
IC
VT
 The base-emitter junction capacitance Cje:
C je  2C j 0
 The collector-base junction capacitance C:
C 
C 0
 V 
1  CB 
 V0 c 
m
The cutoff (unity-gain) frequency:
I c  ( g m  sC  )V
V  I b (r || C || C ) 
Ib
1 / r  sC  sC 
h fe 
g m  sC 
Ic

I b 1 / r  s (C  C )
h fe 
0
g m r

1  s (C  C )r 1  s (C  C )r
fT 
gm
IC
1
1

2 C  C 2 (C  C )VT
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8.3 The 741 Op-Amp Circuit
741 Op-Amp
Device parameters:
 npn: IS = 10-14 A,  = 200, VA = 125 V
 pnp: IS = 10-14 A,  = 50, VA = 50 V
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Bias circuit:
 Reference current generated by Q11, Q12 and R5
 Bias for input stage: Widlar current source (Q10, Q11 and R4) and current mirror Q8, Q9
 Bias for second stage: current mirror Q12, Q13B (Q13 is a two-output current source)
 Bias for output stage: current mirror Q12, Q13A /Q18-Q19 provides 2VBE drop between VB14 and VB20
Input stage: (Q1-Q7, R1-R3)
 Input emitter follower (Q1-Q2): high input resistance
 Current-mirror load (Q5-Q7, R1-R3):high output resistance and differential to single-ended conversion
 Level shifting (Q3 and Q4): for required voltage swing and dc level at the input of the second stage
Second stage: (Q16-Q
Q17, Q13B, R8-R
R9)
 Emitter follower Q16 for high input resistance
 Common-emitter Q17 for voltage gain
 Miller compensation technique by CC
Output stage: (Q14, Q20)
 Complementary pair Q14 and Q20
 Low output resistance
 Relatively large load current without dissipating a large amount of power
 Emitter follower Q23 to increase input resistance of the output stage
Short-circuit protection circuitry Q15, Q21, Q24, Q22, R6, R7, R11
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10.4 DC Analysis of the 741
Reference bias current
Provided by Q11, Q12 and R5
I REF 
VCC  VEB12  VBE11  (VEE )
R5
IREF = 0.73 mA (for VCC = VEE = 15 V)
Input-stage bias
Widlar current source Q11, Q10 and R4:
I
VT ln REF
 I C10

  I C10 R4

IC10 = 19 A
Current mirror Q8 and Q9:
2I
2I

 I C10
1 2 / P P
IC1 = IC2  IC3 = IC4 = 9.5 A
Q1-Q4 and Q8-Q9 form a negative feedback loop
Bias current can be stabilized by the negative feedback
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Current-source load Q5-Q7 and R1-R3
IC5  IC 6  I
IC7  I E7 
2I
N

VBE 6  IR2 2 I VT ln( I / I S )  IR2


N
R3
R3
IC7 = 10.5 A
Input bias current and offset currents
 Input bias current:
IB 
I B1  I B 2
I

N
2
IB = 47.5 nA
 Input
I
offset
ff current:
I OS  I B1  I B 2
Non-zero input offset due to mismatches in the  value
Input common-mode range:
 Input common-mode voltage over which the input stage remains in the linear active mode
 The upper end limited by saturation of Q1 and Q2
 The lower end limited by saturation of Q3 and Q4
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Second-stage bias
I C17  I C13 B  0.75 I REF
I 
VBE17  VT ln C17 
 IS 
I C16  I E16  I B17 
I E17 R8  VBE17
R9
IC17  IC13B = 550 A
VEB17 = 618 mV and IC16 = 16.2 A
Output-stage bias
DC for Q23:
I C 23  I E 23  0.25I REF
IC23  180 A (IB23  3.6 A negligible for IC17)
DC for Q18-Q19:
I C18  0.25I REF  VBE18 / R10
I 
VBE18  VT ln C18 
 IS 
IC18  165 A and IC19  VBE18/R10 + IB18 = 15.8 A
DC for Q14 and Q20:
VBB = VBE18 + VBE19 = 588 mV + 530 mV = 1.118 V
IC14 = IC20 = 154 A (for IS14 = IS20 = 310-14 A)
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10.5 Small-Signal Analysis of the 741
The input stage
Differential input resistance:
ie  vi /( 4re )
Rid  4(  N  1)re
re = 2.63 k and Rid = 2.1 M
Transconductance:
Gm1 
io 2ie 
1


 g m1
vi
vi
2re 2
Gm1 = 0.19 mA/V
Output resistance:
Ro  ro [1  g m ( Re || r )]
Ro4 = ro4[1 + gm4(re4||r2)] = 10.5 M
Ro6 = ro6[1 + gm6(R2||r6)] = 18.2 M
Ro1 = Ro4||Ro6 = 6.7 M
Equivalent circuit for the input stage:
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The second stage
Input resistance
Ri 2  ( 16  1){re16  [ R9 || ( 17  1)( re17  R8 )]}
Ri2  4 M
Transconductance
ic17 
vb17
re17  R8
vb17  vi 2
Gm 2 
R9 || Ri17
re 6  R9 || Ri17
ic17
R9 || Ri17


vi 2 re17  R8 re 6  R9 || Ri17
Gm2 = 6.5 mA/V
Output resistance
Ro 2  Ro13 B || Ro17  ro13 B || {ro17 [1  g m17 (r 17 || R8 )]}
Ro2 = 81 k
Equivalent circuit for the second stage:
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The output stage
Output voltage limits
vO max  VCC  VCEsat  VBE14
vO min  VEE  VCEsat  VEB 23  VEB 20
 approximately 1 V below VCC and 1.5 V above –VEE
Input resistance (for RL = 2 k, IC20 = 5 mA and IC14 =0)
Ri 20  r 20  (1   20 ) RL   20 RL
Rin 3  r 23  (1   23 )( Ri 20 || ro13 A )   23 ( Ri 20 || ro13 A )
Rin3  3.7 M
Open-circuit
Open
circuit voltage gain
Gvo 3 
vo
vo 2
RL  
1
Transconductance
vi 3  vb 23  ve 23  vb 20
Gm 3 
io
vi 3
RL  0

1
 g m 20
re 20
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Output resistance
Ro 23  re 23 
Ro 2
 23  1
Rout  re 20 
Ro 23 || ro13 A
R
 re 20  o 23
 20  1
 20  1
Rout  34 
Equivalent circuit for the output stage
Output short-circuit protection
 One of the two output transistors could conduct
a large amount of current if output is short-circuited
 Short-circuit protection is adopted in the 741 op amp
 For current source case (IC14 > 20 mA)
VBE15 > 540 mA
Q15 turns on and takes away the base current of Q14
IC14 is limited as the base current is reduced
 Similar case for current sink case (IC20 >20 mA)
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10.6 Gain, Frequency Response and Slew Rate of the 741
Small-signal gain
Av 
RL
vo vi 2 vo 2 vo

 Gm1 ( Ro1 || Ri 2 )(Gm 2 Ro 2 )Gvo 3
vi
vi vi 2 vo 2
RL  Rout
Av = 243147 V/V = 107.7 dB
Frequency response
Cin  CC (1 | A2 |)
Rt  Ro1 || Ri 2
fP 
1 1
2 Cin Rt
f t  A0 f P
fP = 4.1 Hz
ft = 1 MHz
Slew rate
SR 
2I
CC
SR = 0.63 V/s
Relationship between ft and slew rate
SR  4VT t
Slew rate of MOS opamp with same ft is 2~3 times higher than the 741
Gm-reduction method: total bias current is kept constant with reduced Gm1
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