BRUSH UP THE THEORY TO
DESIGN AN HIGH POWER CLASSE AMPLIFIER
Contents
1.
Abstract ........................................................................................................................................................ 2
2.
Idealized Class-E operation .......................................................................................................................... 2
3.
Basic assumptions for Class-E amplifier ....................................................................................................... 4
3.1 Design equations for infinite QL. ................................................................................................................ 4
3.2 Devices electrical stress. ............................................................................................................................ 7
3.3 Design equations for finite QL. ................................................................................................................... 8
3.4 Finite DC-feed inductance........................................................................................................................ 10
4.
Design a 500W Class-E at 13.56MHz ......................................................................................................... 10
4.1 Device selection and circuit simulation ................................................................................................... 10
4.2 Gate driver ............................................................................................................................................... 14
4.3 Prototype and RF performances .............................................................................................................. 14
Conclusion .......................................................................................................................................................... 19
Authors Biography ............................................................................................................................................. 19
References ......................................................................................................................................................... 20
1. Abstract
Among several type of switched-mode PAs Class E is the most promising for RF applications due to
a number of reasons: high efficiency, simplicity of the load network and a satisfying performances
even with non-optimal drive signal.
This article recalls the Class-E theoretical basis initially introduced in the 1970’s by Dr. N.O. Sokal
and A.D. Sokal (1) and the idealized operation mathematically explained by Dr. Raab (2). Afterwards
are discussed the effects caused by the various non-ideal effects present in the circuit (3) and finally is
presented a 500W class-E amplifier designed with two SD4933 by STMicroelectronics in parallel.
For Class-E amplifiers the theory offers useful equations to start a new design, all of them have been
obtained making mathematical assumptions for the voltage at the device's drain and considering
lossless components. Nevertheless when all these hypothesis are gradually removed it's difficult to
obtain closed-form equations and the analysis of the circuit can be done using Electronic Design
Automation Software (EDA).
Keywords
Class E amplifier, high efficiency, power transistor, nonlinear output capacitance, RF power,
switching mode, zero-voltage switching (ZVS)
2. Idealized Class-E operation
The basic form of a Class-E power amplifier is showed in Figure 1. The topology consists of a
transistor, a shunt capacitor C, RF choke L1 and a series L2-C2 resonator followed by the load
resistance R.
2
FIGURE 1- BASIC CLASS E AMPLIFIER
The Class-E amplifier works in switched mode, i.e. the transistor is driven hard enough to saturate in
order to acts as switch with two discrete states ON and OFF.
The circuit operation is determined by the transistor when it is ON and by the transient response of the
load network when the transistor is OFF.
The previous circuit is equivalent to the one shown in Figure 2.
Figure 2 - Equivalent schematic of the Class-E circuit.
In Figure 2 the transistor has been replaced by a switch, the capacitor C1 comprises the external
capacitance C and the transistor’s output capacitance. The series combination L2-C2 is tuned at the
3
frequency of operation
. Moreover the series reactance jX (at the switching frequency fsw) can
model a circuit mistuning or a change of the operating frequency.
3. Basic assumptions for Class-E amplifier
Generally the analysis of the circuit is done with the ideal simplified assumptions:
1. The transistor is an ideal switch, i.e. a short circuit in the ON state and an open circuit in the
OFF state, with an instant switching action.
2. The switch is operated with a 50 % duty cycle, at the switching frequency.
3. The switch can sustain the current running through it in the ON state and also must be able to
stand the non-zero voltage that appears during the OFF state.
4. The RF choke (DC-feeder) has a very large inductance and accordingly allows only DC current
to flow through it.
5. The loaded Q-factor (QL) of the series resonator L2-C2 is high enough so it can be considered
that a purely sinusoidal current is running through the load R.
3.1 Design equations for infinite QL.
Under the above ideal conditions it’s possible to obtain design equations for each components of the
circuits. It’s hypothesized that the circuit has reached a steady-state operation and the RF ON-OFF
cycles are equally divided.
In Figure 3 are displayed the well-known ideal Class E waveforms in the switch plus the shunt current
through the capacitor C1.
From now on, the angular phase is defined as Ө = ω with ω is the operation frequency.
4
Figure 3 – Class E waveforms
Due to the large reactance of the RF choke at the frequency of operation, we can consider that only
DC current IDC flows from the power supply.
Moreover with the assumption of QL=∞ for the series resonator L2-C2 only the fundamental frequency
current can flow through the load.
The current delivered to the load R is:
=
sin
+
Equation 1
Where
denotes the amplitude of the load current and
is the initial phase.
At OFF state the currents flowing through switch and shunt capacitor C1 are:
=0
=
Equation 2
− sin
Equation 3
5
+
The current
is charging / discharging the shunt capacitor C1 (see Figure 2). Since we assume
that during the ON state the voltage across switch/shunt capacitor is equal to zero, the capacitor
voltage in the OFF state can be found as
1
=
Equation 4
If we substitute Equation 3 into Equation 4 and perform the integration in the given boundaries we
will obtain that the capacitor voltage at any instant in the OFF state is given by:
=
1
!
+ cos
+
− cos $
Equation 5
A feature of the Class-E operation that distinguishes this class from the others switching-mode PA
configurations, is the so-called “soft switching”. In other words, the switch closes precisely at the
instant where the shunt capacitor is completely discharged.
Therefore to achieve the soft switching at the drain voltage the output’s network must force at the turn
ON the electrical boundary conditions as initially introduced by Sokal:
=% =0
&
Equation 6
'(
=0
Equation 7
After some calculations each component of the output network can be found by the following
equations:
ωR =
%
8
≅ 0.1836
+4
%+
Equation 8
1
=1
%+ + 4
≈ 1.734 ∙ R
8
Equation 9
5
7
8
7 +
= 56 =
≈ 0.5768 ∙
1 %+ + 4
R
+
Equation 10
PDC and RDC are respectively the power absorbed from the power supply totally delivered to the load
and the resistances DC supply sees. The idealized model already presented in addition with the
boundary conditions (Equation 6 and Equation 7) produces a theoretical power efficiency of 100%.
In the reality the power efficiency will decrease because the ideal assumptions are not met and also
because we must add the power losses of each component.
3.2 Devices electrical stress.
The output capacitance C1 reach the max voltage when his current became zero (Figure 3):
9
=0
Equation 11
From Equation 3 follows:
−
sin
9
+
=0
Equation 12
Using the boundary conditions for class-E (Equation 6 and Equation 7) in Equation 5 (voltage across
C1) we get:
=
2
cos
%
= − sin
Equation 14
Equation 13
Comparing the two equations, for a duty cycle of 50%, we obtain:
2
= arctan >− ? = −0.563 @A
%
Equation 15
In Equation 12 replacing IDC with Equation 14 we get:
sin
9
+
+ sin
Equation 16
7
=0
Using the Prosthaphaeresis identities we get:
9
= −2
Equation 17
Finally are obtained the popular equations for peak voltage and current for the active device:
7BC =
9
= −2% 7
= 3.5627
Equation 18
BC
=
+
=
−
sin
= 2.862
Equation 19
For a duty-cycle of 50% the peak voltage at the drain terminal exceeds by more than three times the
supply voltage of the circuit.
Dr. Raab in (2) has presented all the equations that govern an idealized class E RF power amplifier, in
particular, he has proved that a duty-cycle of 50% represents an optimum in terms of output power
capability. Moreover, the device’s breakdown voltage determines the maximum allowable supply
voltage and it is in direct relation to the output power.
3.3 Design equations for finite QL.
When QL (defined as 2πfL2/R) decreases the above equations progressively produce less-accurate
results.
In some cases the Dr. Raab’s equations (2) have been represented in tabular form with the output
power, C1 and C2 as function of QL.
8
Table 1 – Tabular Raab’s equations vs QL
Even if QL is a free-choice design variable from the theory it must satisfy the condition QL ≥ 1.7879,
when QL =∞ we may recognize the results already found.
In (4) Dr. Sokal found compact design equations representing the data showed in Table 1 using
polynomial functions in QL.
1 = 0.576801 ∙
7 − 7D
5
+
∙ !1.001245 −
0.451769 0.402444
−
$
FG
FG +
Equation 20
Equations for C1 and C2 were found through similar fitting process used for R.
=
0.1836
0.91424 1.03175
∙ H0.99866 +
−
I
1
FG
FG +
Equation 21
+
=
1
1
1.01468
∙J
K ∙ J1.00121 +
K
1 FG − 0.104823
FG − 1.7879
Equation 22
L+ =
FG 1
Equation 23
9
3.4 Finite DC-feed inductance
Use a finite DC feed inductance instead of an RF-choke has significant benefits (5), (6) :
• Higher load resistance then less losses on the output matching network (7)
• Possibility to use devices with lower breakdown voltage.
To analyze a circuit with DC finite feed inductance is quite complex, a practical approach (3) is to
choose the RF choke reactance large in comparison to the reactance of the shunting capacitor, i.e.
L > 10 ∙
1
Equation 24
Using Equation 8 (Class E at optimal operation) this condition become:
1
L > 10 ∙
≅ 551
0.1836
Equation 25
4. Design a 500W Class-E at 13.56MHz
Hereafter the target specifications for the design:
Table 2 - Target specifications
4.1 Device selection and circuit simulation
Using the Advanced Design System (ADS) from Keysight (Agilent) we have analyzed the RF
performances of the switch mode Class-E power amplifier. The analysis of the circuit was done using
the transient envelop and the harmonic balance simulation. With the transient envelop we optimized
the values of the output components (Figure 4) in Class-E conditions (Equation 6, Equation 7)
10
Figure 4 - Transient envelop simulation
In simulation we implemented the Equation 20, Equation 21 Equation 22, with capacitors and
inductors lossless and loaded quality factor QL (resonant load) chosen high as 10. The measure
equations include the conditions when the switch voltage and its voltage derivative is zero just before
the switch is turned ON. Were considered 20th periods in order to reach the steady-state condition and
check the class-E conditions.
Figure 6 –Zoom of transient at 20th period
Figure 5 – Transient to reach the steady-state
To evaluate the relationship between the device’s RDS(on) and the required R_load required from
theoretical class-E we did a switching voltage simulation at different coefficient factor R_load_factor
defined as ratio between the RDS(on) and the R_load (Figure 6).
11
At Switch-ON the class-E conditions were met with R_load_factor = 0.03 and RDS(on) =82 mΩ.
In Figure 7 and Figure 8 are showed voltage and current with the value of the components as optimized.
Figure 7 – Current waveform of the MOSFET
Figure 8 - Drain voltage of the MOSFET
For the project we selected the SD4933 from STMicroelectronics, the device is a 50 V N-channel MOS
field-effect RF power transistor specially designed for ISM applications up to 100 MHz (7).
Since the SD4933 has RDS(on) =170mΩ at ID = 20A using two devices in parallel we have RDS(on)
=85mΩ, that is similar to the value obtained before.
In simulation we found a drain peak voltage of 173V, this value is compatible with the breakdown
voltage reported in the datasheet of SD4933.
In order to get an amplifier with high efficiency we estimated the losses of each component.
To build the amplifier we used ATC 100B capacitors with high Q. To minimize the total losses we
used multiple capacitors in parallel (C1 and C2), for them we estimated an equivalent ESR=5mΩ. The
wire wound inductors used in the amplifier were hand-made, we did preliminary trials to obtain an
ESR=100mΩ for each of them.
12
Figure 9 – Harmonic Balance simulation
Implementing the equations for Class-E plus the device’s losses inside the harmonic balance (Figure
9) we got the following results.
FIGURE 10 – Voltage of the MOSFET
Figure 11 - Current of the MOSFET
From simulation we got an efficiency of 93.4% and a power out of 512W at 13.56MHz (Figure 12) .
Using two SD4933 in parallel we have halved the RDS(on) and the stray inductances but we doubled
the equivalent capacitance Coss.
At this point of the design the nonlinear characteristic of the Coss versus the drain voltage was under
particular consideration.
To depower the negative effects of Coss we introduced the advantages offered by the finite feed inductor
already introduced.
13
separately. At the drain’s leads of each SD4933
were added external ceramic capacitors in
parallel, the value of these capacitors has been
chosen to be about one half of the Coss. These
additional capacitors have a balancing effect
against the nonlinearity of Coss. Moreover, the
finite feed inductor (dynamically in parallel
with
the
drains)
helps
to
reduce
the
impedance’s module without change the
Figure 12 – Power Spectrum
capacitive behavior of the impedance (a new C1
Two SD4933 in parallel at VDS=0 have an
in fig.2). This new C1 with reduced value and
equivalent Coss= 800pF. Instead to consider two
better linearity is the capacitance at the
devices in parallel as an equivalent single
entrance of the resonant output thank C2-L2
device, we decide to address the two Coss
(see fig.2).
4.2 Gate driver
Dedicated consideration was done about the current gate driver’s capabilities and his role on the overall
efficiency. In order to drive the parallel of two SD4933 we used a gate driver with high peak current
capability like the DEIC515 from IXYS (8).
This gate driver can source and sink 15A of peak current while producing voltage rise and fall times
of less than 4ns, and minimum pulse widths of 8ns.
4.3 Prototype and RF performances
The schematic and the BOM of the project are here presented:
1
2
3
4
5
6
7
8
GND 50 V
GND
J2
VCC
3
2
1
Vcc
1
2
3
GND
C66
VccIN
A
C2
D2
R2
Vout_reg
5V
R39
GND
A
C4
C1
RK1
GND
C3
R1
GND
GND
R15
C7
GND
VG
C6
GND
U1
R7
0
1
2
3
4
C12
GND
GND
8
7
6
5
C8
R33
Short
C9
C13
C14
GND
GND
LP2951ACM
R4
C15
C16
GND
1
C10
GND
C11
4
Vbuffer
C17
GND
C76
GND
U3
C20
C65
C18
C72
C70
C73
GND
3
GND
GND
R3
GND
C23
RG1
RG2
Q1
C24
0
R16
C25 C26 C27
GND
R14
GND
C22
GND
R9
2
C50
R19
C28
GND
R17
C29
GND
GND
C32
GND
SD4933
GND
B
C31
B
GND
GND
+10 V
3 X R22
GND
L1
C33
P3 1k
R20
C39
GND
4
Cap Var
~53nH
C42
C38
1
2
3
4
P1
500
4 X R18
GND
8
7
6
5
U6
GND
GND
+10 V
GND
GND
C45
C46 C47 C48 C49
C51
GND
R29
C44
Vcc
GND
R30
3 X R22
LT1818CS8
U4B
SN74ACT74D
GND
N_Female
C43
U5
GND
50 Ohm
GND
C40
100pF
Cap Var
C41
R27
C56
C74
C71
C75
C53 C54 C55
GND
C78
GND
C5
GND
C30
GND
C77
GND
12
11
C21
C37
GND
R24
0 Ohm
R31
C34
C35
GND
14
Vcc
CLK
PR
Q
6
D1
LED
7
Q CLR
1
R25
J1
Out
L2
L3,L4,L5
5
C36
GND
Vcc
T1
D
R21
GND
GND
2
3
U4A
SN74ACT74D
Q2
SD4933
GND
P2
U2
GND
Vout_reg
10
R10
R12 short
GND
Q
PR
D
GND
1
2
3
4
C63
8
7
6
5
LP2951ACM
9
13
Q CLR
C
CLK
C57
8
15
Figure 13 - Schematic
GND
C19
GND
Vinp 10 V
C
C58
RG3
GND
R8 R11
Short
C52
GND
C59
R34
GND
GND
U4
SN74ACT74D
GND
J3
C61
RK2
R13
Vcc
C62
Vbuffer
3
2
1
GND
RG4
GND
VG
GND
VCC
GND
C60
C67
GND
GND
GND
D
D
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Table 3 - BOM
16
After an extensive hand-on lab activity was required to refine the RF performances of the power
amplifier, the results are here shown. In Figure 14 we see Pout and the Efficiency versus the supply
voltage. When Vdd= 50V the Pout reach 500W while the Efficiency settle to 88% which is slightly
lower than expected.
Figure 14 - Pout and Efficiency vs VDD
Figure 15 – Drain Current and Voltage Peak vs VDD
17
In Figure 15 we can see the peak current and voltage at the device’s drain.
When Vdd=50V we can see that the drain peak voltage is a little bit higher than expected from the
theory, however the value is still inside the device’s specification.
In Figure 16 we can see the demo of the amplifier, in particular in Figure 17 is visible the finite feed
inductor made with thin copper located in the back side of the board.
Figure 16 – Demoboard for Class-E
Figure 17 – Finite Feed-Inductor beneath the Demoboard
18
Conclusion
This article has recalled the theoretical guidelines and the practical aspects for synthesizing the
matching networks of a high power RF class-E amplifier.
The performance of a SD4933 from STMicroelectronics has been studied thoroughly. It was shown
that the high efficiency operation of such amplifiers is determined mainly by the output load network.
Nevertheless the power efficiency is a little bit lower than expected (declared at the beginning of the
design), we deem that with a different gate drive and a proper input matching network the performance
of the amplifier can be substantially improved.
Authors Biography
Alfio Scuto (alfio.scuto@st.com) received the Master’s degree in
Microelectronics engineering from the University of Catania, Italy.
In the 1999 he joined the STMicroelectronics - RF Power Design Center in
Montgomeryville (PA) USA - as RF Application Engineer he was involved in
the characterization of high-power and high-frequency transistors (DMOS and
LDMOS).
In the 2002 he moved to STMicroelectronics in Catania (Italy) to support the RF products marketing
group developing power amplifiers in order to evaluate and verify product performances in reference
to customer specifications.
Today he works as High Power Application Engineer supporting customers and exploring new
applications for High Power MOSFETs device.
Roberto Cammarata (roberto.cammarata@st.com) Received the Master’s degree in
Electrical Engineer from the University of Catania , Italy. He begins in hearth satellite
ground stations (Selenia_Marconi Comm.) microwave field in 1985, after he
works in Space Satellite Projects (Alenia Aerospace) and finally (Richardson and
STM) in power amplifiers design for Communications and ISM RF applications.
19
References
1. Class E - A new class of high-efficiency tuned single-ended switching power amplifiers. N. O. Sokal, A. D.
Sokal. s.l. : IEEE , June 1975, IEEE - Solid-State Circuits, pp. 168-176.
2. Idealized Operation of the Class E Tuned Power Amplifier. RAAB, FREDERICK H. s.l. : IEEE TRANSAClTONS
ON CIRCUITS AND SYSTEMS, DECEMBER 1977. VOL. CAS-24, NO. 12.
3. Sokal, N. O. and A. D. Sokal. Class E Switching-Mode RF Power Amplifiers-low Power Dissipation, Low
Sensitivity to Component Tolerances (including Transistors), and Well-Defimed Operation. RF Design. Vols.
vol. 3, no. 7, July/August.
4. Sokal, Nathan O. CLASS-E HIGH-EFFICIENCY RF/MICROWAVE POWER AMPLIFIERS: PRINCIPLES OF
OPERATION, DESIGN PROCEDURES, AND EXPERIMENTAL VERIFICATION. s.l. : Design Automation, Inc.
5. A.V.Grebennikov, H.Jaeger,. ”Class E with parallel circuit - a new challenge for high-efficiency RF and
microwave power amplifiers”. IEEE MTT-S International Microwave Symposium Digest. June 2002, , Vols. Vol.
3, 2-7, pp. 1627-1630.
6. D.Milosevic, J.van der Tang, A.van Roermund. ”Explicit design equations for class-E power amplifiers with
small DC-feed inductance". Proceedings of the ECCTD,. Vols. Vol. 3, September 2005, pp. 101-104.
7. STMicroelectronics. HF/VHF/UHF RF power N-channel MOSFET. SD4933.
8. IXYS. 15 Ampere Low-Side Ultrafast RF MOSFET Driver .
9. Grebennikov, Andrei. RF and Microwave Power Amplifier Design. s.l. : Mc Graw Hill, 2005.
10. Holzman, Eric. Essentials of RF and Microwave Grounding. s.l. : Artech House, 2006.
11. Puczko, M. K. Kazimierczuk and K. Exact analysis of Class E tuned power amplifier at any Q and switch
duty cycle. Feb 1987, Vols. IEEE Trans. Circuits and Systems, vol. CAS-34, no. 2, pp. 149-159.
20