UNIVERSITY OF NAIROBI
A 600W SWITCHED MODE POWER SUPPLY FOR 12V SYSTEMS
PROJECT INDEX: PRJ063
BY
KALENGA THOMAS TSUMA
REG. NO: F17/2154/2004
SUPERVISOR: MR. C. OMBURA
EXAMINER: DR. MANG’OLI
PROJECT REPORT SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENT FOR THE
AWARD OF THE DEGREE OF BACHELOR OF SCIENCE IN ELECTRICAL AND ELECTRONIC
ENGINEERING OF THE UNIVERSITY OF NAIROBI.
DATE OF SUBMISSION: 19TH MAY 2009
DEPARTMENT OF ELECTRICAL AND INFORMATION ENGINEERING
i
DEDICATION
To my mum,
What would life have been without your support and care.
ii
ACKNOWLEDGEMENTS
I wish to express my heartfelt gratitude to my supervisor Mr. C. Ombura for the guidance,
support and constructive criticism that you offered.
Special thanks go to my entire family for your consistent moral and financial support .
To my friends; Mr. Andrew Mbaji and Miss Angeline, your encouragement, love and support
has gone along way into the completion of this project.
Thanks a lot.
To all my classmates; thank you for the encouragement and hope, your suggestions, questions
and odd jokes helped shape the project. Again I say thank you for putting the smile back in its
place when times were hard.
iii
ABSTRACT:
Some electronic equipment require a higher voltage than the 12V provided by a battery or
accumulator. Thus to power these equipment there is need for an efficient power supply that
can convert the low 12V battery voltage into a high (40V dc )for such equipment as car audio
amplifiers, lighting when camping, television sets and DVD player in vehicles. This project
explores the design methods and tradeoffs that were utilized to accomplish high efficiency in
the switch mode power supply. An isolating DC to DC converter was selected for the power
system because of requirements for separate primary and secondary grounds and for a wellregulated secondary output voltage derived from a slightly varying input voltage. A push-pull
topology circuit was chosen for this converter because of its potential for high efficiency and
reliability. To enhance efficiency, a non-dissipative snubber circuit for the very-low-Rds-on
Metal Oxide Field Effect Transistors (MOSFETs) was utilized, redistributing the energy that
could be wasted during the switching cycle of the power MOSFETs. All of these choices
contributed to the design of a highly efficient 600W regulated dc to dc converter. The
methodology used in the design of this DC to DC Converter Unit may be directly applicable
to other systems that require a conservative approach to efficient power conversion.
iv
TABLE OF CONTENTS
DEDICATION………………………………………………………………………………...i
ACKNOWLEDGEMENT…………………………………………………………………….ii
ABSTRACT …….…………………………………………………………………………..iii
CHAPTER 1: INTRODUCTION…………..…………………………………………………1
1.1 Project Objectives…………………………………………………………1
1.2 Why switched mode power supply………………………………………..1
1.3 Recognition of previous work………………….………………………….1
CHAPTER 2 : BACKGROUND INFORMATION AND THEORY..………………………3
2.1 Theory ………………………………………………………..…………3
2.1.0 Input rectifier and filter …………………………………..…..3
2.1.1 High frequency inverter…………………………………………3
2.1.2 Power switches ………………………………………….………4
2.1.3 Output rectifier and filter ……………………………………….5
2.1.4 Control circuit………………………………………………...…5
2.2 Types of SMPS………………………………………………………...…5
2.2.0 Push-pull converter………………………………………………6
2.2.1 Bridge type conveter…………………….....................................8
2.2.2 SCR power supplies……………………………………………11
2.3 Performance parameters…………………………………………………12
CHAPTER 3: ACTUAL DESIGN OF THE POWER SUPPLY…………………………….13
v
3.1 Input circuit………………………………..…………………………….13
3.2 Power stage………………………………….……………………………12
3.2.0 Switches………………………………………………………...12
3.2.1 Power switch losses……………….……………………………13
3.2.2 Transformer…………………….……………………………..15
3.2.3 Snubber circuit……………………..………………………….19
3.3 Output stage…………………………………..…………………………..20
3.3.0 Rectifier selection………………….……………………….….20
3.3.1 Filter design………………………..…………………………..20
3.4 Control circuit………………………………….…………………………21
3.4.0 Control IC………………………….………………………….22
3.4.1 Feedback …………………………..………………………….22
3.4.2 Protection……………………………..………………………23
CHAPTER 4: OPERATION OF THE DESIGNED CIRCUIT ..…………………………...24
CHAPTER 5: RESULTS AND ANALYSIS …..…………………………………………....29
CHAPTER 6: CONCLUSION AND RECOMMENDATIONS … …..…………………..…34
APPENDICES: ………………………….………………………………………………...…35
Appendix A: Derivation of output power relations in push-pull topology. ……...….36
Appendix B: Derivation for the output voltage relations in push-pull topology….…39
Appendix C: Transformer core type chart………………………..……….…………41
Appendix D: Component Datasheet…………………………..…………...…………43
vi
D1: The SG3525A datasheet…………………………………………43
D2: The IRF1010E N-channel MOSFET datasheet…………..……49
Appendix E: Programme code for computation of component values………………52
REFERENCES………………………………………………..……………………..………56
vii
Chapter 1
INTRODUCTION
1.1 Project Objectives
The project is aimed at coming up with specification design and implementation of a high
efficient 600W DC/DC converter for 12V systems. My design uses a 12V accumulator as the
input and outputs a regulated 40V that can be used to power high voltage DC equipments. A
switched mode push-pull DC/DC converter was designed taking into considerations the
appropriate trade offs in terms of cost, losses and reliability.
1.2 Why switched mode power supply (SMPS)
Switched mode power supplies offer the advantages of a smallest size, weight and cost while
achieving much higher power efficiencies, almost any current benefits from reduction of
weight and size. Although SMPS have a more complex circuitry and high cost than linear
power supply, at medium power levels, cost of design of dealing with high heat dissipation
outweigh the cost of complex design. Improved energy efficiency is a required feature in
most products especially in battery products; the battery life is a major selling point. Energy
efficiency has become a major government requirement like the USA energy star programme.
1.3Recognition of previous work
A lot of research has been going on in the design of high efficient switched mode power
supplies. Most of which dealt with designing a particular component of the power supply say
like the control mechanism, power factor correction or efficiency improvement. SMPS are
using new technologies to meet system demands for more power. They are moving into the
Megahertz switching frequencies, shrinking in size, and becoming more efficient.
My design mostly required integrating all these ideas into a complete design, which is
efficient and reliable.
1
The project is organised into six chapters. Chapter one gives the general introduction, project
objectives, the need for the design and previous work.
Chapter two gives the theory and background information concerning the switched mode
power supplies. The principles of operation of the various topologies of medium SMPS are
discussed here. Different power supply topologies are compared based on power output and
efficiency.
Chapter three deals with the system design outlining the various components block diagrams
and sub-circuits used. A detailed account on the choice of particular components and trade
offs made based on cost, availability and efficiency are presented.
Chapter four gives a detailed explanation of the working of the designed circuit.
Chapter five gives the results and analysis of the data obtained while chapter six gives the
conclusion and recommendations.
2
Chapter 2
THEORY OF DC/DC CONVERTERS
2.0 Theory
The switching mode power supply is a class of power supplies that makes use of electronic
switching to process electrical power. Because ideal switches do not dissipate power, the
SMPS can be designed to have a high efficiency. In the SMPS a high frequency of switching
is used and the size of the transformer and filtering circuits can be minimized. Because of
these great advantages, the SMPS has become the power processing unit of choice in low
power circuits or circuits where interference must be kept to a minimum.
The heart of a SMPS is a dc-to-dc converter. The converter accepts a dc input and produces a
controlled dc output. The three basic types are the buck converter, the boost converter, and
the buck boost converter. For each of these converters there is an electronic switch that is
driven ON or OFF by a high frequency (5-500 KHz). It is the duty cycle of the electronic
switch which controls the dc output voltage Vo. There is an output filtering capacitor Co
which is used to smooth out the ripple components of the output voltage resulting from the
high frequency switching. By adding a feedback circuit in a converter, the output voltage of
the converter can be regulated.
Figure 2-1 shows the basic building blocks of an SMPS system.
2.1.0 Input rectifier and filter
This comprise of a rectifier bridge and capacitors. The bridge rectifies the input alternating
voltage to unregulated DC voltage. The capacitors are used to smoothen this voltage before
its input to the power stage.
2.1.1High frequency inverter
This is the heart of the power supply. It is normally referred to as the power stage in SMPS
design. Its main function is to chop the rectified input voltage at high frequency (20 kHz- 1
3
MHz). The inverter also transforms the line voltage to the correct output level. It is made of
the power switches and a transformer.
2.1.2The power switches.
Transistors are the switches of choice when dealing with low to medium power supplies.
Ideally they are switched “full-on” and “full-off” reducing wasteful power dissipation.
Power MOSFETs are preferred to bipolar transistors because they can operate at high
frequencies up to megahertz due to their majority carrier nature and can be driven directly by
the new control ICs.
MOSFETs are voltage controlled and require very little current to drive hence require a
simple drive circuitry.
Figure 2-1 Block diagram of a switched mode power supply
4
2.1.3 Output rectifier and filter
In the output section high frequency rectifiers are needed, there are several types available.
In addition to the Schottky (SBR) and fast recovery (FR), there is also an ultrafast recovery
(UFR). Schottky diodes are generally used for 5.0 V outputs and fast recovery and ultrafast
devices for 12 V outputs and greater. The ultrafast is competing both with the Schottky where
higher breakdown is needed and with the fast recovery in those applications where
performance is more important than cost.
Since the result of the switching action of the power transistors is a square waveform, this
must be filtered to provide the desired output. Thus an LC filter is used to accomplish this.
2.1.4 Control circuit.
This circuit regulates the output voltage by closing the loop from the output to the inverter.
Most control circuits generate a fixed frequency internally and utilize pulse width modulation
(PWM) techniques to implement the desired regulation. The on time of the square wave drive
to the inverter is controlled by the output voltage. As load is removed or input voltage
increases , the slight rise in output voltage will signal the control circuit to deliver shorter
pulses to the inverter and conversely as the load is increased or input voltage decreases ,
wider pulses will be fed to the inverter.
2.2.0 TYPES OF SMPS
The most widely used converter topologies are:
•
Flyback
•
Forward
•
Push-pull
•
Half and full bridge
Both flyback and forward converters store energy in an inductor, and only when there
switches are conducting [1]. But a flyback, or “parallel,” converters load is in parallel with
the inductor, so its stored energy passes to the load during the off (flyback) period. On the
5
other hand a forward “series” converters inductor is in series with the load, so its energy goes
into the load and inductor simultaneously during the on period and as well as into the load
from the inductor during the off period.
A push-pull converter reduces output voltage ripple by doubling ripple-current frequency to
the output filter. Moreover, it uses smaller transformer cores because unlike forward or
flyback converters’, it excites the transformer core alternately in both directions. But pushpull transformers are subject to DC imbalance that can lead to core saturation.
Push-pull converter transformers can be single ended, push-pull, half wave or full wave
bridge.
Table 2-1 summarizes each of these four DC/DC converter types. A detailed discussion of
each type can be found by referring to reference [1]
Figure 2-2 depicts several of these categories:
•
Full bridge for large outputs from hundreds to thousands of watts.
•
Two switch flyback converter for high voltage power applications.
•
Push-pull for medium to large outputs from hundreds to thousands of watts.
•
Two switch forward converter type for low power applications.
2.2.1 Push-Pull Converters
For higher power outputs push-pull are more suitable. In the medium power range from (10
to 100W), the self-oscillating push-pull is commonly used.
Basically, the circuit uses two power transistors in a symmetrical square-wave oscillator. It
perhaps can be best compared with a mechanical vibrator without contacts. The transistors
play the part of switches that are constrained to be alternately on and off to connect the
unidirectional input voltage alternately to the separate primary windings of an output
transformer. This produces an alternating square-wave output across the transformer
secondary
6
(a)
(b)
(c)
(d)
Figure 2-2 Basic types of converter supplies. (a) full bridge converter. (b) two switch flyback
converter. (c)push-pull converter. (d ) two switch forward converter.
7
For very high power out puts driven converters (figure 2-2c) are more common than selfoscillating ones although self oscillating units are quite high power can be found for example
250W from one pair of power transistor has been achieved. Another circumstances calling for
driven converters is that in which multiphase AC out put is required. But one of the most
common reasons for preferring driven circuits is active at present and much of the
conventional circuit design of the magnetic and servo amplifiers is applicable to it. Out put
into kilowatt range are being achieved. This is primarily concerned with self oscillating and
driven push pull (parallel) converters.
2.2.2 Bridge type converters
Many of the disadvantages of push pull circuit can be alleviated by the use of bridge
converters als shown in figure 2.2 d. In this circuit, the transistors switch at the applied DC
voltage E instead of 2E as in the push pull case but, there are some problems that must be
overcome especially in the drive circuitry. Because the transistors see only half the voltage of
the push pull circuit, it is possible to use this circuit from rectified 240 V AC lines while still
specifying only 400 volts transistors. It is also possible to design a dual input converter if the
117 volt input is used wit a voltage double rectifier.
The leakage inductance problem associated with the push pull circuit causes large spikes of
voltage to appear at the switching transistors. The half bridge converter does not have this
problem because the energy stored in the leakage inductance of the power transformer is
conducted back into the DC bus through the commutation diodes.
Unequal turn-off times in the power transistors results in core saturation with the push pull
converter. By using the half bridge converter, the addition of the series capacitor feeding the
primary of the power transformer eliminates the DC core flux problem. The unbalance of the
turn off times merely produces a shift in the mean DC level of the waveform so that the
transformer now sees balance volt-seconds. A full bridge converter doubles the number of
power transistors over the half bridge converter, thus doubling the current carrying capability
(and output power) but it requires four isolated drive signals.
8
Table 2-1 DC/DC converter comparison
Type
Flyback
advantages
disadvantages
•
Isolation from supply to line.
•
Output doesn’t need to be filtered
•
High output ripple
by choke
•
Requires large core
•
Simple circuit
•
Low component count easily
inductors
•
levels.
provides multiple outputs.
•
Low power output
Simple power transistor base drive
circuit.
•
Useful in low power applications.
•
Forward(single ended or
ringing choke
Requires addition of
•
Low output voltage ripple.
transformer for line
•
Easily provides multiple outputs
isolation.
•
Needs only single switching
•
•
Extra winding and
transition.
components required
Simple power transistor base drive
for multiple output
circuitry.
•
Useful low power applications.
•
Low output voltage ripple.
•
Good regulation
•
Uses small transformer
push-pull
•
High component
count.
•
Complex circuit
•
Complex power
component cores.
•
Provides automatic line isolation
transistor base drive
•
High power output capability
•
Useful in high power high
circuitry.
•
Subject to dc
imbalance which can
performance single output
cause core
applications.
saturation.
•
Extra winding and
components required
for multiple output
9
•
Half bridge
Transistors see supply
voltage(approx)
•
Primary utilization 100%
•
Leakage inductance spikes
•
Isolate drive
required.
•
Drive circuit must
conducted back to DC bus
have low
Low intertwining capacitance
capacitance
allows fast switching
•
•
Capacitor C eliminates DC core
•
Capacitor must pass
full primary current
flux: collector currents are
balanced.
2.2.3 SCR Power Supplies.
Silicon controlled rectifiers (SCR’s) are sometime used in place of transistors in parallel
(push-pull) converters to increase power capability of the power supply. The use of SCR’s in
place of transistors for power levels of less than 2KW has been limited for several reasons:
•
SCR’s are slow-speed switching device and thus tend to dissipate more power than
transistors. Typically, the turn off time for an SCR may be several microseconds
whereas the turn off time for a comparable transistor is tens to hundreds nanoseconds.
•
SCR’s are capable of supporting much higher load currents than transistor. Therefore,
as load requirements increase, SCR’s become more desirable than transistors, the heat
sink and thus the weight requirements increase also.
•
SCR inverters are heavier than transistor inverters.
•
SCR inverters circuit is complex, requiring extra circuit to turn the SCR’s off. This is
not so with transistor inverter, which are simpler in nature.
•
SRC circuits results in lower reliability because of the need for communication and
the addition of complex logic circuit to prevent false triggering and provide proper
communication timing.
•
For power levels up to2kW transistor inverters offer a substantial increase in reliable
operation and efficiency compared to SCR’s.
10
2.3.0 Performance parameters.
The primary function of the power supply is to hold the voltage in its output circuit at a
predetermined value over the expected range of load currents. Working against the supply are
variations in load current, input voltage and temperature. The degree to which a power supply
can maintain a constant voltage output in the face of these variations is the figure of merit.[1]
Load regulation is the extent to which the output voltage is affected by output or load current
and is expressed as a percentage of the output voltage. The general formula for load
regulation is
Load Regulation (%) = (
Eml − E fl
Eo
)100 …………………………….1
Where Eml=output voltage with minimum rated load
Efl=output voltage with maximum rated load
Eo=the nominal or reference output voltage (usually Efl to minimize the numerical
value of load regulation)
Input regulation is a measure of the effect of changes in the input voltage on the output
voltage. Input regulation is given by;
Input Regulation (% / Ein ) = (
∆Eo
)100 ………………………………………..2
∆Ein × Eo
Where: ∆Eo = change in output voltage Eo, for ∆Ein
∆Ein = change in input voltage.
Eo = nominal output voltage
Chapter 3
11
ACTUAL DESIGN OF THE POWER SUPPLY.
The design specifications of the power supply were;
•
Output voltage = +40V
•
Output power = 600W
•
Input voltage range 12-13.8v dc
3.1 input circuit
The input circuit was made of a 12V battery, and three capacitors for smoothening the output
as well as help sourcing the high currents during switching.
3.2 power stage
This is the heart of the power supply. It is composed of the power switches and the
transformer.
3.2.1 Switches
The choice of power switching element was very important for an efficient design. High
current bipolar devices require substantial base drive power, which hurts efficiency unless
regenerative drives are used. High gain bipolar devices, such as Darlingtons, have a high
saturation voltage drop. Insulated-gate-bipolar transistors (IGBTs) have a similar problem
with conduction losses. Thyristors are subject to noise/rate triggering as well as junction
voltage drop losses [2]. Power Field Effect Transistors (FET) was the optimum choice for
this application due to their very low ‘on-resistance.’ Thus metal Oxide Field Effect
Transistors (MOSFET) was used.
The MOSFETs were then paralleled to reduce their thermal requirements since the effective
case to heat sink thermal resistance of the pair is half that of a single MOSFET. This allows
the MOSFETs to run cooler and more efficiently for the same cost as an equivalent single
MOSFET.
12
The MOSFET’s sources were then connected to ground to allow them to be driven directly
from the control circuitry without voltage isolation thus reducing the overall cost at the same
time not compromising the efficiency of the design.
Estimating the significance minimum parameters of power switches, the maximum voltage
stress on the switches was determined as;
VDSS = 2 Vin = 2(13.8) = 27.6v
ID
=
(3.1)
1.2 Pout
1.2(600 )
=
= 60A
Vin (min)
12
(3.2)
Where VDSS is the minimum gate to source voltage rating of the switch and ID is the
minimum current rating of switch.
Thus the IRF1010E was chosen since its has the following desirable characteristics
VDSS = 60V
RDS(on) = 12mW
ID = 84A.
3.2.1.1Power switch losses
Ac losses
These are negligible at turn on because transformer leakage inductance causes a very fast
voltage fall down and a slow current rise time. This results in very little overlap of fall
voltage and rising current. Worst case scenario is assumed at turnoff. Current remains
constant at its peak Ipft until voltage rises to 2Vdc. Then the voltage remains at 2Vdc during
the time it takes the current to fall to zero. Assuming equal rise and fall times the losses are
given by:
Pt ( ac ) =
I T
2VdcTs
+ 2Vdc pft s
2T
2T
(3.3)
13
= 2 I pft (Vdc )
I pft = 1.56
Ts
T
Po
Vdc min
Pt ( ac ) = 3.12
I pft = 3.12(
PoTsVdc
Vdc minT
600 ×13.8 ×110 ×10−9
)
12 × 20 ×10−6
= 11.84W
Where Vdc=maximum input voltage
Vdcmin= minimum input voltage
Ts = the period switching
T = period of operation
DC conduction losses.
These are a function of the on voltage, the on current and the duty cycle:
Pdc = I pftVon
Pdc = 0.4
0.8T / 2
= 0.4 I pftVon
T
(3.4)
1.56 Po 0.4 × 1.56 × 600
=
= 31.2W
Vdc min
12
When two switches are connected in parallel then their equivalent losses are ¼ of the original
as they share the current equally and losses are a function of the square of the current. Thus
the total losses will be:
P total = [Pt(ac) + Pdc] =[11.84+1/4(31.2)] 4
=78.56W
;
14
3.2.2 transformer
Transformer was designed using the equations derived in the power section in the appendix.
A ferrite core material was chosen because of its inherent desirable properties as stated in the
theory section.
The operating frequency of the system was chosen to be 50Khz.
Selecting the core that could handle up to the required power was done by taking the
maximum flux Bmax=800G so that even if the flux walks then it can not cause destruction of
the switches.
Thus from equation A7 in the appendix A
P0 =
0.001Bmax fAeAb
Dcma
where
Dcma = 500 circular mills/rms Amp
Bmax = 800G
Since the only unknown parameter in the equation above is AeAb,making this the subject of
the equation and solving for AeAb we have
Ae Ab =
P0 × Dcma
0.001Bmax f
Ae Ab = 7.5cm 4
The value of AeAb was then compared to the charts from transformer core datasheets from
different manufacturers and the core with a higher area product was chosen. This table of
core data sheet is provided in the appendix
Thus the cores that I can use are:
Ferrox-cube Phillips –EE55 (volume 43.50cm3)
15
With
Ae = 3.530cm2
Ab = 2.800cm2
AeAb = 9.884 cm4
Po = 0.001×
800 x50 x103 x9.884
= 790.72 W
500
(Volume = 40.10cm3)
2. EC70
Ae = 2.79 cm2
Ab = 4.77 cm2
AcAb = 13.308 cm4
Po = 0.001×
800 x50 x103 x13.308
= 1064.64
500
Thus the choice will depend on cost and reliability of the core.
Primary turns of the transformer are proportional to the input voltage and duty cycle while
inversely proportional to the effective core area Ae and the maximum flux change dB. Thus
the following equation gives this relationship and was used to find the number of primary
turns.
(Vdc − 1)(0.8 T ) x10 8
Np =
2
AedB
(3.5)
But dBmax = 800G
And T =
1
= 2x10-5sec
50KHz
16
Np =
(Vdc − 1)(0.4T ) x10 8
AedB
Thus in the core EE55
Ae 2.33 cm2
Np =
11x0.4 x 2 x10 −5 x108
= 3.12turns
3.53 x800
≈ 3turns
Using EC 70 core
Ae = 2.79 cm2
Np =
11x0.4 x 2 x10 −5 x108
= 3.94turns
2.79 x800
≈ 4turns
Thus increasing the primary turns will reduce the Bmax making it more stable and the
hysteresis curve more square.
3.2.2.1secondary turns
Taking the equation B1 from appendix B we have

Ns  2Ton
− 1
V0 = (Vdc − 1)
Np  T

(3.6)
But since Ton = 0.4T
Equation becomes
17

Ns 
− 10.8
V0 = (Vdc − 1)
Np 

V
 Np
Ns =  0 + 1
 0.8  (Vdc − 1)
3
 40 
+ 1
=
 0.8  (13.8 − 1)
= 11.95
≈ 12 turns
3.2.2.2 Wire gauges
The wire gauges to be used for the windings are found by considering the values of the root
mean square (rms) current that would flow in the wire so as to take into account the heat
generated. The circular mills per rms current are taken as 500.
3.2.2.3 Primary winding
IPrms
= Ipk
D but D = 0.4
= 78 0.4
= 49.296A or 0.632 Ipk
Cross section area is given by 500 circular mills per rms ampere for large number of
windings and 300 circular mills/rms amperes for small number of windings thus
= 49.296 x 500 = 24,648 Circular mills- 6 AWG
3.2.2.4 Secondary winding.
Is(rms) = I dc D = 0.632 Idc
= 0.632 x 7.5 = 4.74A
18
thus
4.74x 500 = 2370 circular mills ---AWG 16
3.2.3snubber circuit
Snubbers are small networks of parts in the power switching circuits whose function is to
control the effects of circuit reactances. Snubbers enhance the performance of the switching
circuits and result in higher reliability, higher efficiency, higher switching frequency, smaller
size, lower weight, and lower EMI. The basic intent of a snubber is to absorb energy from the
reactive elements in the circuit. The benefits of this may include circuit damping, controlling
the rate of change of voltage or current or clamping voltage overshoot. In performing these
functions a snubber limits the amount of stress which the switch must endure and this
increases the reliability of the switch.
In the design ,an input current snubber made of L2 and L3 were used. These prevent abrupt
rise of current in through the switches on turning on.
The output circuit has an RC snubber with minimal dissipation. This protects the output
diodes from ringing. The value of the resistor was chosen to be equal to the equivalent
impedance of the parasitic reactances of the circuit so as to minimize the overshoot.
While the value of the capacitance is estimated at 3 times the output capacitance of the
switches in this case 690 pF from the data sheet. Thus a 2nF capacitor was used.
3.3 Output Stage
This stage is made up of the rectifier and an LC filter for smoothing the ripple.
3.3.1 Rectifier selection
In selection of the rectifier, the maximum expected voltage across the rectifier was calculated
as below.
19
VR = 2(1.3)Vout = 2 .6 x 40 =104V
The scalar (1.3) is due to the voltage spikes that occur during switching. The forward current
through the rectifier is the same as the output current, hence
IF = IO = 7.5 A.
A full bridge rectifier, with a 200V voltage rating was designed using the MBR2045CT
diodes. These are fast recovery switching diodes with a 20A current rating. A section of its
electrical properties is provided in the datasheet in the appendix.
Fast recovery diodes were used since they recover more softly than schottky because they
have a longer fall time to rise time ratio [1] hence low electromagnetic interference (EMI).
3.3.2 Filter design
A low pass filter was used in the output to smoothen the ripples. Thus it was made of an
inductor and a capacitor. Their design was as shown below.
inductor
LO =
0.05Vo T
Idc
(3.7)
Where Idc(min) = 0.1Ion
=
0.05(40) × 2 ×10 −5
= 53.33µH
0.75
capacitor
Let Vripple = 50mV
dI = 2Idc(min)
= 1.5Amps
20
(80x10 ) dI
−6
CO =
=
Vr
80 × 10−6 × 1.5
50 ×10−3
=2.4mF
The capacitors used should be either multilayered ceramic or improved electrolytic with
lower equivalent series resistance (ESR)and higher capacitance per unit volume. But since
higher frequencies are used, it allows use of lower capacitance values and of smaller sizes.
Tantalum capacitors meet the high capacitance per unit volume requirement thus were used
with a ceramic capacitor shunting it to reduce high frequency noise.
A small programme was developed in C++ to take care of the iterative calculations and with
the design specification, it can calculate the transformer window area product, thus enabling
selection of the particular core that can handle such power.
It also computes the value of the primary and secondary turns, the output filter capacitor and
inductor. Finally it computes the losses expected in the supply if 80% efficiency is assumed.
This code is presented in appendix E
3.4 control circuit
This circuit controls the output of the power supply. A voltage controlled fixed frequency
pulse width modulation technique was used to achieve the desired output regulation. This was
made of:
•
Control IC
•
The feedback loop
•
And the protection circuit.
21
3.4.1 Control IC
The SG3525A was chosen and has the following desirable features;
•
It has a Vcc range of 8-35V hence can be supplied directly from my input,
thus it does not require an external source.
•
It has an inbuilt soft-start circuitry with only an external timing capacitor
required to achieve desired soft start.
•
A single resistor between the CT and DISCH terminal provide a wide range of
dead time adjustments thus controlling overlap.
•
Has a shutdown terminal that controls both the soft-start and output stages
providing instantaneous turn off through the PWM latch with pulsed shutdown
as well as soft start recycle with longer shutdown commands.
•
It also has an undervoltage which keeps the outputs off and the soft-start
capacitor discharged for subnormal input voltages.
•
Its outputs are high enough to drive the MOSFETS fully on thus no need of a
drive circuit.
A small resistance is connected between MOSFET gate and the IC output.
The principle of operation of this IC is provided in the data sheet which is presented in
appendix D
3.4.2 Feedback
The feedback loop was implemented using voltage divider circuit connected to the inverting
input terminal of the SG3525A
Since the reference voltage of the comparator in the SG3525A is 5V , and the output 40V ,the
divider was designed as follows:
Vref = (
R2
)Vo
R1 + R2
(3.8)
Thus solving for the values of R, and letting R1 =1KΩ
22
Then;
5
R2
=(
) = 0.125
40
R1 + R2
1 − 0.125
= R1 = 7
0.125
Thus R2=7KΩ
3.4.3 Protection
Protection of the circuit elements was achieved by incorporating a soft start circuit,
overvoltage and undervoltage protection. All these made possible by the use of the SG3525
chip.
23
Chapter 4
OPERATION OF THE DESIGNED CIRCUIT
A complete schematic of the SMPS designed to meet the required specifications is shown in
figure 4-1. The design will be discussed by dividing the complete circuit into its building
blocks constituent components.
Figure 4-2 (a) shows the input voltage and filtering circuit. The choke is used to stop fast rise
time transients from the car electrical system from disturbing the circuit and also prevent the
switching noise generated from interfering with other stuff in the car like to radio and engine
management computer in the car.
The capacitor and choke combination form a low pass filter hence regulating the input.
Figure 4-2 (b) shows the power stage of the design. Four MOSFETs are used, Q1 and Q2 in
parallel, and Q3, Q4 in parallel. The effective case to heat resistance of the pair is half that of
a single MOSFET and the pairs’ drive requirements can be optimised using less control
circuitry.
The MOSFETs’ source is connected to the ground to allow the MOSFET s to be driven
directly by the control circuitry without isolation to permit a wide range of pulse width for
control of the output.
Q1, Q2 and Q3, Q4 drive the transformer T1 with combined duty cycle of 96% leaving 4%
dead time to prevent power loss and component stress due to overlapping on times.
The control circuitry is shown in figure 4-3. The heart of this circuit is an SG3525A pulse
width modulator IC whose outputs are ideally suited to driving power MOSFETs while
providing the necessary oscillator, amplifier and voltage reference.
24
The IC directly drives the MOSFETs while incorporating the feedback amplifier and soft
start control. RT and CT set the oscillation at 100KHz. Due to the push-pull attributes, the
transformer runs at 50 KHz.
Because the gates of power MOSFETs can be damaged by voltages exceeding +20V, the
supply voltage for the output stage of the IC is limited. This function is performed by the
zener diode D1, C9 and C10. When the voltage exceeds 15V the zener diode is reverse biased
thus pulling VCC and VC to ground, switching off the outputs.
Capacitor Css is connected to the soft start input pin of the IC. This circuit reduces stress on
the supply s’ components by gradually increasing the pulse width during turn on from zero to
40% duty cycle.
Figure 4-5 shows the secondary of the transformer and its associated rectifiers and capacitors.
C1, C2, C5, C6 are high ripple current capacitors capable of handling current ripples from T1
and the ripples currents created by the load. A small capacitance C3,C4 is placed in shunt to
these to filter the output.
25
Figure 4-1 The complete power supply schematic
26
(a)
(b)
Figure 4-2 (a) The input circuit and (b )The power stage
‘
27
(a)
(b)
Figure 4-3 (a) control circuitry (b) the output stage.
28
Chapter 5
RESULTS AND ANALYSIS
A simulation of the complete design was done using emulator software (Multisim 10) since at
the time of presenting the report not all the components had been acquired. Thus results from
the simulation were used in the analysis. The load was varied in random steps and the output
voltage and current recorded.
Table 5-1 gives the data obtained on simulation of the circuit.
A graph of the output load against the output voltage was then drawn. As seen from these
graphs, the output of the power supply remains relatively constant with increased loading
giving a voltage difference of about two volts between minimum loading and maximum load.
Thus load regulation, a figure of merit for power supplies was then calculated as follows.
From chapter 1 equation 1.1 we have
Load Regulation (%) = (
Eml − E fl
Eo
)100
Where Eml=output voltage with minimum rated load
Efl=output voltage with maximum rated load
Eo=the nominal or reference output voltage (usually Efl to minimize the numerical
value of load regulation )
40 − 37.1
)100
37.1
% = 7.816
%=(
Thus the load regulation was found to be 7.816% which is an accepted value. Oscilloscope
screen clippings were taken showing the input and output waveforms at particular load values
taken at random. It was observed that it takes about one millisecond for the output of the
29
power supply to rise from zero to its maximum output. The screen clippings are displayed in
figure 5-1.
Table 5-1data obtained on simulation of the circuit.
Input
Load(W) Voltage(V)
160
16.8
210
16.9
258
16.8
304
16.8
335
16.7
370
16.8
416
16.8
475
16.8
549
16.6
657
16.5
811
16.5
Input
Input
Current
Power
Output
output
Efficiency
(A)
(W)
voltage(V) Current(A) (%)
7.18
120.62
40
4 undefined
16.8
283.9
39.60
5.29
73.97
18.6
312.5
39.3
6.56
82.6
19.7
330.96
39
7.8
91.8
22.3
372.4
38.8
8.62
89.96
23.7
398.2
38.4
9.63
92.9
25.9
435.1
38.2
10.9
95.6
28.7
482.2
37.7
12.6
98.5
33.3
552.78
37.1
14.8
99.3
39.5
659.65
36.3
18.1
99.5
61.8
1019.7
34.8
23.3
79.95
Graph 5-1 plot of the output voltage against the loading.
45
40
35
output voltage(V)
30
25
20
VOLTAGE(V)
15
10
5
0
0
200
400
600
Load (W)
30
800
1000
Graph 5-2 plot of the output current through the load against loading.
Graph 5-3 plot of the power supply efficiency against load.
31
(a)
(b)
Figure 5-1 (a) oscilloscope screen showing the waveforms when the load is 160W
(b)waveform when the load is 305W. Channel A gives the output waveform while channel B
is the input square wave. There magnitudes are shown on the screen window.
32
From table 5-1 the average frequency of the power supply was found to be 90.41%
Its aslo seen from the table that the power supply is more efficient when connected to the
rated load and reduces significantly when its under or overloaded.
At the time of presenting the report some critical components like the PCB board to etch the
circuit had not been acquired thus the simulation results were used hopping these will be
available before presentation so that the actual tested results will be used. The part of circuit
that could be fabricated on bread board was done and tested. Figure 5-2 shows the designed
circuit to be etched on PCB while figure 5-3 shows the gating signals from the control IC.
The power and output stages could not be done on the bread board due to the high currents
involved thus were not ready by the time of presenting the report.
Figure 5-2 the printed circuit board design of the power supply.
33
(a)
(b)
Figure 5-3 (a) and(b) show the gating signals output from the PWM IC
(SG3525A) and are 180 degrees out of phase at a frequency of 100kHz.
Chapter 6
34
CONCLUSIONS AND RECOMMENDATIONS
6.1 Conclusion.
The results obtained in the simulation show that the efficiency of the power supply depends
on the loading. The system was found to have an average efficiency of 90.41% which meets
the design objectives of a high efficiency converter. The supply should be operating a load
between 50-100% of the rated load to achieve maximum efficiency.
Since in the simulation ideal conditions were used the system efficiency is expected to
slightly drop when implemented on the physical board due to impedances introduced by the
tracks on the printed circuit board as well as coupling reactance.
6.2 Recommendations.
The system designed here is not perfect, thus there is room for improvement and
development.
However the project had some limitations e.g. it was not possible to acquire the correct core
size for the transformer (a critical component) and thus a smaller core extracted from an old
PC power supply was used.
On the control a current mode of control could be used as it monitors each current to the
switches on a pulse by pulse basis, forcing alternate pulses to have equal amplitudes thus
guaranteeing no flux imbalance and instantaneous correction of line voltage changes without
the delay of the error amplifier.
APPENDICES
35
APPENDIX A: Derivation of output power relations for push-pull topology
The following output power relations are based on the following assumptions:
Efficiency of the power train - from Vdc to the sum of all outputs neglecting control circuit
dissipation is 80 percent.
The space factor SF, the fraction of total bobbin area occupied by the coil is 0.4. This
includes primary and all secondary plus any RFI or Faraday shields. The SF is low due to
several factors contributing to waste of total bobbin area. One significant factor is turns
within a coil are often widely spaced to make all bobbin areas of equal width to improve
magnetic coupling between layers and reduce leakage inductances. European safety standards
VDE require :
•
4-mm space from each end of a layer to the end of the bobbin .
•
Three layers of 1-mm thick insulating material if secondary are to be
sandwiched in between halves of the primary, that waste 6mills of bobbin
height .
Primary current waveshape as shown in fig.7.3. At minimum Vdc input on time is a maximum
at 0.8T/2. Primary current has ramp-on-a-step waveshape because of inductors at the
secondary output. The ramp swings +_10% about the value at its centre Ipft. The primary
current can be best approximated by a rectangular pulse of peak amplitude Ipft of duty cycle
0.8T/2 or 0.4T. Then for minimum Vdc = Vdcmin
Po = 0.8Pin = 0.8Vdc(min) [Iav at Vdc(min)].
In a push-pull, at Vdc(min), each transistor is on a maximum of 0.8T/2 within its half period.
For two such pulses per period, the total duty cycle of current drawn from Vdc(minb) is 0.8, and
during its on time, each transistor and half primary carries an equivalent flat-topped current
pulse of amplitude Ipft. Then
P0 = 0.8Vdc(min)(0.8Ipft)
36
= 0.64 Vdc(min)Ipft
(A1)
But each half primary carries current at a duty cycle of only 0.4, so rms current in each half
primary is Irms = Ipft 0.4 Ipftt = 1.58Irms
1.58
(A2)
Then
P0 = 0.64Vdc(min)(1.58 Irms)
= 1.01Vdc(min)Irms
(A3)
Figure A-1 push-pull
pull primary current waveshape Ip. Equivalent flat-topped
topped current waveshape
Ipft is used to calculate output power versus Bmax frequency, Ae,Aband Dcma
Again for SF = 0.4, half the total coil area devoted to the primary and half to the secondary
seco
and each winding operating at a current density of Dcma circular mils per rms ampere, we
obtain
Ap = 0.20Ab = 2NpAti
or
37
Ati =
0.1Ab
Np
(A4)
Where Np = number of turns per half primary
Ab = total bobbin winding area, in2
Ati = area of a single turn of primary wire, in2
Now
Dcma =
Atcm
I rms
Where Atcm = wire area in circular mils and Irms = rms current per half primary
Irms =
Atcm
Drms
(A5)
Now Ati = Atcm( π /4)10-6. Putting this into Equation A4 we obtain
Atcm = 0.1273
Ab +6
10
Np
And putting this into Equation A5
Irms = 0.1273
Ab
10+6
N p Dcma
And putting this into Equation A3
P0 = 1.01Vdc(min)
0.1273Ab + 6
10
N p Dcma
38
= 0.129
Vdc (min) Ab
N p Dcma
10+6
(A6)
And again from Faraday’s law
V primary min ≈ V dc(min) =
NpAe∆Bb −8
10
∆T
Where here in a push-pull, flus swing is 2Bmax in a time 0.4T at Vdc(min). Put this into
Equation A6:
Po =
0.129( NpAe)2 B max Ab
× 10−2
0.4TNpDcma
Again is in square inches. If its expressed in square centimeters, devide this last relation by
6.45. then
Po =
0.001B max fAeAb
Dcma
(A7)
Where Po is in watts for Bmax in gauss, Ae and Ab is in square centimeters, f is in hertz, and
Dcma is in circular mils per rms ampere.
39
APPENDIX B: derivation for the output voltage relations in push-pull topology.
Since transistor turnon are sufficient to bring the bottom end of each half primary down to
Vce(sat) level about 1V for the transistor over the specified current range. When transistor turns
on, it applies to half its primary a square voltage pulse of magnitude Vdc-1.
Then for output rectifier forward drop of Vd, outputs at the rectifier cathodes will be flattopped square waves of amplitude (Vdc-1)(Ns/Np) –Vd and of duration Ton . here Vd, the
rectifier diode forward drop, will be taken as 1V for a convectional fast recovery diode.
These output pulses at the rectifier cathodes have a duty cycle of 2Ton/T as there is one such
pulse of duration Ton per half period T/2.
Thus the waveform at input to the LC filters in figure B-1 has a unique flat-topped amplitude
and adjustable width. The LC filter provides a DC output voltage which is the average of the
square wave at their inputs and filter out the square-wave ripple.
Thus the DC or average voltage at Vm output in figure B-2 (assuming D1and D2 are fast
recovery drop) is
Vm = [(Vdc − 1)(
Nm
2T
) − 1] on
Np
T
(B1)
The waveforms at the Vm output rectifiers are shown in figure B-2
40
Figure B-1 push-pull
pull width modulated converter. Transistors Q1 and Q2 are driven by 180
out of phase width modulated signals. Outputs are one master Vm and two slaves(Vs1 and
Vs2). Feedback loop is closed around Vsm and Ton is controlled to regulate it against line
and load changes.
Figure B-22 voltages at main (Nm)secondary winding. Output LC filter is an averaging filter.
It yields DC out voltage =Vm = [(Vdc -1)(Nm/Np)-0.5](2Ton/T).
0.5](2Ton/T). as Vdc varies, the negative
feedback loop corrects Ton in such a direction to keep Vm constant.
41
APPENDIX C: Transformer core type chart
42
43
APPENDIX D: Datasheets
D1 The SG3525A Datasheet
44
45
46
47
48
49
D2 IRF1010E Datasheet
50
51
52
APPENDIX E: computer simulation code for component value computation.
This code was done in C++ to compute the values of output capacitor and inductor.
#include <iostream.h>
float
Pout,Dcma,Bmax,AeAb,Vout,Iout;
int
frequency;
float
Ae,VdcMin;
float
Np;
float
VdcMax;
float
Ns;
float
Vr,dI;
double Co;
float
Pac,Pdc,Pt,Ts;
void getvalues()
{
cout<<"enter power output:";
cin>>Pout;
cout<<"enter Dcma:";
cin>>Dcma;
cout<<"enter Bmax:";
cin>>Bmax;
cout<<"enter frequency of operation:";
cin>>frequency;
cout<<"enter Vout:";
53
cin>>Vout;
cout<<"enter VdcMin:";
cin>>VdcMin;
cout<<"Enter VdcMax:";
cin>>VdcMax;
cout<<"Enter Voltage ripple:";
cin>>Vr;
cout<<"enter Ts:";
cin>>Ts;
};
void calculateAeAb()
{
AeAb=((1000*Pout*Dcma)/(Bmax*frequency));
cout<<"\nAeAb="<<AeAb<<"\n";
};
void CalculateLo()
{
Iout=(0.5*Pout/Vout);
cout<<"Iout="<<Iout<<"\n";
float IdcMin=0.1*Iout;
float Lo=((0.05*Vout)/(frequency*IdcMin));
cout<<"Lo="<<Lo<<"\n";
54
}
void calculateCo()
{
dI=0.2*Iout;
Co=(80)*(dI/Vr/1000000);
cout<<"\nCo="<<Co;
};
void calculateNp()
{
cout<<"\nenter Ae: ";
cin>>Ae;
Np=((VdcMin-1)*(0.4/frequency)*100000000)/(Ae*Bmax);
cout<<"\nNp="<<Np;
};
void calculateNs()
{
Ns=((Vout/0.8+1)*(Np/(VdcMin-1)));
cout<<"\n\nNs="<<Ns;
};
void calculate_losses()
{
Pac=3.12*VdcMin*Pout*Ts*frequency/VdcMin;
Pdc=0.4*1.56*Pout/VdcMin;
Pt=Pac+2*Pdc;
cout<<"\n\nPac:"<<Pac;
55
cout<<"\nPdc:"<<Pdc;
cout<<"\nPt:"<<Pt;
}
int main()
{
getvalues();
calculateAeAb();
CalculateLo();
calculateCo();
calculateNp();
calculateNs();
calculate_losses();
return 0;
}
56
REFERENCES
[1] Hnatek E, Design of solid state power supplies, 3rd Edition. Van Nostrand Reinhold 1989
[2] Abraham I. Pressman, Switching Power Supply Design international Edition
1992,McGraw Hill 1992
[3] Billings, K. Switchmode Power Supply Handbook, 2nd Edition. McGraw Hill. 1999
[4]Magnetics application notes.
[5]Eddy Current Losses in Transformer Windings and Circuit Wiring,” Unitrode Seminar
Manual SEM600,1988
57