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# Answers to the Tutorial 1

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```ELEC3204/ELEC5733
Suggested Solution to the Tutorial 1
Case A- No initial condition specified, circuit element based load modeling
1. Obtain the waveforms of vs , vload and iload when the initial value of the capacitor C0 voltage is chosen to be
zero.
Figure 1. The waveforms of vs , vload and iload when the initial value of the capacitor C0 voltage is chosen to
be zero.
2. Record down the approximate number of cycles needed for the output capacitor voltage to reach steady-state
condition. How do we define steady-state condition for a time varying waveform?
It is approximate three cycles needed.
We say a time varying waveform reaches steady-state when this waveform is constant or repeat uniformly.
Case B Initial condition specified, circuit element based load modeling
3. Plot the waveforms of vs , vload and iload when the initial value of the capacitor C0 voltage is chosen to be the
peak value of the input voltage source (V̂s ).
Figure 2. The waveforms of fvs , vload and iload when the initial value of the capacitor C0 voltage is chosen to
be the peak value of the input voltage source (V̂s ).
4. Observe the time required for the capacitor to be charged and hence the time required for the waveforms to reach
steady-state condition.
The time required for the capacitor to be charged is equal to the time required for the waveforms to reach
steady-state condition. It takes about one cycle for the waveforms to reach steady-state condition.
Prepared by Mingfei Wu. Edited by Dr Lu.
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ELEC3204/ELEC5733
5. Compare the two times required for the output capacitor voltage to reach steady-state condition, i.e., with and
without an initial condition selected in the software.
It takes much shorter time for the waveforms to reach steady-state condition with an initial condition.
6. Generate the spectrum of the output voltage vload and observe the value and location of the three most
significant harmonics. Record their amplitude and harmonic order and also the DC component of the same
waveform.
In order to see the characteristics of a waveform in frequency domain more accurately, we usually choose a part of
the waveform which has already reached steady-state.
Figure 3. The spectrum of the output voltage vload .
7. Perform calculations for the average, RMS, global minimum and global maximum values of the output voltage
waveform using the PSIM functions and keep a record.
Avg: 325.1V
RMS: 326.9V
Global minimum: 269.4V
Global maximum: 388.6V
8. Calculate in percentage the output voltage ripple. How do we define ripple for a given time-varying waveform?
By using the following equation
Vmax − Vmin
Vload(ripple in %) =
&times; 100%
Vavg
We got 33.8%.
Ripple is a periodic variation of a direct current variable.
̅̅̅̅̅̅
̃
9. Investigate the influence of the value of the capacitor on the average (V
load ) and RMS(Vload ) values of the
output voltage by varying its value as follows: 8C0 , 4C0 , 2C0 , 1/2C0 where C0 is the given nominal value.
Record the value and location of the harmonics of the output voltage for each case. Do you need to re-specify the
initial condition for the capacitor voltage in order to get the steady-state condition for the circuit without any
transient intervals?
Table I. The average, RMS and peak values of the output voltage with 8C0 , 4C0 , 2C0 , C0 and 1/2C0.
8C0
4C0
2C0
C0
1/2C0
̅̅̅̅̅̅
309.3V
312.5V
318.2V
325.0V
304.5V
V
load
309.3V
312.6V
318.7V
326.9V
311.8V
Ṽ
load
Vload(max)
315.9V
325.9V
346.1V
383.8V
421.0V
Table II. Harmonics
8C0
4C0
2C0
C0
1/2C0
50 Hz
/
/
/
/
/
100 Hz
5.36V
10.84V
22.3V
46.1V
87.5V
150 Hz
/
/
/
/
/
Prepared by Mingfei Wu. Edited by Dr Lu.
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ELEC3204/ELEC5733
200 Hz
1.69V
3.48V
7.40V
16.2V
33.3V
250 Hz
/
/
/
/
/
300 Hz
0.46V
0.99V
2.26V
5.53V
13.2V
When the capacitance increases, the output voltage becomes smoother.
We need to re-specify the initial condition for the capacitor voltage in order to get the steady-state condition for
the circuit with much shorter transient intervals.
̅̅̅̅̅̅
10. Plot the percentage of the ratio of the peak output voltage (V̂
load ) over the average value (Vload ) as a function
of the capacitor value for the measurements obtained in the previous step.
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
8C
4C
2C
1C
0.5C
̅̅̅̅̅̅
Figure 4. The percentage of the ratio of the peak output voltage (V̂
load ) over the average value (Vload ) as a
function of the capacitor value.
̅̅̅̅̅̅
11. Investigate the influence of the load on the average value of the output voltage (V
load ).
Table III. The average value of output voltage in different loads.
R load
2R load
4R load
10R load
̅̅̅̅̅̅
(Vload )
325.0V
328.0V
329.7V
331.9V
According to Table III, when the resistance of the load increases, the average value of the output voltage will
increase.
12. Calculate for each value of the load resistance, the average power delivered to the load.
Table IV. The average power delivered to the load in different loads.
R load
2R load
4R load
10R load
̅̅̅̅̅̅̅
(P
5.34kw
2.70kw
1.36kw
0.55kw
load )
6.3 Case C – Load modeled as a current source, no line source inductance
13. Simplify the circuit and study it under ideal conditions (i.e., no source inductance 𝐋𝐬 ) and replace the
output capacitance 𝐂𝐨 and the load resistance 𝐑 𝐥𝐨𝐚𝐝 with a DC current source of 15 A.
The circuit for case C is shown as follow
Prepared by Mingfei Wu. Edited by Dr Lu.
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ELEC3204/ELEC5733
Figure 5. The circuit for case C.
14. Obtain the input current 𝐢𝐬 , the input voltage 𝐯𝐬 and the output voltage 𝐯𝐥𝐨𝐚𝐝 waveforms.
Figure 6. the input current is , the input voltage vs and the output voltage vload waveforms.
6.4 Case D – Load modeled as a current source, source inductance specified
15. Compare the ideal case previously studied with a more realistic case when the source is modeled with an
inductance 𝐋𝐬 of 1 mH.
The input current is , the input voltage vs and the output voltage vload of case D are shown as follow
Figure 7. The input current is , the input voltage vs and the output voltage vload waveforms of case D.
Prepared by Mingfei Wu. Edited by Dr Lu.
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16. Explain any differences in the waveforms between the two cases.
In case C, the source current is is ideally square wave and the vload is ideally rectified. In mathematical expression,
vload = |vs |.
However, in case D, because of the effect of the inductance, it costs a short period of time for is to reach +15A and
-15A. In addition, vload is not ideally rectified. There is a voltage drop in the inductor. According to KVL, the
voltage of the load maintains to be zero when the source current increases or decreases. In mathematical expression,
vload = |vs − vL |.
Figure 8. The waveforms in case D.
̅̅̅̅̅̅̅
17. Compare the average value 𝐕𝐥𝐨𝐚𝐝 of the output voltage for the two cases (i.e C and D above) and explain
any differences.
The average value ̅̅̅̅̅̅
Vload is 216.1 V in case C and 213.1 V in case D.
In case C, vload_C = |vs |.
In case D, vload_D = |vs − vL |, and vs and vL have the same sign at all time. Current commutation occurs due to
the inductance which delays the turn-off time of two bridge diode when they are supposed to be turned off during a
half cycle. Therefore four diodes conduct at the same time during current commutation and the output voltage is made
to zero. So a portion of the output voltage is being “stolen” by the current commutation interval and hence the average
̅̅̅̅̅̅̅̅̅
value ̅̅̅̅̅̅̅̅̅
Vload_C in case C is slightly higher than the average value V
load_D in case D.
7 Further Learning Activity
Using the results and observations above, critically discuss the following:
The importance of the initial value of the capacitor voltage for the circuit simulation to reach the steady-state
condition.
Qualitatively, the closer the initial value of the capacitor voltage is to the average value of the output voltage, the
shorter the time for the waveforms to reach steady-state will be.
The effect of the output capacitance value on the ripple of the output voltage and the average output power
delivered to the load.
The effect of the output capacitance value on the ripple of the output voltage:
As shown in Figure 4, the bigger the capacitance is, the smaller the ripple of the output voltage will be.
Table V. The effect of the output capacitance value on the average output power delivered to the load:
8C0
4C0
2C0
C0
1/2C0
̅̅̅̅̅̅̅
(P
)
4.78kW
4.89kW
5.08kW
5.34kW
4.86kW
load
From the above table, it can be concluded that from 8C0 to C0 , the power delivered to the load will increase when
Prepared by Mingfei Wu. Edited by Dr Lu.
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the capacitance decreases and from C0 to 1/2C0, the power delivered to the load will decrease when the capacitance
decreases. There is the maximum power delivered to the load in the capacitance around C0 .
The effect of the load value on the output voltage ripple when the load varies.
By using the definition of the output voltage ripple in Question 8, we can obtain the following table.
Table VI. The effect of the load value on the output voltage ripple.
R load
2R load
4R load
10R load
Vload(ripple in %)
33.8%
18.0%
9.4%
3.9%
The percentage of ripple of the output voltage will decrease when the load becomes smaller.
The influence of the model on the ripple and average value of the output voltage and the source current when
the modeling for the behavior of the load uses a current source (Case C) and when the circuit is studied with
actual circuit elements, such as the output capacitor and the load resistor (Case B).
The output voltage and source current waveforms in case B and case C are different as shown in Figure 9.
(a)
(b)
Figure 9. The output voltage and source current waveforms in case B (a) and case C (b).
Table VII.
Case B
Case C
Vload(ripple in %)
33.8%
157.4%
̅̅̅̅̅̅
325V
216V
Vload
As shown in the Figure 9 and Table VII, in the case B, the output voltage is much smoother. This may be due to the
effect of capacitor. The RMS value of source current in the case B is much smaller.
Use data obtained during the tutorial session in the computer laboratory to support your arguments.
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