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Conference Paper · August 2016
DOI: 10.1109/CCAA.2016.7813945
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Indian Institute of Technology (Banaras Hindu University) Varanasi
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International Conference on Computing, Communication and Automation (ICCCA2016)
1
2
2
1
1
2
< 1 smrityratan2k7.mit, 2
1 IIT (BHU) Varanasi, 2 NIT Durgapur debalina.109.mondal, 2
India animawidu, 1 chandan22sr, 1 akgour.kumar, 2 rajibkarece > @gmail.com
Abstract — In this paper the inductive degenerated Differential
Low Noise Amplifier (DLNA) is designed with operating frequency 2.4 GHz using 0.18 µm CMOS Technology. The DLNA is biased at 1.8 V supply and perfectly matched with input impedance of 50 Ω. Designed DLNA provides power gain of 21.59
dB with a noise figure of 398.1 mdB.
Keywords — Differntial Low Noise Amplifier (DLNA),
Impedance Matching, CMOS Technology, Noise Figure.
Fig. 1. Source Degenerated LNA
To design Differential LNA, single ended source degenerated LNA is used as shown in Fig. 1. Inductive degeneration is used to enhance the transit time effect. Major applications of the LNAs are to increase the signal power as well as minimizing the noise [6].
II.
LNA D ESIGN
I.
I NTRODUCTION
C ommunication system can’t be possible without a Low
Noise Amplifier (LNA). LNA is the basic building block of every communication system [1]. In modern communication field, Radio Receiver plays a very important role, and a Radio
Receiver is made from LNA, Mixer and Filter, where LNA plays a very important role [2]. LNA is an electronic amplifier used to amplify a very weak signal and it is the first stage of radio receiver [3], [4]. A good LNA has large gain, low noise figure and higher intermodulation and compression point [5] -
[7]. A two stage cascode LNA has proposed to achieved noise figure less than 2.5dB and a gain >18dB on specified frequency range with good input and output matching [8].
This paper designs a differential Low Noise Amplifier using
UMC 0.18µm Technology. United Microelectronics
Corporation (UMC) Technology is the first semiconductor company of Taiwan, and the best thing of 0.18µm Technology is that it uses lowest power compare to other Technology.
Advantage of differential LNA is that it cancels the even harmonic term in output so noise reduces to very small value.
Generally, S-parameters type and normal devices are used to design LNA. Advantage of S-parameter type device is that it is a built in device in which there is no need of external bias, so it is widely used. In designing of LNA proper selection of transducer is required so that it provide a maximum gain and low noise figure, because signal received at the antenna of receiver is comparatively weak. A good LNA provide very high gain, good input output matching impedance, high linearity and very low power consumption [7]. To make tradeoff between gain and linearity in LNA design optimization technique is used.
The source degenerated LNA is shown in Fig.1. Operating frequency is the resonance frequency, given by the L d drain node capacitance of M
2 with the design circuit because L d
1
. Proposed circuit is low power and node capacitance provide band pass filtering and the very small voltage drop across L because it is connected in series. M
3 d is in the current mirror
and used for biasing the LNA circuit and connection with M current flowing in cascade branch also determine by their ratio. Gate source voltage of M
1 selection of width of M
1
. M
1
is determined by proper
provides the cascode amplifier with an infinite input resistance. Another important advantage is that the cascode is able to reduce the effect of the gate to drain capacitance of M
1
, i.e. the Miller effect. This is because the input resistance of M resistance of M
1 to obtain the width of M
1
2
is usually much smaller than output
. R isolates the signal path from the current mirror. Power constrain noise optimization technique is used
[8].
W opt
 1 .
5 ( 
0
LC ox
R
S
Q in , opt
)  1
(1)
Here, calculated W opt is width of transistor M
1
. L, C ox
and Q are effective channel length of M
1
, oxide capacitance and circuit quality factor respectively. Value of L is 0.18 µm, ω
0
=
ISBN: 978-1-5090-1666-2/16/$31.00 ©2016 IEEE 1435

International Conference on Computing, Communication and Automation (ICCCA2016)
2π × 2.4 GHz, oxide capacitance calculated to be C fF/µm 2 , where t ox ox
= 9.45
specified by the foundry as 3.65 x 10 -9 m.
Source resistance R s
is typically 50 Ω and finally the optimum quality factor of the input circuit was estimated as 4 using the noise figure optimization method of fixed power dissipation for short channel device [5]. To give more freedom to match input impedance and reduce the value of inductor C introduced in the circuit. M
1
and M
2
transistor have equal width so that they can share drain area. Transistor M provide isolation between input and output.
2 ex
also
For input impedance matching parameter L model is used as shown in Fig. 2 [8]. g
and L s
are used.
For calculation of input impedance small signal equivalent
Fig. 2. The small signal equivalent model for calculation of input impedance
Design specifications are as follows:
TABLE I. S PECIFICATION FOR D ISIGN OF LNA
Parameter Specification
Supply Voltage
Gain (S
21
)
Noise Figure
1.8 V
> 20 dB
< 2.5 dB
Quality factor of input is given as
Q 
SC gs
( SL g

1
)
1
 SL s
( g m
 SC gs
)
(4)
SC gs
Therefore the gain of LNA is given by
V
V out in
 
1
At resonance,
  2 C gs
( g
L m g
SL d
 L s
)  SL s g m
(5)
R
And,
 in
2

( L g
R e

[ Z
L s in
] 
) C gs g
C
 m
L s gs
(6)
1 (7)
V out   g m
SL d  
L d
(8)
V in
SL s g m
L s
Thus, the ratio of the inductor at the drain to the inductor at the source is equal to gain. To obtain high gain the value of load inductor to be much bigger than the degeneration inductor. However, the large size of inductor will consume a lot of die area and a significant series resistance which may affect the noise and output performances of circuit. With the help of bias current flowing through LNA, width of transistor
M
3
is calculated.
With the help of single ended source degenerated LNA, we have designed a differential LNA and it’ s schemat is shown in
Fig. 3.
Input impedance (S
11
)
Output impedance (S
22
)
IIP3
<-20 dB
< -10 dB
> -10dBm
From Fig. 2 input impedance of circuit is given by
V in
 i in
( SL g

1
SC
Taking ratio between V in gs
) 
and i
( in g m v gs
 i in
) SL s
(2)
Z in
 S ( L g
 L s
)  (
1
SC gs
 g m
L s
C gs
) (3)
Fig. 3. Circuit diagram of the Differential LNA
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International Conference on Computing, Communication and Automation (ICCCA2016)
III.
S IMULATION R ESULTS
Spectre RF from cadence design suite are used in designing of this differential LNA. Length of channel is fixed at 180 nm and other parameters are find using parametric analysis, so that, we get operating frequency 2.4 GHz and other values better than given specification. For S-parameter analysis, connect port at input and output from analog library and use balun at differential output for impedance matching. Designed
LNA gives voltage gain 17.86 dB, power gain (S input return loss (S
11
21
) 21.59 dB,
) -47.24 dB, Output return loss (S dB, reverse isolation (S
12
22
) -1.59
) -40.84 dB and noise figure of 398.1 mdB, which is believed to be good as it exceeds the requirement, which is typically below 2 dB without having to trade-off the power gain, which also satisfies the requirement.
The obtained IIP3 is -0.611 dBm, which gives linearity of designed circuit. Table II shows the value of parameters calculated after parametric analysis.
Fig. 5. Plot of input return loss (S11)
TABLE II. D EVICE P ARAMETER V ALUES OF THE LNA
Parameters Values Parameter Values
R
1
=R
2
R
3
L
3
L
2
L
1
C
2
C
1
(W/L)
0
1K Ω
3KΩ
300pH
10nH
(W/L)
1
(W/L)
2
(W/L)
3
(W/L)
4
8nH
100fF
(W/L)
5
(W/L)
6
330fF (W/L)
7
85µm/0.18µm (W/L)
8
25µm/0.18µm
85µm/0.18µm
85µm/0.18µm
85µm/0.18µm
85µm/0.18µm
85µm/0.18µm
85µm/0.18µm
85µm/0.18µm
Fig. 4 to Fig. 10 shows S-parameter result of CMOS differential LNA.
Fig. 6. Plot of reverse isolation S12
Fig. 4. Plot of voltage gain
Fig. 7. Plot of Power gain S21
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International Conference on Computing, Communication and Automation (ICCCA2016)
Fig. 8. Plot of output return loss S22 Fig. 10. Plot of IIP3
Earlier, many authors have worked on the optimization of low noise amplifier. B. Dwivedi, and R. Khatri [9], G. Karimi,
S. B. Sedaghat, and R. Banitalebi [10], M. Khan, Y. Wang, and R. Raut [11], L. H. Lu, H. H. Hsieh, and Y. S. Wang [12],
G. Tulunay, and S. Balkır [13], F. Kalantari, N. Masoumi, and
A.R.Hoseini [14], D. J. Cassan, and J. R. Long [15], M.
Benmansour, and P. R. Mukund [16], P. Leroux, J. Janssens, and M. Steyaert [17], S. Toofan, A. R. Rahmati, A.
Abrishamifar, and G. R. Lahiji [18], W. K. Chong, H. Ramiah,
G. H. Tan, N. Vitee, and J. Kanesan [19], T. Sasilatha, and J.
Raja [20], V. Vidojkovic, J. van der Tang, E. Hanssen, A.
Leeuwenburgh, and A. van Roermund [21] etc. have worked for the optimization of LNA, but in this work noise figure is minimum from all of them.
Fig. 9. Plot of Noise Figure
[10]
[11]
[12]
[13]
TABLE III. P ERFORMANCE S UMMARY OF T HIS LNA C OMPARED TO O THER R EPORTED LNA S
Ref. Technology Frequency Voltage Gain S
21
S
11
S
22
S
12
Noise Figure IIP3 point
Unit _ (GHz) (dB) (dB) (dB) (dB) (dB) (dB) (dBm)
[9] 0.18µm 2.44 - 24.92 -23.64 -4.46 - 0.5 -8.83
[14]
[15]
0.18µm
0.18µm
0.18µm
0.35µm
0.18µm
0.18µm
2.45
1
2.4
0.9
5.25
5.75
-
-
-
-
28.5
-
19.36
24
10.1
13.03
-
14.1
< -20.88 < -1.416
-
-10.1
-12.07
-11.03
-
-
-10.5
-
-
-
-
-
-
-
-11.22
32
2.27
1.2
2.9
1.02
2.26
1.8
14
4.2
-
-29
4
-
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[16]
[17]
[18]
[19]
[20]
[21]
This
0.25µm
0.25µm
0.18µm
0.13µm
0.12µm
0.18µm
0.18µm
International Conference on Computing, Communication and Automation (ICCCA2016)
1.4 to 2 - 11.7 to 12.6 <-10 <-24 - 1.8 to 3.4 -3.16 to -4.8
1.2276
2.4
2.4
2.4
1.9 to 2.4
2.4
-
37.6
-
-
17/15
17.86
20
11.2
22.3
20
-
21.59
IV.
C ONCLUSION
Using the library UMC_18_CMOS for 0.18 µm technology in cadence a DLNA is designed. DLNA is working at 2.4 GHz frequency which is the standard frequency. Main aim of this paper was to reduce noise as much as possible without detoriating the other parameters. The noise figure of this circuit is 0.398 dB which is lesser than the noise figure of other reported LNAs operating at the 2.4 GHz frequency.
R EFERENCES
[1] B. Razavi, “ CMOS technology characterization for analog and RF design, ” IEEE Journal of Solid-Stuie Circuits, vol. 34, no. 3, pp.
268-276, 1999.
[2] H. Hashemi, and A. Hajimir i. “ Concurrent multiband low-noise amplifiers--th eory, design, and applications,” IEEE Transactions on Microwave Theory and techniques, vol. 50, no. 1, 288-301,
2002.
[3] A. Abidi, “ Direct-conversion radio transceivers for digital communications,” IEEE Journal of Solid-State Circuits, vol. 30, no. 12, 1399-1410, 1995.
[4] C. Kumar, S. Kumar, and A. K. Mal, “ An Efficient Two-Phase
NOC Generator for Low Frequency Applications,” IEEE
International Conference on Advanced Communication Control and Computing Technologies, 2014.
[5] T. H. Lee, The design of CMOS radio-frequency integrated circuits. Cambridge university press, 2004.
[6] D. K. Shaeffer , and T. H. Lee. “ A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 32, no.
5, pp. 745-759, 1997.
[7] Tran Thi Thu Nga, “ Ultra low-power low-noise amplifier designs for 2.4 GHz ISM band applications, ” A thesis submitted to the
Nanyang Technological University, July, 2012.
[8] Dhongde et al., “ Design 2.4 GHz 130nm CMOS Low Noise
Amplifier Design for Wireless Network, International Journal of
Computer Applications ” (0975 – 8887) Volume 88 – No.2,
February, 2014.
[9] N. M. Noh, and T. Z. A. Zulkifli, “ Design, Simulation and
Measurement Analysis on the S-parameters of an Inductivelydegenerated Common-source Open-drain Cascode Low Noise
Amplifier,” IEEE International Workshop on Radio-Frequency
Integration Technology : RFIT 007, 2007.
[10] M. Muhamad et al, “ Design of CMOS differential LNA at 2.4
GHz,” IEEE International Conference of Electron Devices and
Solid-State Circuits (EDSSC), 2013.
-11
<-11
-37.1
-
-16/-14
-47.24
-11.5
-
-
-
-
-1.59
-31
<-60
-
-
-
-40.84
0.8
2.15 to 2.7
7.2
3.9
2.25 to 2.2
0.398
-11
-6.5
-10.8
-
0.5 to 3
-0.611
[11] B. Dwivedi, and R. Khatri, “ A 2.4-GHz Differential Low-noise
Amplifiers using 0.18µm CMOS Technology, ” International
Journal of Electronic and Electrical Engineering, ISSN 0974-2174, vol. 7, no. 3, pp. 207-212, 2014.
[12] G. Karimi, S. B. Sedaghat, and R. Banitalebi , “ Designing and modeling of ultra low voltage and ultra low power LNA using
ANN and ANFIS for Bluetooth applications, ” Neurocomputing,
120, pp. 504 – 508, 2013.
[13] M. Khan, Y. Wang, and R. Raut, “ Noise Optimization Techniques for 1 V 1 GHz CMOS LowNoise Amplifiers Design,” WASET
Transactions On Engineering, Computing and Technology, vol. 2,
ISSN 1307-6884, 2004.
[14] L. H. Lu, H. H. Hsieh, and Y. S. Wang, “ A compact 2.4/5.2-GHz
CMOS dual-band low-noise amplifier, ” IEEE Microwave and
Wireless Components Letters, vol. 15, no. 10, pp. 685 – 687, 2005.
[15] G. Tulunay, and S. Balkır, “A compact optimization methodology for single-ended LNA, ” IEEE Proceeding of the International
Symposium on Circuits and Systems, pp. V273-276, 2004.
[16] F. Kalantari, N. Masoumi, and A.R.Hoseini, “ High Gain LNA
Design For WMAN Receiver and Optimization With Simulated
Annealing Algorithm, ” IEEE Proceeding of the International
Conference on Mixed Design of Integrated Circuits and systems, pp. 299-303, 2006.
[17] D. J. Cassan, and J. R. Long, “A 1 -V transformer-feedback lownoise amplifier for 5-GHz wireless LAN in 0.18 μm CMOS,”
IEEE Journal of Solid-State Circuit, vol. 38, no. 3, pp. 427-435,
2003.
[18] M. Benmansour, and P. R. Mukund, “ A tuned wideband LNA in
0.25 µm IBM process for RF communication applications, ” IEEE
Proceeding of 17 th International Conference on VLSI Design, pp.
631 – 634, 2004.
[19] P. Leroux, J. Janssens, and M. Steyaert, “A 0.8
-dB NF ESD-
Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver],” IEEE Journal of Solid -State Circuits, vol. 37, no. 6, pp.
760-765, 2002.
[20] S. Toofan, A. R. Rahmati, A. Abrishamifar, and G. R. Lahiji, “ A low-power and high-gain fully integrated CMOS LNA, ”
Microelectronics Journal, vol. 38, pp. 1150 – 1155, 2007.
[21] W. K. Chong, H. Ramiah, G. H. Tan, N. Vitee, and J. Kanesan,
“ Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application, ” International Journal of Electronics and Communications, vol. 68, no. 2, pp. 138-142, 2014.
[22] T. Sasilatha, and J. Raja, “ A 1 V, 2.4 GHz low power CMOS common source LNA for WSN applications, ” International Journal
Electronics and Communications, vol. 64, no. 10, pp. 940-946,
2010.
[23] V. Vidojkovic, J. van der Tang, E. Hanssen, A. Leeuwenburgh, and A. van Roermund, “ Fully-integrated DECT/Bluetooth multiband LNA in 0.18 μm CMOS,” IEEE Proceeding of International
Symposium on Circuits and Systems, vol. 1, pp. 565-568, 2004.
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