Section II
Dr. Laila Nassef
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The diagrams that show the R, I, and J format for MIPS machine
language instructions.
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Give as many examples as you can of MIPS assembly language instructions
that translate into single machine instructions.
MIPS instructions that translate into a single machine instruction are known
as TAL instructions.
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R-Format: arithmetic (add, addu), logical (and, or, slt, sltu), shifts
(sll, srl, sra), jump register (jr)
I-Format: arithmetic immediates (addi, addiu), logical immediates
(andi, ori, slti), loads/stores (lw, sw, lb, sb, lbu), branches (beq, bne)
J-Format: jumps (j, jal)
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translate the following instructions into corresponding machine instruction.
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addu $t0, $t1, $t2
000000 01001 01010 01000 00000 100000
addiu $t0, $t1, 8
010001 01001 01000 00000 00000 001000
jL
000010 xxxxxxxxxxxxxxxxxxxxxxxxxx
(jump target of L)
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What is the farthest distance a beq instruction can branch?
What is the range a j instruction can jump?
What is the range a jr instruction can jump?
beq:+215-1 or -215 instructions away from the next instruction (PC + 4).
j: any address that have the same four leftmost bits as the PC.
jr: anywhere – since a register holds a 32 bit value, it can hold a 32 bit address.
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Consider the branch: beq $t0, $0, really_far_away , Translate the instruction
so that the code jumps to really_far_away rather than branching to
really_far_away.
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bne $t0, $0, L
j really_far_away
L: ...
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Translate the branch instruction in previous slide so that the code is able to reach
the address really_far_away regardless of where really_far_away is in memory?
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bne $t0, $0, L
la $at, really_far_away
# note that $at should only be used by
# the assembler, not you!
jr $at
L: ...
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Can the following instruction be written as one machine instruction:
slti $8, $9, 0xfafff.
If not, then write out the shortest sequence of TAL instructions that could be
used in place of the instruction.
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lui $at, 0xf
ori $at, 0xafff
slt $8, $9, $at
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What is the difference between slt and sltu?
slt treats the immediate as signed (2's complement),
sltu treats the immediate as unsigned.
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For the following instructions, determine whether the immediate is
signed or unsigned:
addiu, lw/sw, ori, beq.
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Signed Immediate: addiu, lw/sw, beq
Unsigned Immediate: ori
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What is the largest and smallest immediate that can be represented in a
non-psuedo addiu instruction.
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215-1, -215
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Assemble the following assembly language instruction into a
machine language instruction using hexadecimal representation:
sltu $2, $3, $12
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Assemble the following assembly language instruction into a
machine language instruction, using hexadecimal
representation: slt $2, $3, 12
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Show how the following pseudoinstruction is translated into
machine instructions.
beq $s0, 45, loop1
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Decode the instructions
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0x02114824
and $9, $16, $17  and $t1, $s0, $s1
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Decode the instructions
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0x03E00008
jr $31  jr $ra
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Decode the instructions
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0x292A0020
slti $10, $9, 32  slti $t2, $t1, 32
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Convert the following machine language instruction,
represented as a hexadecimal value, into an assembly
language instruction: 28620016
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Test overflow
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Unsigned addition.
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Write a sequence of MIPS assembly code that
will detect overflow for unsigned addition.
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Signed addition
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Signed subtraction
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Write a sequence of MIPS assembly code that
will detect overflow for signed subtraction.
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Unsigned subtraction.
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Write a sequence of MIPS assembly code that
will detect overflow for unsigned subtraction.
Hint: overflow occurs when the operation’s
result falls outside the valid range.
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Translate each of the following C-code snippets into MIPS assembly. Use up to
eight instructions for each segment, but limit the instructions used to those listed in
the table below.
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Translate the assembly code in the previous question into machine code
(binary) knowing that the opcodes for add, addi, lw, sw, and bne are 0, 8,
35, 43, and 5 respectively and that the function code for add is 32.
It is enough to translate one instruction for each opcode (e.g., there is no
need to translate all 5 addi instructions, one addi instruction is enough)
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Write a snippet of MIPS code that reverses the bit sequence stored in register
$s0.
You may use the following algorithm (substitute symbolic registers with
actual registers):
1) set register A to 0 (used as counter)
2) set register B to 0 (used as result)
3) right-shift $s0 by A bits, put result into temporary register C
4) left-shift C by 31 bits
5) right-shift C by A bits
6) perform a bit-wise OR between register B and C, put result in B
7) increment A
8) if A < 32, go to line 3
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li $t0,0
li $t1,0
loop: srlv $t2,$s0,$t0
sll
$t2,$t2,31
srlv $t2,$t2,$t0
or
$t1,$t1,$t2
addi $t0,$t0,1
blt
$t0,32,loop
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Convert the following sequence of machine instructions,
represented as hexadecimal values, into assembly language.
 3c010010
 34300001
 01105006
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lui $1,16
ori $16,$1,1
srlv $10, $16, $8
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For each of the following pseudo-instructions, produce a minimal sequence of real
MIPS instructions to accomplish the same thing.
You may use the $at register only as a temporary register.
A) abs $s1, $s2
addu $s1, $zero, $s2
bgez $s2, next
subu $s1, $zero, $s2
next:
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b) addiu $s1, $s2, imm32
# imm32 is a 32-bit immediate
lui $at, upper16
ori $at, $at, lower16
addu $s1, $s2, $at
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c) bleu $s1, $s2, Label
# branch less than or equal unsigned
sltu $at, $s2, $s1
beq $at, $zero, Label
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d) bge $s1, imm32, Label
# imm32 is a 32-bit immediate
lui $at, upper16
ori $at, $at, lower16
slt $at, $s1, $at
beq $at, $zero, Label
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e) rol $s1, $s2, 5
# rol = rotate left $s2 by 5 bits
srl $at, $s2, 27
sll $s1, $s2, 5
or $s1, $s1, $at
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For each pseudo-instruction in the following table, produce a minimal sequence of
actual MIPS instructions to accomplish the same thing. You may use the $at for
some of the sequences. In the following table, imm32 refers to a 32-bit constant.
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Translate the following statements into MIPS assembly language.
Assume that a, b, c, and d are allocated in $s0, $s1, $s2, and $s3.
All values are signed 32-bit integers.
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||  OR i.e., If first expression is true, second
expression is skipped
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&&  (AND) i.e., if first expression is false,
second expression is skipped
a, b, c, and d are allocated in $s0, $s1, $s2, and $s3
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Translate the following if-else statement into assembly language:
if (($t0 >= '0') && ($t0 <= '9')) {$t1 = $t0 – '0';}
else if (($t0 >= 'A') && ($t0 <= 'F')) {$t1 = $t0+10-'A';}
else if (($t0 >= 'a') && ($t0 <= 'f')) {$t1 = $t0+10-'a';}
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blt $t0, '0', else1
bgt $t0, '9', else1
addiu $t1, $t0, -48 # '0' = 48
j next
else1:
blt $t0, 'A', else2
bgt $t0, 'F', else2
addiu $t1, $t0, -55 # 10-'A' = 10-65=-55
j next
else2:
blt $t0, 'a', next
bgt $t0, 'f', next
addiu $t1, $t0, -87 # 10-'a' = 10-97=-87
next:
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Consider the following fragment of C code:
for (i=0; i<=100; i=i+1) { a[i] = b[i] + c; }
Assume that a and b are arrays of words and the base address of a is in $a0 and
the base address of b is in $a1. Register $t0 is associated with variable i and
register $s0 with c. Write the code in MIPS.
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Add comments to the following MIPS code and describe in one sentence what it
computes.
Assume that $a0 is used for the input and initially contains n, a positive integer.
Assume that $v0 is used for the output.
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What is the corresponding MIPS assembly code for each of
the following C statements?
How many MIPS instructions are needed in each case? Assume
that the variables f, g, h, i and j are available 32-bit integers.
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The number of MIPS instructions is: 5
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The number of MIPS instructions is: 2
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What is the corresponding C statement for each
of the following MIPS code?
Assume that the variables f, g and h are available
32-bit integers.
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What is the corresponding MIPS assembly code for each of the
following C statements?
How many MIPS instructions and how many registers are
needed in each case?
Assume that the variables f, g and h are assigned to registers
$s0, $s1, and $s2 respectively and the base address of arrays A
and B are in registers $s6 and $s7.
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Questions?
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