Analog VLSI assignment
Question no. 68
Parth Samnani (2017A3PS0298P)
Vishesh Arora (2017A3PS0299P)
Aryamick Singh (2017A3PS0389P)
PROBLEM STATEMENT:
Que68. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common gate
stage] + gain stage).
a) Analog schematic for OTA.
b) Analysis of all equations for OTA, with a systematic derivation of all transistors W/L ratios and spectre
simulation of circuit for the following specifications.
i) Gain ≥ 80 dB
ii) Phase margin ≈ 600
iii) Power dissipation ≤ 0.5mA
c) Show the biasing circuitry to bias all the voltages in your design (except the input).
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and phase,
ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power consumption, and input and
output offset voltage.
INTRODUCTION:
The problem statement required us to design a two-stage fully differential (folded cascode) operational
transconductance amplifier. All MOSFETs (M1 – M25) are required to work in saturation region inorder to
meet the required design specifications.
DESIGN:
For deciding the W/L of all the MOSFETs and other design parameters, we assumed the gain of the second
stage of the OpAmp to be nearly 30 dB and the gain of the first stage to be nearly 50 dB and started designing
our circuit from the second stage. The second stage needed an input of 1.165 V (approx.) to give the desired
gain. So, we chose W/L of all the MOSFETs and did our current budgeting in such a way that the output of our
first stage (which is connected to our stage 2 input) comes out to be 1.165 V, and the gain of the second stage of
the circuit is 30 dB. Now, to improve upon the gain of our first stage, we did a parametric sweep on all the
W/Ls and found out the best combination for which our gain is nearly 50 dB. We were able to achieve a gain of
almost 49 dB from our first stage and a gain of nearly 29 dB from our second stage. Our DC gain is 77.93 dB.
We followed a similar procedure for finding out the bias voltages. We found out approximate values based on
calculations and then did a parametric sweep to find the nest possible combination for which our gain remains
near the required design specification.
To design our reference circuitry, we used a simple diode connected PMOS connected with a diode connected
NMOS in series and were able to generate the required bias voltage at the common drain node of the circuit.
After finding out rough estimates, we did a parametric sweep on the W/L of the PMOS to generate the exact
bias voltages.
RESULTS:
MOSFET
M1
M2,3
M4-7,19
M8,9
M10,11
M12,13,17,21,23,25
M14,15
M16
M18
M20
M22
M24
W(um)
13.7
5
3.5
1.825
3.95
0.35
1.95
1.3476
0.6318
3.008
9.85
18.87
DC Gain
ICMR
Slew Rate
Differential Output Swing
Power Consumption
Input DC Offset
Output DC Offset
Output Capacitance
Phase Margin
L(um)
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
77.93 dB
.241 – 1.43 V
71.98 kV/s
4.2 V
2.24 mW
7.54 pV
-163.43 uV
900 pF
59.6 deg
W/L
39.143
14.286
10
5.214
11.286
1
5.571
3.850
1.805
8.594
28.143
53.914
PLOTS:
1. AC Gain and Phase:
The DC gain is 77.93 dB which (almost) meets the design requirements. Phase margin achieved is 59.6
degrees which meets the design requirements.
2. ICMR Plot:
ICMR = 1.43 – .241 = 1.189 V
3. Slew Rate:
The inverting input of the circuit is connected to the output and a step signal is provided as input. Slew rate
of 71.98 kV/s is achieved.
4. Power consumption:
Vdd * Itotal = 2.5 V * 897 µA = 2.24 mW
5. Output Voltage Swing differential (DC + transient):
This is the input corresponding to which we’ve found the output voltage swing differential.
Differential output swing = -2.1 to 2.1 = 4.2 V
6. Output DC offset voltage:
Output DC offset = -163.43 uV
7. Input DC offset voltage:
Input DC offset = 7.54 pV