Lecture 11 Process Integration Lecture 11: Process Integration “Where we are today” Device Integration Wafer Fabrication Simulation & Modeling Metrology FEOL Processes Electrical Testing BEOL Fabrication Packaging PS: This list of co-dependencies is not complete! Future Technologies IH2655 Spring 2012 Process Integration: Overview • Lithography Laser (Steppers), EUV, E-Beam, … Pattern • Thin Film deposition CVD – LPCVD, PECVD, ALD … PVD – Sputtering (DC, RF, …), Evaporation (Resistance, E-Beam), … Epitaxy – CVD, MBE, SPE Spin-coating Inkjet Printing • Etching Wet etching Dry etching • Doping Ion implantation Diffusion • Surface engineering Thermal oxidation Metal silicide（SALICIDE） Christoph Henkel / Mikael Östling KTH 3 IH2655 Spring 2012 Process Integration - Overview • Isolation Technology • LOCOS • STI • Gate Stack Options • Advanced CMOS Integration Christoph Henkel / Mikael Östling KTH 4 IH2655 Spring 2012 MOS-Basic Isolation in Ics MOS transistors are self-isolated. Compared to bipolar devices, MOSFETs may have higher density, but they will suffer from parasitic effects from the adjacent devices. High threshold voltage at the field region VTF is preferred. VTF must be 3-4 V higher (depending on CMOS generation) than the supply voltage to ensure that the current from parasitic MOSFET is less than 1 pA. VTF decreases with decreasing device distance or increasing temperature T. When T increases from 25 oC to 125 oC, VTF will decrease by 2 V. VT VFB 2MS 2 s qN A (2MS ) Cox Methods to Increase Field Threshold Voltage VTF Increase field oxide to be 7~10 times thicker than gate oxide Increase the doping concentration under field oxide (Channelstop implantation) Christoph Henkel / Mikael Östling KTH 5 IH2655 Spring 2012 LOCOS Isolation Technology (40nm) (80nm) 50 keV，1×1013 cm-2 Christoph Henkel / Mikael Östling KTH 6 IH2655 Spring 2012 Problems in LOCOS Technology 2) Rough Surface — limits Lithography (DOF) 1) Bird’s Beak Effect — limits integration improvement Christoph Henkel / Mikael Östling KTH 7 IH2655 Spring 2012 Improved LOCOS — PBL (Poly-Buffered LOCOS) Deposit a layer of polysilicon before LPCVD Si3N4. Polysilicon consumes the oxygen diffused laterally during field oxidation. The bird’s beak can reduce to 0.1-0.2 mm. Christoph Henkel / Mikael Östling KTH 8 IH2655 Spring 2012 Improved LOCOS — PBL (Poly-Buffered LOCOS) Helpful to integration improvement Christoph Henkel / Mikael Östling KTH 9 IH2655 Spring 2012 Shallow Trench Isolation (STI) 1/5 LOCOS, PBL applicable for technology node0.35-0.5 mm. For technology node <0.35 mm, STI must be used. 1) Wafer Cleaning 2) Substrate Oxidation (20 nm) Christoph Henkel / Mikael Östling KTH 10 IH2655 Spring 2012 Shallow Trench Isolation (STI) 2/5 3) LPCVD Si3N4 (100 nm) 4) Isolation Lithography 5) Shallow Trench Etching (0.5 mm) Christoph Henkel / Mikael Östling KTH 11 IH2655 Spring 2012 Shallow Trench Isolation (STI) 3/5 6) Thermal Growth of Oxide Stop (20 nm) 7) Channel Stop Implantation 8) Trench Filling by CVD Oxide Christoph Henkel / Mikael Östling KTH 12 IH2655 Spring 2012 Shallow Trench Isolation (STI) 4/5 9) Etching-back Planarization 10) Si3N4 Etching Christoph Henkel / Mikael Östling KTH 13 IH2655 Spring 2012 Shallow Trench Isolation (STI) 5/5 11) Re-Etching-back Planarization 12) Densification Annealing of CVD Oxide Christoph Henkel / Mikael Östling KTH 14 IH2655 Spring 2012 Modern STI Technology (CMOS) 1/2 1) No Channel Stop Implantation USG (Un-doped Silicate Glass): SiH4+O2+Ar→USG + volatiles 2) HDPCVD: No Densification Annealing Christoph Henkel / Mikael Östling KTH 15 IH2655 Spring 2012 Modern STI Technology (CMOS) 2/2 3) CMP Planarization 4) Si3N4 Etchingback and USG Christoph Henkel / Mikael Östling KTH 16 IH2655 Spring 2012 Process Integration - Overview • Isolation Technology • Gate Stack Options • Self Aligned Structures • Replacement Gate Technology • Fully Silicided Gates • Advanced CMOS Integration Christoph Henkel / Mikael Östling KTH 17 IH2655 Spring 2012 Gate Structure Early gate structure is SiO2－Metal Gate (Al Gate). With increased integration, low VT is required. VT VFB 2F 2 s qNA ( 2F ) Cox ND ; F VT ln ni Moreover, Al is incompatible to high-temperature Poly-Gate process, such as ion implantation annealing. (Interconnect) Al gate not feasible when reducing source-drain series resistance is required. Using poly-gate, VT can decrease by 1.2~1.4 V Other Advantages of Poly-Gate: MS can be changed by doping. For example, n-poly may reduce VT by 1.1 V, i.e., the dual-poly (n & p) technology commonly used in industry. Poly-Gate self-alignment technology can further improve integration. Christoph Henkel / Mikael Östling KTH 18 IH2655 Spring 2012 Poly-Gate Self-Alignment Technology “Hot” electron effects are considerable in small devices !! Christoph Henkel / Mikael Östling KTH Lighly Doped Drain (LDD) + Spacer 19 IH2655 Spring 2012 LDD + Spacer Polysilicon Self-Alignment 1) LDD Implant 2) Sidewall Formation Christoph Henkel / Mikael Östling KTH 20 IH2655 Spring 2012 LDD + Spacer Polysilicon Self-Alignment 3) Ion Implantation +Annealing Self-Aligned Ion Implantation SALICIDE Self-Aligned Silicide Maximize contact area, reduce contact resistance and make contacts much closer to the channel (see also Lecture 9) TiSi2，CoSi2，NiSi Christoph Henkel / Mikael Östling KTH 21 IH2655 Spring 2012 High k/Metal Gate: Replacement of Poly-Gate Problem: High-k / Metal Gate stacks are not compatible with CMOS FEOL temperature requirements. 1) LDD and Sidewall Si3N4 2) LPCVD Si3N4 + CVD PSG + CMP Christoph Henkel / Mikael Östling KTH 22 IH2655 Spring 2012 High k/Metal Gate: Replacement of Poly-Gate 3) Si3N4 Etching 4) Poly-Si Etching 5) Oxide Etching Christoph Henkel / Mikael Östling KTH 23 IH2655 Spring 2012 High k/Metal Gate: Replacement of Poly-Gate Hf-based High k 6) High-k Deposition Today: Hafniumbased; ALD process 7) Metal Gate 8) CMP Hf-based Christoph Henkel / Mikael Östling KTH 24 IH2655 Spring 2012 Fully-Silicided (FUSI) Gate Metal silicide directly on gate oxide without poly-Si in-between Example: nickel silicide (1 nm Ni + 1.84 nm Si 2.2 nm NiSi) Gottlob et al., “0.86-nm CET Gate Stacks With Epitaxial Gd2O3 High-k Dielectrics and FUSI NiSi Metal Electrodes”, IEEE El. Dev. Lett., 27(10), 2006. Gottlob et al., “Gentle FUSI NiSi metal gate process for high-k dielectric screening”, Microelectronic Engineering 85 (2008) 2019–2021 Christoph Henkel / Mikael Östling KTH 25 IH2655 Spring 2012 Process Integration - Overview • Isolation Technology • Gate Stack Options • Advanced CMOS Integration • Full SOI CMOS Process • Flip Chip Packaging • Current Technology Christoph Henkel / Mikael Östling KTH 26 IH2655 Spring 2012 Modern SOI CMOS Integration Technology Example: SOI + Five-level Cu Interconnect Next Slides 21 mask process Christoph Henkel / Mikael Östling KTH 27 IH2655 Spring 2012 CMOS Integration Christoph Henkel / Mikael Östling KTH 28 IH2655 Spring 2012 SIMOX = Separation by Ion Implantation of Oxygen Christoph Henkel / Mikael Östling KTH 29 IH2655 Spring 2012 & Wafer cleaning Christoph Henkel / Mikael Östling KTH 30 IH2655 Spring 2012 & Wafer cleaning Christoph Henkel / Mikael Östling KTH 31 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 32 IH2655 Spring 2012 & alignment, exposure, PEB, development and inspection mask0 Etch oxide & Si as alignment marks Christoph Henkel / Mikael Östling KTH 33 IH2655 Spring 2012 Strip PR and Screen Oxide Wafer cleaning Christoph Henkel / Mikael Östling KTH 34 IH2655 Spring 2012 Pad thermal oxidation LPCVD Nitride Christoph Henkel / Mikael Östling KTH 35 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 36 IH2655 Spring 2012 PR coating and pre-baking mask1 Christoph Henkel / Mikael Östling KTH 37 IH2655 Spring 2012 PEB, development & inspection Etch pad oxide and nitride Christoph Henkel / Mikael Östling KTH 38 IH2655 Spring 2012 Strip PR & etch Si Christoph Henkel / Mikael Östling KTH 39 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 40 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 41 IH2655 Spring 2012 Strip nitride & oxide Wafer cleaning Christoph Henkel / Mikael Östling KTH 42 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 43 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 44 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask2 Christoph Henkel / Mikael Östling KTH 45 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 46 IH2655 Spring 2012 2 S qNA (2F ) 2QI Vth VFB 2F COx COx QI ion implantation dose (typical dose 1011-1012) Christoph Henkel / Mikael Östling KTH 47 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 48 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 49 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask3 Christoph Henkel / Mikael Östling KTH 50 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 51 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 52 IH2655 Spring 2012 Strip PR & sacrificial oxide Wafer cleaning Christoph Henkel / Mikael Östling KTH 53 IH2655 Spring 2012 Group Activity 1 How to get from A to B? A ? B Christoph Henkel / Mikael Östling KTH 54 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 55 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 56 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 57 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection a-Si etching Christoph Henkel / Mikael Östling mask4 KTH 58 IH2655 Spring 2012 Strip PR, wafer cleaning, a-Si annealing and oxidation oxide Christoph Henkel / Mikael Östling KTH 59 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 60 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask5 Christoph Henkel / Mikael Östling KTH 61 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 62 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 63 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 64 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask6 Christoph Henkel / Mikael Östling KTH 65 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 66 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 67 IH2655 Spring 2012 Group Activity 2 How to get from B to C? B ? C Christoph Henkel / Mikael Östling KTH 68 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 69 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 70 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 71 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask7 Christoph Henkel / Mikael Östling KTH 72 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 73 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 74 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 75 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask8 Christoph Henkel / Mikael Östling KTH 76 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 77 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 78 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 79 IH2655 Spring 2012 Ar Sputtering etching (SiO2 and Cleaning) Co and TiN Sputtering Deposition Christoph Henkel / Mikael Östling KTH 80 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 81 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 82 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 83 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 84 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 85 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 86 IH2655 Spring 2012 PR coating and pre-baking, mask alignment & exposure, PEB, development and inspection mask9 Christoph Henkel / Mikael Östling KTH 87 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 88 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 89 IH2655 Spring 2012 Ar sputtering etching Ti and TiN Sputtering Deposition Christoph Henkel / Mikael Östling KTH 90 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 91 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 92 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 93 IH2655 Spring 2012 Ar Sputtering etching Ta and TaN Barrier Layer PVD Christoph Henkel / Mikael Östling KTH 94 IH2655 Spring 2012 Bulk Cu ECP & annealing Christoph Henkel / Mikael Östling KTH 95 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 96 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 97 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 98 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 99 IH2655 Spring 2012 Mask 16、17 Christoph Henkel / Mikael Östling KTH 100 IH2655 Spring 2012 Mask 18、19 Christoph Henkel / Mikael Östling KTH 101 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 102 IH2655 Spring 2012 Mask 20 Christoph Henkel / Mikael Östling KTH 103 IH2655 Spring 2012 & ship to testing Christoph Henkel / Mikael Östling KTH 104 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 105 IH2655 Spring 2012 Ar sputtering etching Cr, Cu, and Au Liner Coating Christoph Henkel / Mikael Östling KTH 106 IH2655 Spring 2012 Mask 21 Christoph Henkel / Mikael Östling KTH 107 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 108 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH 109 IH2655 Spring 2012 Process Integration - Overview • Isolation Technology • Gate Stack Options • Advanced CMOS Integration • Full SOI CMOS Process • Flip Chip Packaging • Current Technology Christoph Henkel / Mikael Östling KTH 110 IH2655 Spring 2012 Flip Chip Packaging Dicing, Packaging: e.g., Flip-chip packaging Through Silicon Via (TSV) Christoph Henkel / Mikael Östling KTH 111 IH2655 Spring 2012 Process Integration - Overview • Isolation Technology • Gate Stack Options • Advanced CMOS Integration • Full SOI CMOS Process • Flip Chip Packaging • Current Technology Christoph Henkel / Mikael Östling KTH 112 IH2655 Spring 2012 On-Time 2 Year Cycles 130 nm 2001 90 nm 2003 65 nm 2005 45 nm 2007 32 nm 2009 High-k 2nd Generation Christoph Henkel / Mikael Östling KTH 113 IH2655 Spring 2012 Taken from: Masaaki Niwa, “Development of 32nm CMOS and Recent Trend for Beyond 32nm” SMT Symp. 2011 Christoph Henkel / Mikael Östling KTH 114 IH2655 Spring 2012 Taken from: Masaaki Niwa, “Development of 32nm CMOS and Recent Trend for Beyond 32nm” SMT Symp. 2011 Christoph Henkel / Mikael Östling KTH 115 IH2655 Spring 2012 Taken from: Kelin Kuhn, “Moore's Law past 32nm: Future Challenges in Device Scaling” SSDM. 2009 Christoph Henkel / Mikael Östling KTH 116 IH2655 Spring 2012 Christoph Henkel / Mikael Östling KTH Taken from: Masaaki Niwa, “Development of 32nm CMOS and Recent Trend for Beyond 32nm” SMT Symp. 2011 117 IH2655 Spring 2012 IBM Cu Technology To interconnect the extremely small transistors, a complex multilevel multi-layer metallization scheme is needed. Shown below is what IBM has done with their state-of-the-art Cu technology. Cu W-stud Six Cu metallization levels above the 1st metal level with tungsten studs to the transistors http://www-3.ibm.com/chips/gallery/p-n2.html Christoph Henkel / Mikael Östling KTH 118
