Problem Set 7 Solutions The opcode tells us that the instruction is: “And the register contents of Reg9 and Reg4 and store the result in Reg8”. In the following figure, the values of all the wires in the MIPS datapath are shown at the end of the clock cycle in which the And instruction has been executed. (Assumption: The Program counter is at a value of PC1 when the above instruction was fetched). Critical Path: IMem Regs Mux ALU Mux Regs Time taken: 400ps + 200ps + 30ps + 120ps + 30ps + 200ps = 980ps Critical Path: IMem Regs ALU DMem Mux Regs Time taken: 400ps + 200ps + 120ps + 350ps + 30ps + 200ps = 1300ps Critical Path: IMem Regs Mux ALU Mux Regs (PC) Time taken: 400ps + 200ps + 30ps + 120ps + 30ps + 200ps = 980ps The clock cycle time of the processor must accommodate the time taken for the longest critical path of any instruction. Hence the clock cycle time for this processor is 1300ps. The load instruction’s critical path takes the longest time to traverse and hence determines the clock cycle time of the processor. Since the adder does not fall in this critical path, reducing its latency will not reduce the clock cycle time of the processor. The clock cycle time of the new version is also 1300ps.