Practical 1
Date: 3ed Jan.
Aim: To Study about Microwind tool and λ (Lambda) Rules for Layout Generation.
Objective:
1. To be familiar with tool.
2. To learn about λ (Lambda) Rules for 90 nm Technology.
Microwind Getting Started:
The present experiment is a guide to using the « Microwind » educational software on a PC
computer.
The MICROWIND program allows the student to design and simulate an integrated circuit. The
package itself contains a library of common logic and analog ICs to view and simulate.
MICROWIND includes all the commands for a mask editor as well as new original tools never
gathered before in a single module. You can gain access to Circuit Simulation by pressing one
single key. The electric extraction of your circuit is automatically performed and the analog
simulator produces voltage and current curves immediately.
A specific command displays the characteristics of pMOS and nMOS, where the size of the
device and the process parameters can be very easily changed. Altering the MOS model
parameters and, then, seeing the effects on the Vds and Ids curves constitutes a good interactive
tutorial on devices.
The Process Simulator shows the layout in a vertical perspective, as when fabrication has been
completed. This feature is a significant aid to supplement the descriptions of fabrication found in
most textbooks.
The Logic Cell Compiler is a particularly sophisticated tool enabling the automatic design of a
CMOS circuit corresponding to your logic description in VERILOG. The DSCH software, which
is a user-friendly schematic editor and a logic simulator presented in a companion manual, is
used to generate this Verilog description. The cell is created in compliance with the environment,
design rules and fabrication specifications.
A set of CMOS processes ranging from 1.2µm down to state-of-the-art 0.25µm are proposed.
To use the MICROWIND program use the following procedure:

Go to the directory in which the software has been copied
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(The default directory is MICROWIND)

Double-click on the MicroWind icon
The MICROWIND display window is shown in Figure 1. It includes four main windows: the
main menu, the layout display window, the icon menu and the layer palette. The cursor appears
in the middle of the layout window and is controlled by using the mouse.
The layout window features a grid that represents the current scale of the drawing, scaled in
lambda () units and in micron.
The lambda unit is fixed to half of the minimum available lithography of the technology. The
default technology is a 0.8 µm technology, consequently lambda is 0.4 µm.
Fig. 1. The MICROWIND window as it appears at the initialization stage..
The MOS device
The MOS symbols are reported below. The n-channel MOS is built using polysilicon as the gate
material and N+ diffusion to build the source and drain. The p-channel MOS is built using
polysilicon as the gate material and P+ diffusion to build the source and drain.
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nMOS
pMOS
Manual Design
By using the following procedure, you can create a manual design of the n-channel MOS. The
default icon is the drawing icon shown above. It permits box editing. The display window is
empty. The palette is located in the lower right corner of the screen. A red color indicates the
current layer. Initially the selected layer in the palette is polysilicon. The two first steps are
illustrated in Figure 2.

Fix the first corner of the box with the mouse.

While keeping the mouse button pressed, move the mouse to the
opposite corner of the box.

Release the button. This creates a box in polysilicon layer as shown in Figure 2.
The box width should not be inferior to 2 , which is the minimum width of the
polysilicon box.
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Fig. 2. Creating a polysilicon box.
Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button.
Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of
the drawing as in Figure 3. N-diffusion boxes are represented in green. The intersection between
diffusion and polysilicon creates the channel of the nMOS device.
Fig. 3. Creating the N-channel MOS transistor
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Process Simulation
Click on this icon to access process simulation. The cross-section is given by a click of the
mouse at the first point and the release of the mouse at the second point. In the example below
(Figure 4), three nodes appear in the cross-section of the n-channel MOS device: the gate (red),
the left diffusion called source (green) and the right diffusion called drain (green), over a
substrate (gray). The gate is isolated by a thin oxide called the gate oxide. Various steps of
oxidation have lead to a thick oxide on the top of the gate.
Fig. 4. The cross-section of the nMOS devices.
The physical properties of the source and of the drain are exactly the same. Theoretically, the
source is the origin of channel impurities. In the case of this nMOS device, the channel
impurities are the electrons. Therefore, the source is the diffusion area with the lowest voltage.
The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and
the drain. The gate controls the current flow from the drain to the source, both ways. A high
voltage on the gate attracts electrons below the gate, creates an electron channel and enables
current to flow. A low voltage disables the channel.
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Mos Characteristics
Click on the MOS characteristics icon. The screen shown in Figure 5 appears. It represents the
Id/Vd simulation of the nMOS device.
Fig. 5. N-Channel MOS characteristics.
The MOS size (width and length of the channel situated at the intersection of the polysilicon gate
and the diffusion) has a strong influence on the value of the current. In Figure 5, the MOS width
is 12.8µm and the length is 1.2µm. Click on OK to return to the editor. A high gate voltage (Vg
=5.0) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. The maximum current
is obtained for Vg=5.0V, Vd=5.0V, with Vs=0.0.
The MOS parameters correspond to SPICE Level 3. You can alter the value of the parameters, or
even access to Level 1. You may also skip to PMOS. You may as well add some measurements
to fit the simulation. Finally, you can simulate devices with other sizes in the proposed list.
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Add Properties for Simulation
Properties must be added to the layout to activate the MOS device. The most convenient way to
operate the MOS is to apply a clock to the gate, another to the source and to observe the drain.
The summary of available properties is reported below.
VDD property
Node visible
VSS property
Clock property
Pulse property

Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock
menu appears (See below). Change the name into « drain » and click on OK. A default clock
with 3 ns period is generated. The Clock property is sent to the node and appears at the right
hand side of the desired location with the name « drain ».
Fig. 6. The clock menu.

Apply a clock to the gate. Click on the Clock icon and then, click on
the polysilicon gate. The clock menu appears again.
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Change the name into « gate» and click on OK to apply a clock with 6 ns period.

Watch the output: Click on the Visible icon and then, click on the right diffusion.
The window below appears. Click OK. The Visible property is then sent
to the node. The associated text « s1 » is in italic. The wave form of this node
will appear at the next simulation.
Fig. 7. The visible node menu.
Save before Simulation
Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window
appears, into which you enter the design name. Type, for example, myMos. Use the keyboard for
this and press . Then click on OK. After a confirmation question, the design is saved under that
filename.
IMPORTANT : Always save BEFORE any simulation !
Analog Simulation
Click on Simulate on the main menu. The timing diagrams of the inverter appear, as shown in
Figure 8.
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Fig. 8. Analog simulation of the MOS device.
When the gate is at zero, no channel exists so the node s1 is disconnected from the drain. When
the gate is on, the source copies the drain. It can be observed that the nMOS device drives well at
zero but at the high voltage. The final value is 4.2V, that is VDD minus the threshold voltage.
Click on More in order to perform more simulations. Click on Stop to return to the editor.
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λ (Lambda) Rule:
Design Rules
The software can handle various technologies. The process parameters are stored in files with the
appendix '.RUL'. The default technology corresponds to the ATMEL-ES2 2-metal 0.8µm CMOS process.
The default file is ES208.RUL.
To select a foundry, click on File -> Select Foundry and choose the appropriate technology in the list.
N-Well
r101
r102
nwell
nwell
p substrate
r101
r102
Minimum well size : 12 
Between wells : 12 
Diffusion
r201
r202
r203
r204
r203
Minimum diffusion size : 4 
Between two diffusions : 4 
Extra well after diffusion : 6 
Between diffusion and well : 6 
P+ diff
r201
r202
P+ diff
nwell
r204
N+ diff
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Polysilicon
r301
r302
r303
r304
r305
r306
r307
Polysilicon width : 2 
Polysilicon gate on diff n+ : 2 
Polysilicon gate on diff p+ : 2 
Between two polysilicons : 3 
Poly v.s other diff diffusion : 2 
Diffusion after polysilicon : 4 
Extension of Poly after diff : 3 
r305
P+diff
r306
r302
r301
nwell
r304
r306
N+diff
r307
Contact
r401
r402
r403
r404
r405
Contact width : 2 
Between two contacts : 3 
Extra metal over contact:1 
Extra poly over contact: 2 
Extra diff over contact: 1 
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r403
r402
metal
r401
contact
r405
r404
N+diff
poly
Metal 1
r501
r502
Metal width : 3 
Between two metals : 3 
r501
metal
r502
metal
Via
r601
r602
r603
r604
r605
Via width : 3 
Between two Via: 3 
Between Via and contact: 3 
Extra metal over via: 2 
Extra metal 2 over via: 2 
r604
r602
via
metal2
r601
r603
contact
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Metal 2
Metal width: 5 
Between two metal2 : 5 
r701
r702
r701
metal2
r702
metal2
Via 2
r801
r802
r803
r804
Via2 width : 3 
Between two Via2s: 4 
Between Via2 and via : 4 
Extra metal2 & metal 3 over via2: 3 
Metal 3
r901
r902
Metal3 width: 6 
Between two metal3s : 5 
Via 3
ra01
ra02
ra03
ra04
Via3 width : 4 
Between two Via3s : 6 
Between Via3 and via2 : 6 
Extra metal4 and metal3 over via3: 6 
Metal 4
rb01
rb02
Metal4 width: 10 
Between two metal4s: 22 
Via 4
rc01
rc02
rc03
Via4 width : 4 
Between two Via4s : 6 
Between Via4 and Via3 : 6 
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Extra metal4 & metal 5 over via4: 6 
rc04
rc04
rc02
via4
rc01
metal5 & metal4
rc03
Via3
Metal 5
rd01
rd02
Metal 5 width: 10 
Between two metal5s : 4 
rd01
metal 5
rd02
metal 5
Pads
rp01
rp02
rp03
rp04
rp05
Pad width: 100 µm (lambda conversion depending on the technology)
Between two pads 100 µm
Opening in passivation v.s via : 5µm
Opening in passivation v.s metals: 5µm
Between pad and unrelated active area : 20 µm
rp03
PAD
rp02
rp01
Conclusion:
By performing this experiment we understand the basics of Microwind tool and
study the different design rules in 90nm technology.
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Practical 2
Date:10th Jan.
Aim: To generate layout for CMOS Inverter circuit and simulate it for verification..
Objective:
1. To simulate CMOS inverter and obtain VTC
2. To Prepare the Layout of Horizontal Inverter.
3. Measure propagation delay.
Theory: The inverter circuit uses two MOS devices which are enhancement type. Q1 acts as the load
resistor and Q2 as driver device. The load is PMOS and driver is NMOS. The input is connected to gate
terminal of both MOS device. The source of PMOS is connected to supply Vdd and drain terminal to drain
of NMOS from which output is taken.
Layout of Inverter
1. Vertical Layout Design:
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Results:
Observation:
Delay: 2ps
Optimized Area: 792 lambda2
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3. Horizontal Layout Design:
Result:
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3. Inverter with Dual Contact and Substrate:
Result:
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VTC Characteristic:
This represents Output Voltage Vs. Input Voltage Graph.
Conclusion:
In this experiment we design CMOS inverter circuit in three different way and get
the response of the circuit. By observing the output voltage vs. input voltage graph we
understand the response of the inverter.
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Practical 3
Date: 17th Jan
Aim: To prepare layout for given logic function and verify it with simulations.
Objective:
1. To Simulate the Buffer.
2. To Simulate NAND and NOR Gate.
3. To Simulate one Boolean Equation.
Layout of Buffer:
Results:
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Layout of CMOS NAND Gate:
Results:
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Layout of CMOS NOR Gate:
Results:
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Layout of Boolean Function:
F  A.B  C.D
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Results:
Conclusion:
In this experiment we design the design the buffer, NAND, NOR, and a Boolean
function and understand the design and the working of all this circuits.
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Practical 4
Date:31st Jan
Aim: To study about VHDL as first Look.
Objective:
1. To learn Basic about VHDL.
2. To know about VHDL Elements.
Introduction:
 VHDL stands for Very high speed integrated circuit Hardware Description Language
 Funded by the US Department of Defense in the 70's and 80's
 Originally meant for design standardisation, documentation, simulation and ease of
maintenance.
 Established as IEEE standard IEEE 1076 in 1987. An updated standard, IEEE 1164 was
adopted in 1993. In 1996 IEEE 1076.3 became a VHDL synthesis standard.
 Today VHDL is widely used across the industry for design description, simulation and
synthesis.
Software Language Vs Hardware Description Language
In a software language, all assignments are sequential. This means that the order in which the
statements appear is significant because they are executed that way. On the other hand the events
in hardware are concurrent, and they must be represented that way. A software language cannot
be used to describe hardware and therefore a Hardware Description Language is required. To
illustrate this fact consider the following circuit:
The required output equation is C = (not (X) and Y) or (not (X))
If the statements are evaluated sequentially like software, we get different results when the order
is changed. This is because of the fact that hardware is always concurrent. Hence software
languages and tools cannot be used to describe hardware. In VHDL language "concurrent
statements" are defined to take care of concurrency in hardware. The simulation engine (that runs
on sequential computers) also has to ensure concurrency in the simulation results.
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How is concurrency achieved?
One of the requirements for the simulation engine is "order independence" for all concurrent
statements. Thus, if a signal is inverted by process "A", and that signal is read by process "B" at
the same instant of time, it is imperative that process "B" read the old uninverted value. This is
regardless of whether process "A" or process "B" was executed first. This is achieved means of
scheduling. When the simulator tags the signal for an update, it does not perform the update
immediately, but rather remembers the value to be updated. The value is actually updated when
the simulator has finished processing the complete description once.
Features of VHDL:
 VHDL is the combination of following languages
- Sequential Language
- Concurrent Language
- Net-List Language
- Simulation Language
- Timing Specifications
- Test Language
 Powerful Language Constructs
- e.g. if –then –else / when –else etc.
 Design Hierarchies to create modular design
 Support for Design Libraries
 Portable and Technology independent
 VHDL is not case sensitive
 VHDL is a free form language. You can write the whole program on a single line.
Fig: One Sample Program in VHDL.
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Quartus II:
Starting New Project:
 Open Quartus II
 Start Wizard File->New Project Wizard
 Click Next , Specify Name of Project and the directory and click Next
 Specify files you want to add and click Next
 Specify FPGA and click Next , Next and Finish
Cyclone II , EP2C20F484C6
Conclusion:
By performing this experiment we understand the basic conspectus of the VHDL
and the some starting knowledge of the Quartus II.
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Date: 7st Fab
Practical 5
Aim: Implementation of basic logic gates and its testing.
Objective:
1. First Exposure to VHDL Coding.
2. To Implement the VHDL coding of basic gates.
VHDL Code:
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----------library--------------------------------------------library IEEE;
use IEEE.std_logic_1164.all;
------------------------------------------------------------------------------entity decleration----------------------------------entity all_gate is
port (a,b: in std_logic;
c1,c2,c3,c4,c5,c6,c7,c8: out std_logic);
end all_gate;
-----------------------------------------------------------------------------architecture--------------------------------------------architecture all_gate_begin of all_gate is
begin
c1<=(a and b);
c2<=a or b;
c3<=a nand b;
c4<=a nor b;
c5<=a xor b;
c6<=a xnor b;
c7<=not a;
c8<=not b;
end all_gate_begin;
------------------------------------------------------------------
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Result:
Conclusion:
By performing this experiment we understand how to write the VHDL code for
the basic logic gates and by simulation we verify the function of the logic gates.
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Practical 6
Date: 14th Fab
Aim: Implementation of Adder Circuit and its testing.
Objective:
1. To Implement VHDL Code for Half Adder.
2. To Implement the VHDL Code for Full Adder.
VHDL Code:
1. VHDL Code for Half Adder
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-------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------entity half_adder is
port(a,b:in std_logic;
sum,carry:out std_logic);
end half_adder;
-----------------------------------------------------------architecture half_adder1 of half_adder is
begin
sum<=a xor b;
carry<=a and b;
end half_adder1;
------------------------------------------------------------
Result:
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2. VHDL Code for Full Adder.
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------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------entity full_adder is
port(a,b,c:in std_logic;
sum,carry:out std_logic);
end full_adder;
------------------------------------------------------architecture full_adder1 of full_adder is
signal a1,a2:std_logic;
begin
a1<=a xor b;
sum<=a1 xor c;
a2<=a and b;
carry<=a or c;
end full_adder1;
--------------------------------------------------------
Result:
Conclusion:
By performing this experiment we understand how to write the VHDL code for
the half and full adder code and verify the function of the half and a full adder circuit.
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Practical 7
Date: 21th Fab.
Aim: Implementation of D Flip Flop and its Testing.
VHDL Code:
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----------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
----------------------------------------------------------------------ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
----------------------------------------------------------------------ARCHITECTURE behavior OF dff IS
BEGIN
PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
q <= '0';
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END behavior;
------------------------------------------------------------------------
Result:
Conclusion:
By performing this experiment we understand the function of the D-FF and also
write the program in VHDL and simulate that.
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Practical 8
Date:28st Fab.
Aim: Implementation of RS and JK Flip Flop and its Testing.
VHDL Code for RS flip flop:
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-------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------ENTITY rsff is
port (s,r,clk : In std_logic;
q : buffer std_logic );
END rsff;
-------------------------------------------------------ARCHITECTURE arch_rsff of rsff is
Begin
process(r,s,clk)
Variable qbar:std_logic;
Begin
if (clk='1'and clk’event) then
Qbar:=r nand (s nand qbar);
END if;
Q<=qbar;
END process;
END arch_rsff;
--------------------------------------------------------
Result for RS flip flop:
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VHDL code for JK flip flop:
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--------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------------------------ENTITY jkff is
port (j,k,clk:in std_logic;
q,q1,z:inout std_logic);
END jkff;
--------------------------------------------------------------------------ARCHITECTURE arch_jkff of jkff is
Begin
process (clk)
Begin
if clk='1' then
z<=(j and (not q)) or ((not k) and q);
q<=z ;
q1<=not z ;
END if;
END process;
END arch_jkff;
----------------------------------------------------------------------------
Result of JK flip flop:
Conclusion:
By performing this experiment we understand the how to write the VHDL code
for the SR and JK flip flop and verify the function of these flip flops.
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Practical 9
Date:21th Mar.
Aim: Implementation of 4:1 Multiplexer and its Testing.
VHDL Code:
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-----------------------------------------------------------------LIBRARY ieee;
Use ieee.std_logic_1164.all;
------------------------------------------------------------------ENTITY mux is
Port ( a,b,c,d,s0,s1 : in std_logic;
y : out std_logic );
END mux ;
-------------------------------------------------------------------ARCHITECTURE arch_mux of mux is
Begin
Process (a,b,c,d,s0,s1)
Variable sel : INTEGER RANGE 0 TO 3;
Begin
Sel := 0;
If (s0 = ’1’) then sel := sel + 1;
END if;
If (s1 = ’1’) then sel := sel + 2;
END if;
CASE sel is
When 0 => y <=a;
When 1 => y <=b;
When 2 => y <=c;
When 3 => y <=d;
END CASE;
END process;
END arch_mux;
--------------------------------------------------------------------------
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Result:
Conclusion:
By performing this experiment we understand the how to write the VHDL
program for 4:1 multiplexer and by using simulation we verify the function of mux.
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Practical 10
Date:28th Mar.
Aim: Implementation of 3 to 8 Decoder and its Testing.
VHDL Code:
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------------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------------------------------------ENTITY decoder IS
PORT ( ena : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END decoder;
--------------------------------------------ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
BEGIN
temp1 := (OTHERS => '1');
temp2 := 0;
IF (ena='1') THEN
FOR i IN sel'RANGE LOOP
IF (sel(i)='1') THEN
temp2:=2*temp2+1;
ELSE
temp2 := 2*temp2;
END IF;
END LOOP;
temp1(temp2):='0';
END IF;
x <= temp1;
END PROCESS;
END generic_decoder;
---------------------------------------------
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Result:
Conclusion:
By performing this experiment we understand how to write VHDL code for 3 to 8
coder and by using simulation we verify the function of 3 to 8 decoder.
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Practical 11
Date:04st Apr
Aim: Implementation of BCD Counter and its Testing.
VHDL Code:
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----------------------------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
---------------------------------------------------------------------------------------------------ENTITY counter IS
PORT ( clk, rst: IN STD_LOGIC;
count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END counter;
--------------------------------------------------------------------------------------------------ARCHITECTURE state_machine OF counter IS
TYPE state IS (zero, one, two, three, four,
five, six, seven, eight, nine);
SIGNAL pr_state, nx_state: state;
BEGIN
------------- Lower section: ----------------------------------------------------------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= zero;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
------------- Upper section: -----------------------------------------------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
count <= "0000";
nx_state <= one;
WHEN one =>
count <= "0001";
nx_state <= two;
WHEN two =>
count <= "0010";
nx_state <= three;
WHEN three =>
count <= "0011";
nx_state <= four;
WHEN four =>
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count <= "0100";
nx_state <= five;
WHEN five =>
count <= "0101";
nx_state <= six;
WHEN six =>
count <= "0110";
nx_state <= seven;
WHEN seven =>
count <= "0111";
nx_state <= eight;
WHEN eight =>
count <= "1000";
nx_state <= nine;
WHEN nine =>
count <= "1001";
nx_state <= zero;
END CASE;
END PROCESS;
END state_machine;
-----------------------------------------------------------------------------------------
Result:
Conclusion:
By performing this experiment we understand how to write VHDL code for the
BCD counter circuit and by using simulation we verify the function of the BCD counter.
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Practical 12
Date:11th Apr
Aim: Design of Logic Gates using Block Diagram Technique and its Testing.
Circuit Schematic:
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Result:
Conclusion:
By performing this experiment we understand the design of Gates using Block
Diagram Technique and it is useful to generate the VHDL code without writing the code. Block
Diagram Technique is more easy and faster for the simulation of circuit compared to
conventional VHDL code.
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Practical 13
Date:11th Apr
Aim: Design of Adder Circuit using Block Diagram Technique and its Testing.
Circuit Schematic:
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Result:
Conclusion:
By performing this experiment we understand the design of adder circuit using
block diagram technique and we verify the function of adder circuit.
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Practical 14
Date:18th Apr
Aim: Implement one FSM that has two state, namely stateA and stateB. There are three
input variables x, y, d and q as output variable.When d=0 the current state is hold
otherwise state has to be changed to other state. Reset state is stateA. Here stateA means
q=x and stateB means q=y.
VHDL Code:
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--------------------------------------------ENTITY simple_fsm IS
PORT ( a, b, d, clk, rst: IN BIT;
x: OUT BIT);
END simple_fsm;
---------------------------------------------ARCHITECTURE simple_fsm OF simple_fsm IS
TYPE state IS (stateA, stateB);
SIGNAL pr_state, nx_state: state;
BEGIN
----- Lower section: ---------------------PROCESS (rst, clk)
BEGIN
IF (rst='1') THEN
pr_state <= stateA;
ELSIF (clk'EVENT AND clk='1') THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: ----------------PROCESS (a, b, d, pr_state)
BEGIN
CASE pr_state IS
WHEN stateA =>
x <= a;
IF (d='1') THEN nx_state <= stateB;
ELSE nx_state <= stateA;
END IF;
WHEN stateB =>
x <= b;
IF (d='1') THEN nx_state <= stateA;
ELSE nx_state <= stateB;
END IF;
END CASE;
END PROCESS;
END simple_fsm;
----------------------------------------------
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Result:
Conclusion:
By performing this experiment we understand that how to write the VHDL code
for Finite State Machine (FSM) and we verify the simulation of the circuit.
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Appendix A
Microwind Reference Guide
FILE MENU
Reset the program and
start with a clean
screen
Read a layout
data file
Insert a layout in the
current layout
Extract the
electrical circuit
and translates
into SPICE
Translates the
layout into CIF
Save the layout
Access to the list
of foundries
(*.RUL)
Switch to
monochrom/Color mode
Layout properties :
number of box,
devices, size
Print the layout
Quit Microwind and
returns to Windows 95
VIEW MENU
Unselect all layers
and redraw the layout
Fit the window with
all the edited layout
Zoom In, Zoom out
the layout window
Access to the
measured I/V
View the 2D crosssection of the layout
Redraw the screen
Protect all layers
from
modifications
Extract the electrical
node starting at the
cursor location
Extract the node
propagating on metal
interconnects
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SIMULATE MENU
Extract the electrical
circuit an run the
simulation
Access to the SPICE model
and some extraction options :
layout cleaning, handle
lateral coupling ...
Access to the single MOS
characteristics in DC,
model parameters and
measurements
Extract the electrical
network and make a
SPICE file
Select MOS
model, gain
access to
parameters
Remove redundant
boxes, clean the data
base
ANALYSIS MENU
Verifies the layout and highlight
the design rule violations
Gives the list of nodes not
connected to diffusion layers
Shows the
navigator menu
Computes the effects of
VDD, t°, capacitance on
delay, freq, etc...
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PALETTE (
)
Contact
diffn/metal
Contact
diffp/metal
Contact
poly/metal
Contact
via/metal
MOS
generator
Unprotect all layers
Pad
Routing
Select the
current
layer
Protect/unprotect
the layer from
delete & stretch
LIST OF ICONS
Open a layout file MSK
Save the layout file in MSK format
Draw a box using the selected layer of the palette
Delete boxes or text.
Copy boxes or text
Stretch or move elements
Zoom In
Zoom Out
View all the drawing
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Extract and view the electrical node pointed by the cursor
Extract and simulate the circuit
Measure the distance in lambda and micron between two points
2D vertical aspect of the device
Design rule checking of the circuit. Errors are notified in the layout.
Add a text to the layout. The text may include simulation properties.
Chip library of contacts, MOS, metal path, 2-metal routing, pads, etc...
View the palette
Static MOS characteristics
LIST OF FILES
PROGRAM
MICROWIND.EXE
*.RUL
*.MSK
*.MES
*.CIR
*.TXT
DESCRIPTION
Layout Editor and Simulator
Design rule files
Layout files
MOS I/V Measurements
Spice compatible files
Verilog text inputs
*.RUL The MICROWIND program reads the rule file to update the simulator parameters (Vt,
K,VDD, etc...), the design rules and parasitic capacitor values. A detailed description of the
.RUL file is reported at the end of Chapter 8.
*.MSK The MICROWIND software creates data files with the appendix .MSK. Those files are
simple text files containing the list of boxes and layers, and the list of text declarations. The 3D
module can simulate the fabrication process of any .MSK file.
*.CIR The MICROWIND program generates a SPICE compatible description file when the
command File -> Make SPICE File is invoked. For example, if the current file is
MYTEST.MSK, a text file MYTEST.CIR is generated and contains the list of transistors,
capacitors and voltage sources corresponding to the drawing, in SPICE compatible format
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Appendix B
Introduction Quartus II
It is useful for ,
 Synthesis tool
 Place and Route
 Simulator
 Debugger
 Programmer
 And much more
Project Files Description
 .qpf Project file
 .qsf Settings file (timing , constrains , pin)
 .vhd Design file , must be at least a top level design file its ports are directly connected
to physical pins
 .stp Signal Tap file
 .vwf Simulation Waveform file
 .sof FPGA programming file
Starting New Project
Open Quartus II (7.2)
Start Wizard File->New Project Wizard
Click Next , Specify Name of Project and the directory and click Next
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Specify files you want to add and click Next
Specify FPGA and click Next , Next and Finish
Cyclone II , EP2C20F484C6
Create VHDL File
o Create new files File->New
o Add existing files and set compilation order Assignments ->Settings->Files
o Changing Top level entity
Assignments->General ->Top-level entity
o Analyze the project : Push
Button
o View resource utilization at “Compilation Report”
Simulation

Add Vector file File->New
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


Add signals Edit->Insert->Insert node or bus
Press the “Node Finder” and select signals
Change Simulation Time Edit->End Time, Edit->Grid Size
Setting waveforms
o Use the buttons on the left side to generate input signals
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Running simulation



Save
the
Waveform
file
and
go
-> Processing ->Simulator tools
Set simulation mode to Functional and choose your file as simulation input
Generate Netlist > start simulation > Report
to
:
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