Fan-Out Wafer/Panel-Level Packaging
(FOW/PLP)
John H Lau
ASM Pacific Technology
852-2619-2757; John.lau@asmpt.com
1
CONTENTS
Formation of Fan-out Wafer-Level Packaging (FOWLP)
FOWLP Chip-first (die face-down)
FOWLP Chip-first (die face-up)
FOWLP Chip-last (RDL-first)
Fabrication of Redistribution Layers (RDLs)
Polymer and ECD Cu + Etching
PECVD and Cu damascene + CMP
Hybrid RDLs
Warpages
Kinds of Warpages
Allowable of Warpages
Reliability of FOWLP
Thermal-Cycling Test
Thermal-Cycling Simulations
Drop Test
Drop Simulations
TSMC InFO
InFO-PoP for Smartphones
InFO_AiP for 5G Millimeter Wave
InFO for HBM (High Bandwidth Memory)
2
CONTENTS (Continue)
Samsung PLP
PoP for Smartwatches
SiP SbS for Smartphones
Formation of Fan-out Panel-Level Packaging (FOPLP)
PCB + SAP
PCB + LDI
PCB + TFT-LCD
PCB/ABF/SAP + LDI
Wafer vs. Panel
Application Ranges of FOWLP and FOPLP
Critical Issues of FOPLP
Fan-Out RDL for High Performance Applications
STATSChipPac’s FOFC-eWLB
ASE’s FOCoS
Mediatek’s FO-RDLs
Samsung’s Si-Less RDL Interposer
TSMC’s InFO_oS and InFO_MS
Trends in FOWLP and FOPLP
3
Chip Edge
Over Mold Encapsulant
Dielectric
CHIP
PCB
Solder Mask
(Polyimide)
Metal wire
(RDL)
Metal pad
Solder Ball
4
eWLB (Embedded Wafer-Level Ball Grid Array)
RDLs
Pads
Solder balls
Lau, PDC ECTC2014
Infineon was the First Company to Commercialize its own eWLB
Packaging Technology in an LGE cell-phone in early 2009
Mold
Baseband SoC
PCB
RDLs
Solder ball
Infineon’s chip is a wireless baseband SoC with multiple integrated
functions (GPS, FM radio, BT…). The same eWLB product has also
been in production in Nokia handsets since 2010.
LGE (wireless baseband), Samsung (baseband modem), and Nokia
(baseband modem and RF transceiver) have used Infineon’s eWLB in
their cell phone products.
Infineon wireless operation (which own eWLB) was acquired by Intel in 2011.
6
Wirebonding and Flip Chip are not
Wafer-Level Packaging
Device Wafer
Device Wafer
Wafer Bumping
and Singulation
Singulation
Wirebonds
Over Mold
Die attach
Solder
Bumps
Underfill
Chip
Chip
Substrate
Substrate
Solder Ball
Solder Ball
PCB
PCB
Wire Bonding Technology
Flip Chip Technology
Temporary (Reconstituted) Carrier for
KGDs (Known Good Dies)
Device Wafer
Tested for KGD & Diced
The street (space )
between chips is
very small ~50µm
Chip
Passivation
Temporary Carrier
Temporary Carrier
KGD
Al or Cu Pad
Chip (KGD)
Place the KGDs a distance apart
so we can make the fan-out of
the RDLs of the KGDs!
8
FOW/PLP Needs a Temporary Carrier
to fan-out the RDLs
Round
KGD
Device Wafer
Tested & Diced for KGD
The street
(50µm) is too
small to do
fan out RDLs
Temporary
Wafer carrier
Passivation
Al or Cu Pad
KGD
Rectangular
Temporary
Panel carrier
Lau, PDC, ECTC2015
KGDs
9
SiP with FOW/PLP
EMC
Pad
KGD
KGD
RDLs
Dielectric
Pad
Solder
ball
Solder mask or polymer
PCB
KGD
KGD
EMC
Solder ball
10
Lau, PDC, ECTC2015
Infineon called it eWLB
(embedded wafer-level ball grid array).
Today, people called it FOWLP
(fan-out wafer-level packaging). The
temporary carrier is round (wafer).
For some people, they called it FOPLP
(fan-out panel-level packaging). The
temporary carrier is rectangular (panel).
11
FOW/PLP Formations
 Chip-First (Die Face-Down)
 Chip-First (Die Face-Up)
 Chip-Last (RDL-First)
RDL (Redistribution Layer)
Fabrication Methods
(A) Polymer and ECD Cu + Etching Method
(B) PECVD and Cu Damascene + CMP Method
(C) Hybrid RDLs
12
Chip-First (Die Face-Down)
Chip-First (Die Face-Up)
Most of the fan-out wafer/panel-level
packages in manufacturing today use either
one of these formations for portable, mobile,
and wearable products.
The reconfigured carrier is neither
wafer or panel!
13
FOW/PLP Formation: Chip-First (Die Face-Down)
2-side (thermal release ) tape
Test for KGD and Dice
Temporary wafer/panel carrier
Device
Wafer
Chip-first (Die
face-down)
KGD
KGD
KGD
KGD
(b)
Reconstituted carrier
Passivation
(a)
Al or Cu Pad
Compression
molding of
EMC on
reconstituted
carrier
CHIP
EMC
(c)
Remove carrier
and tape
(d)
Build RDLs and
mount solder balls
(e)
RDLs
Solder balls
Dice the molded wafer/panel
into individual packages
Lau, et al., CSR, 2016
Solder balls
EMC
KGD
KGD
KGD
KGD
(f)
RDLs
14
5mmx5mm and 3mmx3mm Test Chips for Wafer
Inner Row:
Pads = 160; Pitch = 100µm
Inner Row:
Pads = 80; Pitch = 100µm
100
SiO2
Al Pad
IEEE Trans. CPMT
2018, pp. 1544-1560
15
5mmx5mm and 3mmx3mm Test Chips for Wafer
Pad
Chip
5mmx5mm
Pad
Chip
3mmx3mm
IEEE Trans. CPMT
2018, pp. 1544-1560
16
Layout of the SiP
300mm Temporary
Carrier:
 629 SiPs
 Each SiP consists
of 4 chips and 4
capacitors
Chip: 3mmx3mm
3x3
3x3
5mmx5mm
3x3
Chip: 3mmx3mm
R2-5 S-2
R2-6
S-5
R2-1
S-1
S-1
R1-3
R1-1
R1-4
R1-4
S-5
R2-5 R2-6 R2-4
S-4
R1-3
R1-6
R1-7
R1-5
R1-11
R1-10
R1-8
C2
R1-7
C2
R1-1
R1-8
R1-5
C1
C1
R1-2
R1-2
R1-9 R1-9
S-2
R2-1 R2-2 R2-3
R1-11
S-3
R1-6
R1-10
R2-4 S-3
R2-2
S-4
R2-3
Chip: 5mmx5mm Chip: 3mmx3mm
Capacitor
17
SiP with 4 Test Chips and 4 Capacitors
EMC
3mm
CHIP2
CHIP3
CHIP1
5mmx5mm
3x3
3mm
100µm
5mm
100µm
3x3
CHIP2
3mm
10mm
CHIP4
3x3
3mm
3mm
3mm
0.95mm
100µm
0402
5mm
Ceramics
L
Cu
Ni Plating
10mm
0.95mm
Line width/spacing of:
 1st RDL are 10/10µm
 2nd RDL are 15/15µm
IEEE Trans. CPMT
2018, pp. 1544-1560
T
e
Capacitor
0402 (Unit = mm)
e = 0.28+0.10/-0.05 ; L = 1.0±0.05
W = 0.5±0.05; T = 0.135±0.015
18
Schematic of the Cross Section of
the SiP on Wafer
EMC
CHIP
150µm
Cu-pad
DL1
VC1
RDL1 (Metal)
55µm-pad
DL2
220µm-Pad
RDL2 (Metal)
55µm-pad
V12
65µm-pad
DL3 (Passivation)
180µm Opening
Dielectric layer: DL1 = DL2 = 5µm, DL3 = 10µm
VC1 of DL1 (PI1) = 20-30µm
V12 of DL2 (PI2) = 35-45µm
Metal of RDL1 = 3µm
Metal of RDL2 = 7.5µm
Surface Finishing: NiAu
Metal line width and spacing = 10µm and 15 µm
IEEE Trans. CPMT
2018, pp. 1544-1560
19
FOW/PLP Formation: Chip-First (Die Face-Down)
2-side (thermal release ) tape
Test for KGD and Dice
Temporary wafer/panel carrier
Device
Wafer
Chip-first (Die
face-down)
KGD
KGD
KGD
KGD
(b)
Reconstituted carrier
Passivation
(a)
Al or Cu Pad
Compression
molding of
EMC on
reconstituted
carrier
CHIP
EMC
(c)
Remove carrier
and tape
(d)
Build RDLs and
mount solder balls
(e)
RDLs
Solder balls
Dice the molded wafer/panel
into individual packages
Lau, et al., CSR, 2016
Solder balls
EMC
KGD
KGD
KGD
KGD
(f)
RDLs
20
FOWLP (Chip-First and Die Face-Down)–
Need a KGD and Temporary Carrier
Test for KGD (known-good die) and Dice
2-side (thermal release ) tape
Temporary metal wafer/panel carrier
Device
Wafer
KGD
Passivation
Temporary carrier
with 2-side tape
Al or Cu Pad
KGD
Place the KGDs face-down on the 2-side tape
on the temporary wafer carrier
KDG
KGD
KGD
Temporary metal wafer/panel carrier
Reconstituted (reconfigured) Wafer
21
Carrier Material and Thickness
Carrier
Material and
Thickness
Thermal
expansion
coefficient
(10-6/oC)
Young’s
modulus
(GPa)
Poisson’s
ratio
Silicon (0.76mm)
2.6
168
0.28
Glass-1 (0.76mm)
3.2
73.6
0.3
Glass-2 (1mm)
7.6
69.3
0.3
Stainless Steel 420
(1.5mm)
10.5
200
0.3
22
Nitto Thermal Release 2-Side Tape
"REVALPHA" (170°C Release)
Release liner (0.038mm)
Thermal-release adhesive (0.048mm)
Polyester film (0.1mm)
Pressure-sensitive adhesive (0.01mm)
Release liner (0.075mm)
Apply at room temperature.
23
Nagase Liquid Epoxy Molding Compound (EMC)
Item
R4507
Filler content (%)
85
Filler to cut (µm)
25
Filler average size (µm)
8
Specific gravity
1.96
Viscosity (Pa.s)
250
Flexural Modulus (GPa)
19
Tg (DMA) (℃)
150
CTE1 (ppm/K)
10
CTE2 (ppm/K)
41
 High flowability as suitable for
large surface areas and thin
film molds
 Liquid at room temperature
and able to be dispensed, and
dust-free as suitable for clean
room environments
 Capable of low temperature
form molding (125°C)
 Delivers low reflection in large
surface area molds with low
stress design
 High reliability
 High purity
 Low α line
Compression Molding: 125oC for 10 minutes
Post Mold Cure: 150oC for ≥ one hour
24
SiP on the Temporary (Reconstituted) Carrier
3x3
Chip
3x3
Chip
3x3
Chip
5x5
Chip
100µm-Gap
3mm x 3mm Chip
300mm temporary
(reconstituted) carrier:
 629 SiPs
 Each SiP consists
of 4 chips
5mm x 5mm Chip
100µm-Gap
FOW/PLP Formation: Chip-First (Die Face-Down)
2-side (thermal release ) tape
Test for KGD and Dice
Temporary wafer/panel carrier
Device
Wafer
Chip-first (Die
face-down)
KGD
KGD
KGD
KGD
(b)
Reconstituted carrier
Passivation
(a)
Al or Cu Pad
Compression
molding of
EMC on
reconstituted
carrier
CHIP
EMC
(c)
Remove carrier
and tape
(d)
Build RDLs and
mount solder balls
(e)
RDLs
Solder balls
Dice the molded wafer/panel
into individual packages
Lau, et al., CSR, 2016
Solder balls
EMC
KGD
KGD
KGD
KGD
(f)
RDLs
26
Compression Molding and Post Mold Cure
KGD
KDG
EMC
KGD
Remove trap
air before
compression
molding
Temporary metal carrier
2-side tape
KGD
EMC (Epoxy Molding Compound)
Compression molding the EMC on
the reconstituted wafer:
125oC for 10 minutes;
Pressure = 45kg/cm2
SAM observation of the molding voids
Post mold cure of EMC:
150oC for ≥ one hour
Reconstituted Wafer
Lau, et al. IEEE Trans. CPMT 2018
Voidless after trap air removal
After Compression Molding and
Post Mold Cure (PMC)
EMC
(Epoxy Molding Compound)
Top View
Cross-sectional
View
EMC
Chip
Carrier
28
(a) Schematic of the reconstituted wafer. (b) Molded reconstituted wafer without carrier. (c)
Zone-in on the reconstituted wafer. (d) Individual package without RDLs and solder balls
3x3
3x3
(b)
(a)
5mmx5mm
3x3
EMC
3mmx3mm
3mmx3mm
(c)
(d)
5mmx5mm
3mmx3mm
FOW/PLP Formation: Chip-First (Die Face-Down)
2-side (thermal release ) tape
Test for KGD and Dice
Temporary wafer/panel carrier
Device
Wafer
Chip-first (Die
face-down)
KGD
KGD
KGD
KGD
(b)
Reconstituted carrier
Passivation
(a)
Al or Cu Pad
Compression
molding of
EMC on
reconstituted
carrier
CHIP
EMC
(c)
Remove carrier
and tape
(d)
Build RDLs and
mount solder balls
(e)
RDLs
Solder balls
Dice the molded wafer/panel
into individual packages
Lau, et al., CSR, 2016
Solder balls
EMC
KGD
KGD
KGD
KGD
(f)
RDLs
30
Process to Fabricate RDLs (Polymer + ECD Cu)
Al Pad
Passivation
KGD
EMC
Cu Plating
Photosensitive polyimide (PI)
RDL1
Polymer
Spin Polymer
Mask aligner
or Stepper
and Etch
Polymer
Strip Resist
& Etch TiCu
TiCu
RDL2
RDL1
TiCu
EMC
KGD
Sputter
TiCu
UBM-less Cu-pad
Photoresist
Mask
aligner or
Stepper
(Litho)
IEEE Trans. CPMT
2018, pp. 1544-1560
Solder
ball
Solder
ball
UBM
Contact pad
RDL2
Dielectric2
RDL1
Dielectric1
EMC
KGD
Al Pad
Passivation
TiCu
31
Molded Reconstituted Wafer and Close-up View
300mm reconstituted wafer
 629 SiPs
 Each SiP consists of 4 chips
and 4 capacitors
IEEE Trans. CPMT
2018, pp. 1544-1560
10mmx10mm SiP
3mmx3mm
3mmx3mm
5mmx5mm
3mmx3mm
100µm Gap Capacitor
32
X-ray Image and the Cross Sections of the FOWLP
10mmx10mm SiP (4 chips & 4 capacitors)
300mm
3mmx3mm
Chip
3mmx3mm
RDL1
VC1
RDL2
Reconstituted
Wafer
5mmx5mm
3mmx3m
m
100µm Gap Capacitor
EMC
UBM-less pad
Chip
RDL1
RDL2
V12
VC1
Solder Ball
IEEE Trans. CPMT
2018, pp. 1544-1560
33
Metal Line Width and Spacing = 5µm with Dry-film EMC
Dry-Film EMC
150µm
CHIP
Cu-pad
DL1
VC1
RDL1 (Metal)
55µm-pad
55µm-pad
V12
DL2
65µm-pad
RDL2 (Metal)
220µm-Pad
DL3 (Passivation)
180µm Opening
VC1 of DL1 (PI1) = 20-30µm
V12 of DL2 (PI2) = 35-45µm
Metal thickness of RDL1 = 3µm
Metal thickness of RDL2 = 7.5µm
Dielectric thickness: DL1 = DL2 = 5µm, DL3 = 10µm
Metal line width/spacing: RDL1 (5µm), RDL2 (15µm)
Surface Finishing: NiAu
Chip
Photosensitive Polyimide
Metal L/S : 5µm / 5µm
Chip
Photosensitive Polyimide
ECTC2019
Metal L/S : 5µm / 5µm
Chip
Photosensitive Polyimide
34
Metal L/S : 5µm / 5µm
Embedded Fan-Out Panel
Wafer-Level Packaging
(FOPLP)
35
Wafer vs. Panel
(610mm x 457mm)
Area > 3.8 X 12”-wafer
12” wafer
carrier
24”x18” carrier
36
Lau, CSR, 19(6), 2015
J-Devices’ WFOP (Wide Strip Fan-Out Package)
320mm x 320mm
Chip: 3mmx3mm
Package: 5mmx5mm
20µm line width/spacing
37
EPTC2011
Process Steps for WFOP (Wide Strip Fan-Out Package)
Adhesive
KGD
Metal carrier
KGD placement (face-up)
Resin
Strip off photoresist
Resin costing (dielectric)
Seed layer
Etch off seed layer
Solder mask
Seed layer deposition
Photoresist
Solder mask coating
Solder ball
Photoresist and Lito.
Solder mask
Cu
Dielectric
layer
KGD
Metal carrier
Solder ball mounting
Cu plating
Fraunhofer’s Panel and Package
610mm x 457mm
(a)
Package: 8mm x 8mm
Chip
Chip: 2mmx3mm
(b)
Chip
39
Process for Panel RDLs by PCB and Laser Direct Imaging
Fraunhofer ECTC2015
SPIL’s Panel Fan-Out (P-FO) Packaging Technology
RDL
Adhesive
Glass Carrier 1
KGD
Solder balls
Dry film
Dry film
KGD
RDL
ECTC2014
SPIL’s Panel Fan-Out (P-FO) Packaging Technology
(a)
(b)
370mm (38 rows)
470mm (49 columns)
5mmx5mm and 3mmx3mm Test Chips for Panel
Outer Rows: Pads = 88; Pitch = 180µm
Outer Rows: Pads = 48; Pitch = 180µm
180
PI
SiO2
IEEE Trans. CPMT
2018, pp. 1561-1572 AL Pad
43
5mmx5mm and 3mmx3mm Test Chips for Panel
5mmx5mm
CHIP
Al-pad Cu-pad
3mmx3mm
CHIP
Al-pad Cu-pad
IEEE Trans. CPMT
2018, pp. 1561-1572
44
SiP with 4 Test Chips
10mm
EMC
3mm
CHIP2
CHIP3
3mm
3mm
CHIP4
3mm
10mm
100µm
0.95mm
CHIP2
3mm
CHIP1
100µm
5mm
3mm
5mm
0.95mm
Line width/spacing of:
 1st RDL are 20/20µm
 2nd RDL are 25/25µm
IEEE Trans. CPMT
2018, pp. 1561-1572
45
Schematic of the Cross Section of
the SiP on Panel
EMC
CHIP
150µm
110µm
Cu-pad
ABF DL1
50µm
Metal RDL1
135µm-Pad
135µm-Pad
50µm
ABF DL2
230µm-Pad
Metal RDL2
135µm-Pad
DL3 (Solder Mask)
180µm Opening
ABF DL1 (20µm)
ABF DL2 (20µm)
Solder Mask DL3 (20µm)
RDL1 Metal (10µm)
RDL2 Metal (10µm)
Metal line width and spacing = 20µm
IEEE Trans. CPMT
2018, pp. 1561-1572
46
RDLs by PCB + LDI + SAP Technology (Unimicron)
Ko and Lau, et al., ECTC2018
X-ray Image and the Cross Sections of the FOPLP
Chip: 3mm x 3mm
Solder Ball
Chip: 3mm x 3mm
340mmx340mm
Reconstituted Panel
Chip: 5mm x 5mm
Gap: 100µm
Chip: 5mm x 5mm
Gap: 100µm
Chip: 3mm x 3mm
Chip: 3mm x 3mm
Chip: 5mm x 5mm Gap Chip: 3mm x 3mm
RDL1
Solder
Ball
IEEE Trans. CPMT
2018, pp. 1561-1572
RDL2
48
FOPLP Formation: Chip-First2-side
(Die
Face-Down)
(thermal release) tape
Temporary carrier
Device
Wafer
Chip-first (Die
face-down)
KGD
(b)
Passivation
Al-Pad
Cu-Pad
CHIP (KGD)
 Electroplate Cu-pad
 Test for KGD and Dice
EMC
lamination or
compression
molding
EMC
KGD
(c)
Temporary carrier
2-side tape
Attach the ECM-panels
on both sides of a core
substrate with epoxy
resin. Then, perform
5-layer PCB lamination.
(a)
KGD
EMC
Core Substrate
Epoxy resin
EMC
KGD
2-side tape
Remove carrier. Peel off
the 2-side tapes. Then, it
is ready for RDLs
fabrication.
(d)
Temporary carrier
KGD
Core Substrate
KGD
(e)
508mmx508mm FOPLP for Heterogeneous Integration
10mmx10mm




1512 SiPs
SiP Size = 10mmx10mm
Each SiP has 1 large chip
and 3 small chips
Panel Size = 508mmx508mm
Chip4
Chip3
3x3
3x3
Chip1
Chip2
5x5
3x3
SiP
508mmx508mm (1512 SiPs)
508mmx508mm
(1512 SiPs)
IMAPS Trans. 2018,
pp. 141-147
RDL1
RDL2
10mmx10mm SiP
10mmx10mm SiP
508mmx508mm
(1512 SiPs)
SRO
10mmx10mm SiP
508mmx508mm
(1512 SiPs)
50
Warpage of the Double-side ECM-panel
Double-side ECM-panel (Uni-SIP structure)
Max. Warpage of the Doubleside ECM-panel = 0.918 mm
IMAPS Trans. 2018,
pp. 141-147
51
Top and Cross-section views of the individual SiP
100µm
gap
3mmx3mm
Chip
3mmx3mm
Chip
100µm gap
5mmx5mm
Chip
Dry-Film EMC
5mmx5mm
Chip
Solder Ball
IMAPS Trans. 2018,
3mmx3mm
Chip
100µm gap
5mmx5mm
Chip
Solder Ball
RDL2
Dry-Film EMC
3mmx3mm
Chip
RDL1
52
Test Board Layout
103
46.5
40
52
93
Thickness: 0.65mm
Material: FR-4
Size: 103mm x 52mm
Layer: 6
Pad finish: OSP
98
Units: mm
Pad
0.28
0.28
0.2
0.2
Solder mask opening
OSP PCB
PCB Lead-Free Reflow Temperature Profile
and Assembly
Temperature (oC)
Maximum temperature = 245oC; Time above 217oC = 85s
Time (s)
Gap (100µm)
Large Chip
Small Chip
PCB
Solder Joint
Weibull Life Distribution of the SiP Solder Joints
PCB
assemblies
Thermal cycling test without underfill
Solder joint Characteristic life = 1070 cycles
Thermal cycling chamber
90.00
Percent failed, F(x)
Holder
50.00
10.00
5.00
1.00
300
1000
2000
Cycles-to-failure
IMAPS Trans. 2018,
pp. 148-162
55
Solder Joint Failure Mode and Location
EMC
3mmx3mm
3mmx3mm
PCB
Cross Section
3mmx3mm
EMC
Solder joint crack
3mmx3mm
5mmx5mm
Voi
d
Cu-Pad
VIP
3mmx3mm
PCB
3mmx3m
m
EMC
5mmx5mm
5mmx5mm
EMC
5mmx5mm
PCB
Solder joint crack
Cross Section
5mmx5mm
EMC
Solder joint crack
IMAPS Trans. 2018,
pp. 148-162
Cu-Pad
VIP
EMC
PCB
Creep Strain Contours in Critical
Solder Joints
A
5x5 Chip
3x3 Chip
A
PCB
AA
Largest
Third largest
IMAPS Trans. 2018,
pp. 148-162
Max. Creep strain (0.1) location occurred
at 3x3 die corner solder joint (@-40˚C)
EMC
Chip-First (Die Face-Down)
Chip-First (Die Face-Up)
Most of the fan-out wafer/panel-level
packages in manufacturing today use either
one of these formations for portable, mobile,
and wearable products.
The reconfigured carrier is neither
wafer or panel!
58
FOWLP Formation: Chip-First (Die Face-Up)
IMAPS Trans.,
2017, pp. 123-131.
59
10mmx10mm Test Chip
Cu Contact-Pad
143.8µm
166.4µm
Si-Die
DAF
Glass Carrier
60µm
22.7µm
Cu
Al-pad
200
IEEE/EPTC, 2017,
pp. S23_1-6.
PI
5µm
60
13.42mm x 13.42mm FOWLP Test
Package
13.42mm
300mm Temporary Carrier with 325 Packages
13.42mm
1.71mm
1.71mm
13.42mm
Ti/Cu
Contact pad (60µm)
Cu
25µm
(5µm)
SiO2
Al-Pad
IEEE Trans., CPMT,
2018, pp. 991-1002.
EMC
Test
Chip
10mm
13.42mm
10mm
13.42mm
SiO2
Si
150µm
61
Schematic of the Cross Section of the FOWLP of the
10mmx10mm Test Chips
EMC
VC1 of DL1 (PI1) = 20µm
Metal of RDL1 = 3µm
CHIP
V12 of DL2 (PI2) = 35µm
Contact Pad
Dielectric Layer - 1 (DL1)
Metal RDL1
VC1
55µm-pad
DL2
Metal of RDL2 = 3µm
V23 of DL3 (PI3) = 45µm
55µm-pad
V12
Metal RDL2
65µm-pad
TiCu
65µm-pad
Metal of RDL3 = 7.5µm
Via of DL4 (PI4) = 180µm
DL3
V23
65µm-pad RDL3
Metal RDL3
220µm-pad
DL4 (Passivation)
Dielectric layer thickness:
DL1 = 5µm
DL2 = 5µm
DL3 = 5µm
DL4 = 10µm
IEEE Trans., CPMT,
2018, pp. 991-1002.
Solder ball
(200µm)
Metal line width and spacing
of RDL1 = 5µm
62
FOWLP Formation: Chip-First (Die Face-Up)
IMAPS Trans.,
2017, pp. 123-131.
63
Hitachi FH-9011 Die-Attach-Film
Item
Unit
FH-9011
Test method
Adhesive Thickness
μm
10, 20, 25, 40
–
mJ/cm2
150~400
–
Before UV
N/25mm
1.4
–
After UV
N/25mm
<0.1
–
Wafer laminating temp.
°C
60~80
–
Temp.
Die bonding
condition
Load
°C
100~160
–
MPa
0.05~2.0
–
Elastic modulus (35°C)
MPa
200
DMA
Tg
°C
180
TMA
Die shear strength (260°C)
N/chip
>100
5x5mm chip
Exposure doze
DC tape
properties
Adhesive
strength
between
DCT and
DBF
Wafer backside lamination: 60 - 70oC
Curing: 125oC for one hour
3M Light-To-Heat-Conversion Release Coating (LTHC) Ink
Product Description
3M™ Light-To-Heat-Conversion Release Coating (LTHC) ink is a solvent based coating applied
using a spin coating method. This coating forms the light to heat conversion layer on a glass
substrate for 3M™ Wafer Support System.
Features and Benefits
• Enables stress free, room temperature debonding of adhesive
Typical Properties Note
The following technical information and data should be considered representative or typical only
and should not be used for specification purposes.
Base Resin: Acrylic
Color: Black Thixotropic liquid
Specific Gravity: 1.00
Solid: 11%
Solvent: 1-Methoxy-2-propyl acetate
2-Butoxy Ethanol
Flash Point: 45°C
General Information
Standard container is 20L Stainless steel drum (UN: 1A1/X/250).
Storage
Store this product under normal conditions of 5°C to 35°C in original container for maximum
storage life.
Shelf Life
Six months after the date of shipping from 3M.
Method of Usage
• Product must be stirred/mixed at 600-700 RPM for 12 hours before usage.
• Product must be stirred continuously while in use.
Compression Molding of EMC
Cu contact-pad
KGD
EMC
KGD
Remove trap
air before
compression
molding
KGD
Reconstituted glass carrier
DAF
LTHC layer
KGD
EMC (Epoxy Molding Compound)
Compression molding the EMC on
the reconstituted wafer:
125oC for 10 minutes;
Pressure = 45kg/cm2
SAM observation of the molding voids
Post mold cure of EMC:
150oC for ≥ one hour
Reconstituted Wafer
IEEE Trans., CPMT,
2018, pp. 991-1002.
Voidless after trap air removal
66
(a) Top view of a Molded Reconstituted Wafer.
(b) Bottom view of a Molded Reconstituted Wafer
without the LTHC Layer so we can see the
Backside of the Test Chips.
(a)
(b)
FOWLP Formation: Chip-First (Die Face-Up)
IMAPS Trans.,
2017, pp. 123-131.
68
Test chip with tall polymer (PI ~ 30µm) to cover the
Cu contact-pad and chip surface
Contact pad = 60µmØ
Ti/Cu
30µm
Cu
PI
SiO2
Al-Pad
150µm
SiO2
Si
Cu
Si
PI
(a) Before and (b) After Backgrinding.
(c) Show 2 RDLs
(c)
(5µm)
After backgrinding the EMC to expose the Cu
contact-pads (Cu revealing)
Cu contact-pad
Cu contact-pad
Polymer
Polymer
Cu contact-pad
Cu contact-pad
Polymer
Polymer
Warpage: Post Mold Cure vs. Backgrinding
592µm (smiling face)
Simulation Result
Right after Post Mold Cure by Shadow Moire
Warpage = 609µm (Smiling Face)
864 (crying face)
Simulation Result
Right after Backgrinding by Shadow Moire
Warpage = 811.9µm (Crying Face)
IEEE Trans. CPMT,
2018, pp. 1729-1737
72
FOWLP Formation: Chip-First (Die Face-Up)
IMAPS Trans.,
2017, pp. 123-131.
73
FOWLP of Large Chip and Multiple RDLs
(13.42mm x 13.42mm)
300mm
Solder balls on package
RDLs
Chip
(10mm x 10mm)
Reconstituted Wafer
(325 packages)
Chip corner
Package
Contact-Pad
CHIP
Pads on package for TMV
RDL1
V12
UBM-less Pad
RDL2 VC1 RDL3 V23
RDL1 = 5µm
RDL2 = 10µm
RDL3 = 15µm
Solder ball
IEEE Trans., CPMT,
2018, pp. 991-1002.
74
SAM of Compression Molded EMC
Lead-Free PCB Assembly of the FOWLP
Chip
3RDLs
Solder joint height (µm)
VIP
Solder
joints
PCB
3RDLs
Chip
VIP
Solder joints
Package diagonal positions
PCB
Different Kinds of Warpages
Warpage is a critical issue for FOWLP. Depending on the number of RDLs, there are a few
different warpages affecting the FOWLP process.
 The first warpage is right after post mold cure (PMC) of the reconstituted wafer. If the
warpage is too large, then the reconstituted wafer cannot be placed and/or operated on
the backgrinding equipment to perform the backgrinding of EMC to expose the Cu
contact-pad.
 The second warpage is right after the backgrinding of the EMC to expose the Cu contactpad. If the warpage is too large, then the reconstituted wafer cannot be placed and/or
operated on the RDL equipment such as the stepper, lithographic, physical vapor
deposition, electrochemical deposition, and etching.
 The third warpage is right after the fabrication of the first RDL. (The temperature of the
PVD is about 200ºC, so there is a thermal expansion mismatch among the EMC, Si chip,
and glass carrier.) If the warpage is too large, then there are issues in making the second
RDL.
 The fourth warpage is right after the fabrication of the third RDL. If the warpage is too
large, then there are issues (such as holding and/or operating of the reconstituted wafer
on the equipment and controlling the accuracy of ball drops) in performing the solder ball
mounting.
 The fifth warpage is right after the solder ball mounting. (The temperature of the lead-free
reflow temperature is about 250ºC, so there is a very large thermal expansion mismatch
among the EMC, Si chip and glass carrier.) If the warpage of the diced individual package
is too large, then there are issues (such as solder joint standoff height variation,
stretched solder joints, and titled component) in printed circuit board (PCB) assembly.
77
Maximum Allowable Warpages
What are the maximum allowable warpages?
The rule of thumb is:
 For a 300mm reconstituted wafer, the maximum allowable warpage of
the reconstituted wafer is 1mm, but 0.5mm is preferred for high
package assembly yield.
 For an individual package (≤ 20mm × 20mm) The maximum allowable
warpage of the individual package is 0.2mm, but 0.1mm is preferred for
high PCB assembly yield.
78
Weibull Life Distribution of the Solder Joints
Thermal cycling test without underfill
Solder joint Characteristic life = 2382 cycles
80.00
RDL2
RDL1
Percent failed, F(x)
RDL3
Large
Crack
50.00
Micro Crack
Solder Joint
VIP
PCB
10.00
5.00
RDL1
RDL3
1.00
100.00
1000.00
Cycles-to-failure
3000.00
Large
Crack
RDL2
Micro
Crack
Large
Crack
Solder Joint
IEEE/ECTC2018,
pp. 1568-1576
79
Die corner solder joint
Max. accumulated creep strain
Package corner solder joint
Creep Strain Contours in Critical Solder Joints
Max. creep strain (0.04) occurred at die corner solder joint as well as the package corner
solder joint @-40˚C.
IEEE/ECTC2018,
pp. 1568-1576
80
Drop Test Setup and Spectrum
Standoffs
PCB Assembly
Accelerometer
Base Plate
Drop
Table
Guide
Rods
Drop
Table
Strike
Surface
Rigid
Base
ACCELERATION (g)
Base
Plate
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
-200
1500G/ms
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
TIME (ms)
IEEE/ECTC2018,
pp. 1568-1576
81
Drop Test Life Distribution of RDLs
70.00
Characteristic Life = 1271 Drops
Percent Failed, F(x)
50.00
10.00
5.00
1.00
300
1000
1500
Number of Drops
IEEE/ECTC2018,
pp. 1568-1576
82
Drop Test Failure Modes
EMC
PCB
Package
Chip
EMC
RDL1
EMC
Solder
Joint
Crack
RDL2
RDL2
RDL3
Broken
VIP
RDL3
PCB
IEEE/ECTC2018,
pp. 1568-1576
83
Drop Test Simulation
EMC
Die
PI
Underfill
Solder
RDL
Cu trace
z
y
PCB
Schematic for model
x
PCB
EMC
Die
IEEE/ECTC2018,
pp. 1568-1576
Finite Element Modeling and Results for Drop Test
Solder
Package corner
Solder joint
(a)
(b)
IEEE/ECTC2018,
pp. 1568-1576
Finer meshes on
package corner joints
Cu trace
(RDL) on
package
Cu trace on PCB
Simulation Results for Drop Test
IEEE/ECTC2018,
pp. 1568-1576
86
System in Wafer-Level Package Technology
with RDL-first Process
Norikazu Motohashi, Takehiro Kimura, Kazuyuki Mineo, Yusuke Yamada, Tomohiro Nishiyama,
Koujiro Shibuya, Hiroaki Kobayashi, Yoichiro Kurita, and Masaya Kawano
Renesas Electronics Corporation
1120, Shimokuzawa, Chuou-ku, Sagamihara, Kanagawa, Japan
norikazu.motohashi.uf@renesas.com, +81-42-771-0669
RDL-First (Chip-Last) Method
87
ECTC2011
Chip-Last (RDL-First)
Fan-Out Wafer-Level Packaging (FOWLP)
Since 2006, NEC Electronics Corporation (now Renesas Electronics Corporation)
has been developing a novel SMAFTI (SMArt chip connection with FeedThrough
Interposer) packaging technology for:
 inter-chip wide-band data transfer
 3D stacked memory integrated on a logic devices
 system in wafer-level package (SiWLP) (2010)
 and “RDL-first” fan-out wafer-level packaging (2011)
The FTI (feedthrough interposer) of SMAFTI is a film with ultra-fine line width and
spacing RDLs. The dielectric of the FTI is usually SiO2 or polymer and the
conductor wiring of the RDLs is Cu.
The FTI not only supports the RDLs underneath within the chip, it also supports
beyond the edges of the chip.
Area array solder balls are mounted at the bottom-side of the FTI which are to be
connected to the PCB. Epoxy mold compound (EMC) is used to embed the chip
and support the RDLs and solder balls.
In 2015, Amkor announced a very similar technology called “SWIFTTM” (silicon
wafer integrated fan-out technology).
88
Lau, et al., CSR 20(3), 2016
RDL-First:– Assembly Process Steps
Cu-pillar with
solder cap
Chip
(a)
Pad
Chip
Glass wafer
Sacrificial layer
Underfill
Chip-to-wafer with
RDLs bonding
RDLs
Underfill dispensing
and curing
(b)
EMC (epoxy molding compound)
(c)
Compression
molding of EMC
(d)
Debonding the glass
wafer by a laser
EMC
Cu-pillar with
solder cap
Underfill
Chip
(e)
RDLs
Solder ball
Solder ball mounting
and dicing
89
Lau, PDC, ECTC2015
C4 Bumps vs. C2 Bumps
Solder
Cu
(5) ECD Cu, Solder
(7) Etch Cu/Ti
Cu
Solder
Passivation
pad
Solder
TiCu
Pad
Si
Si
(6) Strip Resist
(1) Redef. Passivation
(3) Spin Resist
UV
Cu
Ti
(8) Flux, Reflow
Passivation
C4 (controlled collapsed chip connection) bump
Mask
Solder
Cu
(4) Patterning
(2) Sputter Ti/Cu
(5) ECD Cu, Solder
Solder
(7) Etch Cu/Ti
Solder
TiCu
Cu
Cu
Pad
Si
(6) Strip Resist
(8) Flux, Reflow
Passivation
C2 (chip connection) bump
Structure
Major
Material
Thermal conductivity
(W/m K)
Electrical
resistivity (µΩm)
Pad pitch
Self alignment
C2 bump
Cu
400
0.0172
Smaller
Smaller
C4 bump
Solder
55–60
0.12–0.14
Larger
Larger
Lau, ASME Trans.
JEP 2016, pp. 1-23.
90
SEM image of
C2 bumps with
solder caps
SEM image of
C2 bumps
without solder
caps
SnAg
Cu
Pillar
9μm
Cu Pad/UBM
Si
91
Lau_ASME Trans. on Electronic Packaging, Sept. 2016.
RDL-First:- Process Steps for Fabricating RDLs
Sacrificial layer
(a)
Cu-pad
Glass wafer
DL1
Opening
Coating a release (sacrificial)
layer on a glass wafer
Cu-contact pads and UBM
fabrication and first dielectric
layer (DL1) opening
(b)
RDL1
Fabrication of the first RDL1
(c)
DL2
Opening
Second dielectric
layer (DL2) opening
(d)
RDL2
Fabrication of the
second RDL2
(e)
DL3
(f)
µbump pads
Third dielectric layer
(DL3) opening and
µbump pads formation
92
Lau_Chip Scale Review, 2016
FOWLP with Chip-Last or RDLs First Process
Flip chip
Cu-pillar
Flip chip with C2 bumps on RDLs
RDLs
Solder
Solder ball
RDLs
Solder ball
PCB
IME, 2015
100µm
Cu-pad on PCB
50µm
Chip-Last or “RDL-first” FOWLP
This is very different from the chip-first FOWLP.
First of all, this only works on wafer carrier.
Also, comparing to chip-first, RDL-first FOWLP requires:
 building up the RDLs on a bare glass/silicon wafer (the FTI),
 performing the wafer bumping,
 performing the fluxing, chip-to-wafer with RDLs bonding, and cleaning,
 performing the underfill dispensing and curing.
Each of these tasks is a huge task and requires additional materials, process,
equipment, manufacturing floor space, and personal effort.
Thus, comparing to chip-first FOWLP, chip-last (RDL-first) FOWLP incurs very
high cost and has more chances to have higher yield losses. It can only be
afforded by very-high density and performance applications such as high-end
servers and computers.
94
Lau, et al., CSR 20(3), 2016
RDL Fabrications
Organic RDLs:
By using (either an ordinary or a photosensitive) polymer to make the dielectric layer
and Cu-plating + etching to make the conductor layer for all the RDLs. It can be applied
to chip-first and chip-last processes.
Multi-Chips
Inorganic RDLs:
TSV
By using PECVD to make the SiO2 (or SiN) dielectric layer and Cu-damascene + CMP to
make the conductor layer of all the RDLs. It can be applied to chip-first and chip-last
TSV Interposer
processes.
Hybrid RDLs:
Today, this only apply to chip last (RDL-first) process. By using PECVD and Cudamascene + CMP to make the first fine line width and spacing RDL and then using a
polymer (either ordinary or photosensitive) to make the dielectric layer and Cu-plating
+ etching to make the conductor layers for the rest of not so fine line width and
spacing RDLs.
PCB/LDI RDLs:
The ABF is used as the dielectric of the RDLs and is built up by SAP. The electroless
Cu is used to make the seed layer, the LDI is used for opening the photoresist, and the
PCB Cu plating is used for making the conductor wiring of the RDLs.
95
Lau, ECTC2017-PDC
Process to Fabricate RDLs (Polymer + ECD Cu)
96
Lau, PDC, ECTC2015
Process to Fabricate RDLs (Polymer + ECD Cu)
Al Pad
Passivation
KGD
EMC
Cu Plating
Photosensitive polyimide (PI)
RDL1
Polymer
Spin Polymer
Mask aligner
or Stepper
and Etch
Polymer
Strip Resist
& Etch TiCu
TiCu
RDL2
RDL1
TiCu
EMC
KGD
Sputter
TiCu
UBM-less Cu-pad
Photoresist
Mask
aligner or
Stepper
(Litho)
IEEE Trans. CPMT
2018, pp. 1544-1560
Solder
ball
Solder
ball
UBM
Contact pad
RDL2
Dielectric2
RDL1
Dielectric1
EMC
KGD
Al Pad
Passivation
TiCu
97
Process flow of RDLs by Dual Cu damascene method
Si wafer
SiO
2
RIE of SiO2
SiO
2
by PECVD
Photoresist
Strip resist
Spin coat Photoresist
TiCu
Cu
Sputter Ti/Cu and Electroplate Cu
Stepper, Litho.
V01
RDL1
CMP the overburden Cu and Ti/Cu
RIE of SiO2
DL2P
DL2
DL12
DL1
DL01
DL0
Contact Pad
DL2P
V12
RDL1
RDL2
SiO2
V01
Si wafer
Stepper, Litho.
98
Repeat the processes to get RDL2 and contact pad
Lau, CSR, May 2016
Typical SEM Image of RDLs Fabricated by
Dual Cu Damascene Method
Contact Pad
UBM
RDL3
V23
RDL2
V12
RDL1
V01
Si wafer
99
Lau, et al., IMAPS Transactions, 2014
Chip-Last FOWLP with Hybrid-RDLs
Sacrificial layer
KGD
KGD
Cu
Glass Carrier - 1
RDL1
(a) Coated a sacrificial layer on a
glass carrier
Carrier - 2
(e) Chip-to-wafer bonding, underfilling
RDLs
RDL1
Glass Carrier - 1
EMC
KGD
KGD
Cu
(b) Build contact pads, first RDL (RDL1)
with PECVD/ Cu-damascene/CMP, and the
rest RDLs with polymer/Cu-plating/etching
Carrier - 2
Carrier - 2
(f) EMC compression molding
EMC
KGD
Cu
Glass Carrier - 1
(c) Attach carrier-2
KGD
RDL1
RDLs
Solder ball
RDL1
Carrier - 2
(g) De-bonding of carrier – 2
and solder ball mounting
(d) Laser debond of carrier - 1
100
Lau, CSR, 2018
The development and the integration of the 5μm to 1μm half
pitches wafer level Cu redistribution layers
Mike Ma, Stephen Chen, P. I. Wu, Ann Huang, C. H. Lu, Alex Chen, Cheng-Hsiang Liu, Shih-Liang Peng
Siliconware Precision Industries Co., Ltd. (SPIL)
Email: mikema@spil.com.tw
Hybrid
RDLs
101
IEEE/ECTC2016
Advanced Low Profile PoP Solution with
Embedded Wafer Level PoP (eWLB-PoP) Technology
Seung Wook YOON, Jose Alvin CAPARAS, Yaojian LIN and Pandi C. MARIMUTHU
STATSChipPAC Ltd. 5 Yishun Street 23, Singapore 768442
(Memory)
450µm
520µm
AP
450µm
PCB
Applied Processor (AP)
IEEE/ECTC2012
RDLs
250µm
25µm
190µm
102
TSMC’s InFO (Integrated
Fan-Out) WLP for Apple’s
Application Processor
Chip-Frist (Die Face-Up)
103
FIG. 1I also shows a more detailed view of the die 104 and the wiring layer 108, in accordance with some embodiments. The view of
the die 104 and wiring layer 108 are exemplary; alternatively, the die 104 and wiring layer 108 may comprise other configurations,
layouts and/or designs. In the embodiment shown, the die 104 includes a substrate 124 comprising silicon or other semiconductive
materials. Insulating layers 126 a and 126 b may comprise passivation layers disposed on the substrate 124. Contact pads 128 of
the die 104 may be formed over conductive features of the substrate such as metal pads 127, plugs, vias, or conductive lines to
make electrical contact with electrical components of the substrate 124, which are not shown.
Lau, PDC ECTC2015
Key Components in iPhone 6 Plus
iPhone 6S/6S Plus
Wirebond
150µm-pitch
staggered
C4 bumps
3-layer Coreless substrate
A9
2GB LPDDR4
Wirebond
LPDDR4
90µm
2-2-2
build-up
substrate
Package Substrate for LPDDR4 3-layer Coreless
A9
Package Substrate for A9 processor 2-2-2 Build-up
A9 application processor fabricated by
14/16nm Fin-FET process technology
105
Lau_Chip Scale Review, 2015
PoP for the Mobile DRAMs + Application Processor
of iPhone 7/7+ (InFO)
PoP
SoC
3-Layer Coreless
Package Substrate
Wirebond
Molding
Memory
15.5mm x 14.4mm
Memory
Solder
Ball
Underfill
EMC
AP A10
TIV
3RDLs
11.6mm x 10.8mm
x 165µm
15.5mm x 14.4mm x 825µm
Solder Ball
Mobile DRAM
3L Coreless substrate
Underfill
DAF
AP A10
Underfill
Underfill
Solder
Ball
386 balls at 0.3mm pitch
EMC
TIV
(Through
InFO Via)
RDLs
386 balls at 0.3mm pitch
386 balls at 0.3mm pitch
Underfill
Solder
Ball
~1300 solder balls at 0.4mm pitch
PCB
Advantages of FOW/PLP
 Wafer bumping (solder bump) is gone
 Flip chip assembly is gone
 Underfill dispensing and curing are gone
 Package substrate are gone
 Better thermal performance
 Better electrical performance
 Thinner package
 Low cost
107
Pop for the Mobile DRAMs + Application Processor
of iPhone X/8/8+ (InFO)
Over Mold
DRAMs
DRAMs
3-Layer Coreless
Package Substrate
Pop
Solder
Ball
Underfill
TIV
Wirebond
EMC
Application
Processor
4RDLs
Solder Ball
PCB
13.9mmx14.8mmx790mm
 3RDLs to 4RDLs
 W/S: 5µm to 10µm
Molding (140µm)
Wire bond
A11 AP (150µm)
Memory (140µm)
Coreless Substrate (90µm)
Solder Ball
Underfill
Underhill
A11
EMC
TIV
4RDLs
(50µm)
4RDLs
Underfill
386 balls at 0.3mm pitch
Capacitor
PCB
Solder Ball
Lau, Chip Scale Review, 2018
108
PoP for the Mobile DRAMs and
Application Processor (AP) of iPhone XS
PoP
A12 AP SoC
3-Layer Coreless
Package
Substrate
Wirebond
Over Mold
Memory
Memory
Solder Ball
Underfill
EMC
TIV
A12 AP
RDLs
9.9mm x 8.4mm
13.4mm x 14.4mm x 0.815mm
3-Layer Coreless
Package
Substrate
Solder bumped
flip chip IPD
Memories
cross-stacked
with wirebonds EMC
Solder Ball
A12 AP (150µm)
RDLs
EMC
PCB
A12 AP
Solder balls at
0.35mm-pitch
RDLs
Solder balls
Solder bumped
flip chip IPD
 The pitch of the solder balls is 0.35mm. It will go down to 0.3mm soon.
 The size of the solder balls is 200µm. It will go down to 150µm soon.
109
Samsung’s Roadmap for Mobile and Server/HPC
FO-
IEEE/ECTC2018
110
Samsung’s AP Chip-Set for Smartwatches - FOPLP
8mm x 9.5mm x 1mm
Memory ePoP
2DRAM, 2NAND, 1Controller
3L Package substrate (90µm)
3L Organic
Substrate
ABF
Underfill
AP
Solder Ball
ABF
4RDLs
PMIC
Solder Ball
PCB
Package substrate
3L Organic
Substrate
Shipped in 2018
Underfill
AP
Solder Ball
(3.57mmx5.18mm)
ABF
RDL
Memory
ePoP
RDL Solder Ball
PMIC
ABF
(3.7mm x 5.8mm)
Samsung’s AP Chip-Set for Smartwatches - FOPLP
3L Package substrate
AP
Underfill
Solder Ball
ABF
Memory
ePoP
PMIC
RDLs
RDL Solder Ball
ABF
ABF
3L Substrate
AP (3mmx3mm)
RDLs
ABF
Photo source: Prismark/Binghamton University
HTC Desire 606W (SPREADTRUM SC8502)
Package Size: 7.4 x 7.4 x 0.71mm
Modem (2.8 x 2.8mm)
430µm
115µm
Apps Processor (3x3mm)
PCB
Over
Mold
2 RDLs: 20µm L/S
230 solder balls @0.4mm pitch
Shipped in 2013
Samsung’s Roadmap for Mobile and Server/HPC
FO-
IEEE/ECTC2018
114
Study of Advanced Fan-Out Packages for Mobile Applications
Taejoo Hwang, Dan (Kyung Suk) Oh, Eunseok Song, Kilsoo Kim, Jaechoon Kim, Seokwon Lee
Package development team, Semiconductor R&D center
Samsung Electronics CO., LTD.
(a) Preparing glass carrier
Glass Carrier
(e) Molding & grinding
(b) RDLs deposition
RDLs
AP
Glass Carrier
EMC
Memory
Glass Carrier
(c) Au plating, Sawing, RDL tests
(f) Carrier detach
AP
Memory
Glass Carrier
(g) Solder ball attach
(d) Bonding & Underfilling
µbump
AP
Underfill
AP
Memory
Glass Carrier
AP & DRAM
are side-byside not PoP
Solder ball
 Samsung’s side-by-side (SbS) for smartphonts
 Chip-Last (RDL-First) Process Steps for AP + Memory
115
IEEE/ECTC2018
TSMC’s InFO_AiP Technology for High Performance
and Compact 5G Millimeter Wave System Integration
C. -T. Wang, T. -C. Tang, C. -W. Lin, C. -W. Hsu, J. -S. Hsieh,
C. -H. Tsai, K. -C. Wu, H. -P. Pu, and Douglas C. -H. Yu
R&D, TSMC, Ltd. 168, Park Ave. 2, Hsinchu Science Park, Hsinchu, Taiwan 300-75,
Email: ctwangm@tsmc.com
RDLs
EMC
Solder Ball
Antenna Patch
RF Chip
RDLs
InFO_AiP (Integrated Fan-Out_Antenna-in-Package)
IEEE/ECTC2018
116
TSMC’s InFO_AiP Technology for High Performance and
Compact 5G Millimeter Wave System Integration
RDLs
InFO_AiP
EMC
Antenna Patch
RF Chip
RDLs
Solder Ball
Antenna Patch
Flip Chip on
Substrate with
Underfill
EMC
Underfill
RF Chip
RDLs
Package Substrate
Solder Ball
Solder Ball
THE TRANSMISSION LOSS FOR RDL AND SUBSTRATE TRACE AT 28 AND 38GHZ
IEEE/ECTC2018
Frequency
InFO RDLs
Substrate Trace
28GHz
0.175dB/mm
0.288dB/mm
38GHz
0.225dB/mm
0.377dB/mm
InFO_AiP (Integrated Fan-Out_Antenna-in-Package)
117
FOWLP for RF Chip and AiP (Antenna-in-Package)
for 5G Millimeter Wave System Integration
Desired direction of radiation (θ = 0o)
Backside protection
RF CHIP
Fan-In area
Solder Balls
Fan-Out antenna area
RDLs
Antenna
Cavity
PCB
Copper Layer (Reflector)
The grounded area on the PCB acts as additional reflector. In order to
increase the reflector performance, a cavity can be placed beneath the
antenna into the PCB, which also increases the antenna bandwidth.
118
High Density 3D Fanout Package for
Heterogeneous Integration
Shin-Puu Jeng, S. M. Chen, F. C. Hsu, P. Y. Lin, J. H. Wang, T. J. Fang, P. Kavle, Y. J. Lin
Taiwan Semiconductor Manufacturing Company (TSMC), Ltd. Hsinchu, Email: spjeng@tsmc.com
HBM (high bandwidth memory)
TSV
DRAM
RDLs
RDLs
RDLs
RDLs
RDLs
RDLs
TMV
RDLs
TMV/TIV or
Cu-pillar
RDLs
Solder bump
119
IEEE2017 Symposium on VLSI
3D Heterogeneous Integration with Multiple Stacking
Fan-Out Package
Feng-Cheng Hsu*, Jackson Lin, Shuo-Mao Chen, Po-Yao Lin, Jerry Fang, Jin-Hua Wang, Shin-Puu Jeng
Taiwan Semiconductor Manufacturing Company (TSMC)
Hsinchu, Taiwan 30077, R.O.C., *fchsuh@tsmc.com
Chip
Microbumps
Cu-Pillars
Chip
Cu-Pillars
Microbumps
Chip
IEEE/ECTC2018
Line width = 1.5µm
120
Cross Section of Intel's Modem Chipset for iPhone XS
DRAM (75µm)
Cu-Pillar
with solder
cap
9mm
Mold
DRAM
Baseband AP
8mm
Intel PMB9955 Modem
chipset which
consists Intel’s
XMM7560 LTE (long
term evolution)
Advanced Pro 4G LTE
baseband application
processor (AP) and a
DRAM.
9mm
Wirebond
3L ETS
PMB9955
Solder ball
PCB
Cu-Pillar with solder cap
8mm x 9mm x 580µm
Die attach (20µm)
Baseband AP (75µm)
115µm
130µm
Solder ball
0.35mm
Molded Underfill
3L ETS
(embedded
trace substrate)
20µm L/S
Heterogeneous Integration of RF Chip, Baseband
AP, DRAM, and AiP
Antenna Patch
Side-view
RDLs
RF Chip
Baseband AP
RDLs
Solder Balls
Antenna Patch
Antenna
Patch
Baseband AP
Top-view
RF Chip
DRAM
Antenna Patch
Thermal Performance of FOWLP
Rja (Junction-to-ambient thermal resistance)
Chip thickness = 150µm
Power = 5W
Max. temperature = 101.5oC
Min. temperature = 89.9oC
Rja (oC/W)
The thinner the chip the higher the Rja
(i.e., the lower the thermal performance)
Chip Thickness (µm)
IEEE Trans., CPMT,
2017, pp. 1729-1738.
123
Issues of FOPLP
 Most OSATs and Foundries already have the necessary equipment for FOWLP.
For FOPLP, new capital will have to be expended on newly developed
equipment.
 Inspection of wafers is a well-known process. FOPLP inspection must be
developed.
 The yield of FOWLP is higher than that of FOPLP. (Assuming the size of panel
is larger than that of wafer.)
 The cost advantages of panel over wafer need to be carefully determined. (Yes,
the throughput is higher, but the pick & place time is longer, the EMC
dispensing time is longer, and the yield is lower.)
 A fully loaded high yield wafer line might be cheaper than a partially loaded low
yield panel line.
 The panel equipment takes longer to clean than wafer equipment.
 Unlike FOWLP, the FOPLP is for medium chip size and line width and spacing.
 If indeed, the panel processing is developed and is high yield for fine line width
and spacing, there is a chance to produce a major oversupply of capacity.
 Lack of panel standard for FOPLP, thus the equipment suppliers cannot make
the equipment.
 There are only a few companies in the world capable of doing panel. You must
have a materials background, equipment automation support and IP. You also
need to manage the dimensional stability and yield of the panel in a large 124
Lau, CSR, 2018
format.
Embedded Chips in:
 Laminated Substrates
 Glass
 Silicon
125
TI’s embedded chip in a rigid substrate
of a DC/DC (power) convertor
PicoStarTM
Capacitor
Inductor
Capacitor
IC Chip
Substrate
Solder Ball
DC/DC convertor IC chip embedded
in the substrate
Packaged by AT&S’ ECP® in-PWB
embedding process
It is a step down converter with a
maximum current of 600 mA.
Embedded
chip
X-ray image
after solder
and SMD
component
removal126
Lau, PDC, ECTC2015
TEK’s SESUB (Semiconductor Embedded in Substrate)
Highly Integrated
Power Management
Unit
127
Lau, PDC, ECTC2015
GIT’s Chips Embedded in Glass Substrate
Glass panel (70µm)
with holes (cavities)
Adhesive
Glass panel (50µm)
Chips (face-up) in
glass cavities
Polymer on both
sides of glass
Backgrind the
polymer to expose
the Cu bumps
Dielectric and
conductor layers
(RDLs)
Solder Ball
mounting
128
IEEE/ECTC2017
Maxim’s chips embedded in silicon wafer. (a) Cavities formation by KOH. (b) P&P
chips (face-up) in cavities. (c) RDLs fabrication and solder balls mounting
129
US20140252655A1, filing date: June 28, 2013
Fanout Flipchip eWLB (embedded Wafer Level Ball Grid
Array) Technology as 2.5D Packaging Solutions
Seung Wook Yoon, Patrick Tang, Roger Emigh, Yaojian Lin, Pandi C. Marimuthu, and Raj Pendse
STATSChipPAC Ltd., 5 Yishun Street 23, Singapore 768442
TSV interposer
µbump
Underfill-2
Analog
Logic
Underfill-1
C4 bump
Solder Ball
Organic Substrate
 No µbump, underfill-1, and TSV interposer.
 The RDLs are made by fan-out technology.
Underfill-2
IEEE/ECTC2013
RDLs
EMC
Logic
Solder Ball
Analog
C4 bump
Organic Substrate
130
Wafer Warpage Experiments and Simulation for
Fan-out Chip on Substrate (FOCoS)
Yuan-Ting Lin, Wei-Hong Lai, Chin-Li Kao, Jian-Wen Lou,Ping-Feng Yang, Chi-Yu Wang, and Chueh-An
Hseih*
Advanced Semiconductor Engineering (ASE), Inc.
e-mail: Adren_Hsieh@aseglobal.com
ASE’s FOCoS
CoWoS
Die1
EMC Microbumps
+ Underfill
Die2
EMC
Die1
TSV-interposer + RDLs
Die2
RDLs
Package Substrate
C4 bumps
Solder Balls
Package Substrate
Underfill
Underfill
Solder Balls
C4 bumps
EMC
EMC
Chip1
RDLs
C4 bumps
Chip2
Chip1
RDLs
C4 bumps
Chip2
Package
Substrate
Solder
Balls
Underfill
Package
Substrate
131
IEEE/ECTC2016
RDLs
131
A Novel System in Package with Fan-out WLP
for high speed SERDES application
Nan-Cheng Chen, Tung-Hsien Hsieh, Jimmy Jinn, Po-Hao Chang, Fandy Huang,
JW Xiao, Alan Chou, Benson Lin
Mediatek Inc
Hsin-Chu City, Taiwan
IEEE/ECTC2016
Low Cost Si-less RDL Interposer Package for High
Performance Computing Applications
Kyoung-Lim Suk*, Seok Hyun Lee, Jong Youn Kim, Seok Won Lee, Hak Jin Kim, Su Chang Lee,
Pyung Wan Kim, Dae-Woo Kim, and
Dan
(Kyung Suk) Oh
HBM2
HBM2
Package Development Team
Samsung Electronics Co.,
Ltd.
GPU
Gyeonggi-do, Republic of Korea
*klim.suk@samsung.com
Jung Soo Byun
HBM2 HBM2
PLP Development Team
Samsung Electro-Mechanics Co., Ltd.
Gyeonggi-do, Republic of Korea
js0.byun@samsung.com
CoWoS
C4 Bump
TSV-Interposer
Underfill
EMC
HBM
Logic
µBump
RDLs
Package
Substrate
µBump
C4 Solder
Bump
Solder Ball
IEEE/ECTC2018
Solder Ball
Package
Substrate
133
Samsung’s Roadmap for Mobile and Server/HPC
FO-
IEEE/ECTC2018
Samsun’s Fan-out on Substrate
(Si-less RDL interposer )
HBM2 HBM2
GPU
RDL Formation
C4 bump
Grinding & bump attach
HBM2 HBM2
µbump
Package
substrate
Underfill
Multichip bonding
Solder ball
RDL on substrate / ball mount
EMC
Encapsulation
IEEE/ECTC2018
Lid attaching
TSMC’s TSV-less Interposer (InFO_oS) for
Heterogeneous Integrations
CHIP1
CHIP2
EMC
RDLs
C4 Bump
Package Substrate
Solder Ball
Solder Ball
PCB
InFO_oS (Integrated Fan-Out on Substrate)
SEMICON Taiwan, September 2018
TSMC’s TSV-less Interposer (InFO_MS) for
Heterogeneous Integrations
*Memory Cube
without TSV
Memory Cube
with TSVs TSV
EMC
Logic
RDLs
Logic
EMC
C4
Bump
Package Substrate
Package Substrate
PCB
InFO_MS (Integrated Fan-Out with Memory on Substrate)
*The memory cube without TSV is fabricated by TSMC’s InFO WLP method.
137
SUMMARY and TRENDS in FOW/PLP
 Chip-first is a good choice for packaging semiconductor ICs such as baseband,
RF/analog, PMIC, AP, and low-end ASIC, CPUs and GPUs for portable, mobile,
and wearable products.
 Chip-last (RDL-first) is potentially suitable for packaging IC devices such as
high-end CPUs, GPUs, ASICs, and FPGAs (field programmable gate arrays) for
super computers, servers, networking, and telecommunication products.
 Chip-first and die face-down is the most simple and low cost formation. In
general, this applies to smaller chips and the line width and spacing of the
metal lines of RDLs are ≥10μm.
 The process steps of chip-first and die face-up are a little more complicated
than chip-first and die face-down and thus slightly higher cost. In general, this
applies to larger chips and the line width and spacing of the metal lines of
RDLs are ≥μm.
 The process steps of chip-last or RDL-first are the most complex and high cost.
However, it applies to very large chips and the line width and spacing of the
metal lines of RDLs are < 5μm to submicron. Thus, this process can only be
afforded by very-high density and performance applications. On the other hand,
for high-density and high-performance applications, why insist on the FOWLP
technology because there are many other packaging alternatives?
 Organic RDLs fabricated by polymer (either photosensitive or not) and ECD Cu
+ etching is the most common method for FOWLP by OSATS or even foundries.
It can be applied to the chip-first and chip-last formations.
138
SUMMARY and TRENDS in FOW/PLP
 Inorganic RDLs fabricated by PECVD and Cu damascene + CMP is a backend
semiconductor method for the chip-last FOWLP formation. By viewing the
change of the line width and spacing (from 5μm to 10μm) of the metal lines of
RDLs of the application processor chipsets (from A10 of iPhone 7 to A11 of
iPhone 8), the chance of using PECVD and Cu- damascene + CMP in fabricating
the RDLs for FOWLP is very slim (may be only for niche applications). If there is
a need for inorganic RDLs, however, why insist on the FOWLP technology?
 Hybrid RDLs fabricated by inorganic RDL first and then organic RDLs are a
mixed method for the chip-last FOWLP formation. Again, if there is a need for
hybrid RDLs, why insist on the FOWLP technology?
 RDLs by pure PCB/LDI technology is for chip-first FOPLP. There is not any
semiconductor equipment required and is the highest throughput and lowest
cost technology. However, the chip sizes are small (< 8mm x 8mm) and the line
width and spacing of the metal lines of RDLs are large (≥ 10μm).
 In order to increase the throughput and yield and reduce the cost with FOPLP
some important issues (should be noted and resolved) have been highlighted.
 Warpage is a critical issue for FOW/PLP. Depending on the formation of the
package and the number of RDLs, there are a few different warpages affecting
the FOW/PLP process.
139
SUMMARY and TRENDS in FOW/PLP
 What are the maximum allowable warpages? The rule of thumb is for a 300mm
reconstituted wafer, the maximum allowable warpage of the reconstituted wafer
is 1mm, but 0.5mm is preferred for high yield. The maximum allowable warpage
of the individual package (≤ 20mm × 20mm) is 0.2mm, but 0.1mm is preferred
for high yield.
 The junction-to-ambient thermal resistance (Rja) of a 10mm × 10mm chip in a
13.42mm x 13.42mm package is higher (i.e., the lower the thermal performance)
for thinner chips. This is because of the inferior thermal spreading capability of
thinner chips.
 Because of the drive of 5G, AI, and ML, there are many opportunities for
FOWLP to house (package) various semiconductor devices for mobile, HPC,
self-drive cars, and IoTs applications. For examples:
 by using the chip-first FOWLP to eliminate the TSV-interposer for multiple
flip chips on a package substrate,
 by using the chip-last FOWLP to eliminate the TSV-interposer for SoC and
HBM cubes on a package substrate,
 by using the chip-first FOWLP to construct the HBM cubes without TSVs,
and
 by using the fan-out for the RF chip in AiP for 5G integration leads to lower
transmission loss.
140
Thank You Very Much for Your
Attention!

141