5.1. Device Structure and Operation ( n- Channel)
 Metal Oxide Semiconductor Field Effect Transistor
 Physical Structure: Metal / Oxide / Semiconductor
 Parallel plate Capacitor
 Controlled by Electric Field
 Four Terminal Device: Gate(G), Source(S), Drain(D), Body (B)
 n-channel MOSFET and p-channel MOSFET
5.1.3. Creating a Channel for Current Flow
(n - channel MOSFET)
When Source and Drain are grounded & VGS applied
(i) Positive vGS to the gate terminal, causing a positive charge build up along metal electrode.
Presence of Electric Field on MOS structure
(ii) This “build up ( E field)” causes free holes ( in p-type SC) to be repelled from region under oxide.
(iii) This “migration” results in the uncovering of negative bound charges
(iv) The positive gate voltage also attracts electrons from the n+ source and n+ drain regions
(v) Once a sufficient number of electrons accumulate under oxide, an n-region is created.
 connecting the source and drain regions
 Inversion
(vi) This inverted n-region ( Channel ) provides path for current flow between D and S.
: CHANNEL formation by VGS



Threshold voltage (Vt) : The minimum value of vGS
required to form a conducting channel between D and S
Vtn for n- MOSFET, Vtp for p-MOSFET
Vt : 0.7 – 1.0V for n-MOSFET
5.1.4. Applying a Small vDS ( < ~ 50mV)






with positive vGS & vGS > vtn , a channel is formed
Electrons can move from source to drain through channel by small vDS
Current iD from drain to source
Current iD is proportional to the number of electrons in the channel
The channel is controlled by the effective voltage (overdrive voltage : vOV = vGS - vtn )
The channel is acting as a variable linear resistor whose value is controlled by vOV ( = vGS - vt )
Increasing
vGS
i D  [  n Cox (
W
)  (VGS  Vtn )]  VDS  k n (VGS  Vtn )  VDS
L
MOSFET in Linear Mode
k n   n Cox 
W
L
5.1.5. as vDS is Increased
(i) with positive vGS & vGS > vtn , a channel is formed
(ii) vDS applied between S and D appears as voltage drop across n-channel(variable linear resistor)
(iii) voltage decreases from vGS at the source end of channel to vGD at drain end
 Voltage at the Source end: vGS
 Voltage at the Drain end: vGD = vGS – vDS
(iv) Inversion layer depends on electric field ( Gate to channel )
increasing vDS will result tapered channel
(v) At the point when vDS = vGS - vtn , the channel is pinched off at the drain end
as v DS increases
i D   n Cox (
W
1
1
2
2
)[(VGS  Vtn )VDS  VDS ]  k n [(VGS  Vtn )VDS  VDS ]
L
2
2
MOSFET in Triode Mode
pinch-off
5.1.6. Operation for vDS  vOV
(i)
Further increase in vDS has no effect on iD
: Saturated current iD
(ii) Channel is still pinched off
i D   n Cox (
W
)(VGS  Vtn ) 2  k n (VGS  Vtn ) 2
L
MOSFET in Saturation Mode
5.2.4. Channel Length Modulation Effect
When VDS  VGS – Vtn : Saturation Mode


pinch-off point moves slightly away from the edge of drain & creates new depletion region.
The effective channel length reduces with VDS





Channel length modulation
Voltage across the (now shorter) channel will remain at (vOV).
Electrons reach at pinch off point will be swept by electric field
the length of the n-channel will decrease.
Early Voltage : VA
ID 
1
k n (VGS  Vtn ) 2 (1  VDS )
2
I – V Characteristics of n-MOSFET

iD depends on the relationship between vDS and vOV ( = VGS – V tn)
 vDS  vOV ( = vDS – vtn )
 Linear Mode
i D  [  n Cox (
W
)  (VGS  Vtn )]  VDS  k n (VGS  Vtn )  VDS
L
 vDS  vOV ( = vDS – vtn )
 Triode Mode
i D   n Cox (
W
1
1
2
2
)[(VGS  Vtn )VDS  VDS ]  k n [(VGS  Vtn )VDS  VDS ]
L
2
2
 vDS  vOV ( = vDS – vtn ) : Saturation Mode
i D   n Cox (
W
)(VGS  Vtn ) 2  k n (VGS  Vtn ) 2
L
 Considering Channel Length Modulation Effect
iD 
1
k n (VGS  Vtn ) 2 (1  VDS )
2
5.2.2. The iD-vGS Characteristic (n-MOSFET)
 MOSFET amplifier will be operated in
Saturation mode
 In saturation, the drain current (iD)
 dependent on vGS
 independent of vDS
 In effect, the MOSFET in Sat. mode becomes a
voltage-controlled current source.
1
I D  k n (VGS  Vtn ) 2
2
in Sat. mode
in Sat. mode
5.2.2. The iD-vGS Characteristic (Sat. mode)
large-signal equivalent circuit in Sat. Mode
 Voltage Controlled ( vGS ) Ideal current source
 Infinite output resistance
ID 
1
k n (VGS  Vtn ) 2
2
5.2.4 Finite Output Resistance in Sat. Mode
ID 
1
k n (VGS  Vtn ) 2 (1  VDS )
2
Where,  
Considering channel length modulation effect
V
1
, ro  A
VA
ID
5.2. MOSFET
 Two types of MOSFET
 Enhancement MOSFET
 Depletion mode MOSFET
n channel enhancement MOSFET
p channel enhancement MOSFET
Complementary MOS (CMOS)
n channel depletion MOSFET
Example 5.6: MOSFET in DC
 Analyze the circuit to determine the voltages at all nodes and the current
through all branches.
 Vtn = 1V and k’n(W/L) = 1mA/V2.
 Neglect the channel-length modulation effect (assume  = 0).
Example 5.3: NMOS Transistor
 Design the circuit of Figure 5.21.
 Determine the values of RD and RS
 the transistor operates at ID = 0.4mA and VD = +0.5V.
 Vtn = 0.7V, nCox = 100A/V 2, L = 1m, and W = 32m.
 Neglect the channel-length modulation effect (assume  = 0)
5.4.1. Voltage Amplifier with MOSFET
Utilizing transconductance amplifier (MOSFET)

as a voltage amplifier
Input : vGS
Output: vDS (RD converts ID to a voltage)
voltage transfer characteristics
 vGS < Vtn : cut off
 vOV = vGS – Vtn < 0
 ID = 0
 vout = vDD
 Vtn < vGS < vDS + Vtn : saturation
 vOV = vGS – Vtn > 0
 ID = ½ kn(vGS – Vtn)2
 vDS >> vOV
 vout = VDD – IDRD
MOSFET amplifier with input vGS and output vDS
VDS  VDD  iD RD
output
Function of VG
 vDS + Vtn < vGS < VDD : triode
 vOV = vGS – Vtn > 0
 ID = kn[(vGS – Vtn ) vDS – ½vDS2]
 vDS > vOV
 vout = VDD – IDRD
5.4.3. Biasing the MOSFET for Linear Amplification
 Linear region in VTC for linear gain
 Slope in VTC = gain
 Appropriate biasing technique
 dc voltage vGS is selected to obtain operation
at point Q within segment AB (near linear)
VDS  VDD  iD RD
 VDD  1 k n (VGS  Vtn ) 2 RD
2
 Achieving linear gain
(i) Bias MOSFET with dc voltage VGS
(ii) Superimpose amplifier input (vgs) upon VGS.
(iii) vds is linearly proportional to small-signal input vgs
vGS  t   VGS  vgs  t 

vds  t   vgs  t 
5.4.3. Biasing the MOSFET to Obtain Linear
Amplification
dv DS
Av 
dvGSd
1
d (VDD  k n (vGS  Vtn ) 2 RD )
2

dvGS
@ VGS
 k n (VGS  Vtn ) RD
 Voltage gain Av
 negative
 proportional to
 load resistance (RD)
 transconductance parameter (kn)
 overdrive voltage : VGS – Vtn = VOV
Av  k n (VGS  Vtn ) RD  
I D RD
(V GS Vtn )
2
: Voltage drop across RD
: Half of overdrive voltage
Example 5.9: MOSFET Amplifier
 Consider the amplifier circuit shown.
 Vtn = 0.4V, k’n = 0.4mA/V2, W/L = 10, and  = 0.
 VDD = 1.8V, RD = 17.5k, and VGS = 0.6V.
 For vgs = 0 (and hence vds = 0), find VOV, ID, VDS, and Av.
 What is the maximum symmetrical signal swing
allowed at the drain? Hence, find the maximum
allowable amplitude of a sinusoidal vgs.
5.5. Small-Signal Operation and Models
VDS  VDD  iD RD
 linear amplification via…
 Operation in saturation region
 Utilization of small-input signal
ID 
1
k n (VGS  Vtn ) 2
2
vGS  VGS  v gs
iD 
1
k n [(VGS  v gs )  Vtn ]2
2
When,
input voltage to be
amplified : vgs
( small signal vgs )
1
k n (VGS  Vtn ) 2  k n (VGS  Vtn )  v gs
2
 I D  id : DC + ac

dc bias voltage : VGS
Transconductance gm [ A/V ]
gm 
v gs  2(VGS  Vtn )
v gs
id
 k n (VGS  Vtn )
id  k n (VGS  Vtn )  v gs
Drain current due to small signal vgs
5.5.3. The Voltage Gain ( Av )
v DS  VDD  RD iD  VDD  RD ( I D  id )
 VDD  RD I D  RD id  VDS  RD iD  VDS  vds
vds   RD id   RD ( g m v gs )
Av 



output vds

  g m RD
input
v gs
Output signal is shifted from input by 180.
Input signal vgs << 2(VGS – Vt)
Operation should remain in Saturation region
5.5.5. Small-Signal Equivalent Models
Hybrid -  model

T - model
FET behaves as VCCS.
 Accepts vgs between gate and source
 Provides current (iD) at drain
 Input resistance is high
 b/c gate terminal draws iG = 0
 Output resistance is high
5.5.6. The Transconductance gm
gm 
v gs
id
 k n (VGS  Vtn )
W
VOV
L
(eq5.56) gm  2kn W / L ID
(eq5.55) gm  kn
gm 
i D
v gs
(eq5.57) gm 
vGS VGS
2ID
VOV
5.7 Biasing a MOS amplifier
Basic arrangement
Two power supplies
Single supply
With feedback RG
With coupling Cap.
With constant
Current source
5.6 Basic MOSFET Amplifier Configurations
(not showing Biasing circuit)
 Design of transistor amplifiers
 Bias the transistor to operate at an
appropriate point in the saturation region.
 Voltage Amplifier
 Three intrinsic electrical properties
 Open Loop voltage Gain: Avo
 Input Resistance: Rin
 Output Resistance: Rout
 Voltage Gain: Av
 Overall gain : Gv
5.8.4 Common Source Amplifier




Input resistance R in = RG
Output Resistance Rout = RD
Open Circuit Voltage Gain: -gmR D
Overall Voltage Gain
Gv  





RG
g m ( RD RL )
RG  Rsig
High Input Resistance
Reasonably High Voltage Gain
High Output Resistance
Degeneration Resistor RS
Most widely used MOSFET Amp.
CC1 & CC2 : Coupling capacitors
Not to disturb the operating point (Q point)
CS : Bypass capacitor
Force signal current passes through Cs
Bypass the high output R of current source
5.8.4 Common Gate Amplifier




Input resistance R in = 1/gm
Output Resistance Rout = RD
Open Circuit Voltage Gain: gmR D
Overall Voltage Gain
Gv 




1
1
gm
 Rsig
( RD RL )
Non inverting
Reasonably High Voltage Gain
Low Input Resistance
High Output Resistance
5.8.4 Common Drain Amplifier
(Source Follower)




Input resistance R in = RG
Output Resistance Rout = 1/gm
Open Circuit Voltage Gain:  1
Overall Voltage Gain
Gv 




RG
RL

RG  Rsig RL  1
gm
High Input Resistance
Voltage Gain lower than unity
Low Output Resistance
Voltage Buffer