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Incremental-Compile

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Incremental Compile
John Blaine (SW APPS) + Ron Plyler (SW Marketing)
• Target Problems to Solve
Agenda
• Running the Incremental
Compile Flow
• Typical Use Cases
• Analyzing Results
• Roadmap
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Solving Problems with Incremental Compile
 Customer says
 “I have made a small change and my timing has degraded significantly”
 “Your implementation tools take forever to run”
 Solution is Incremental Compile
 Prevent performance swings after small design changes
 Average 2x compile time speedup
 Additional flow option in timing closure
 When is 1 hour ≠ 1 hour
 When you get an extra build at the end of the day
 When you don’t have to work your weekend
 When you meet your deadline v when you do not
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2017.1 QoR Predictability Success Rates of Incremental Compile Flow
Ref run with explore in placer/physopt/router
Incremental run with default placer/physopt/router
95%
90%
92%
90%
88%
87%
85%
81%
79%
80%
80%
73%
75%
70%
63%
65%
59%
60%
55%
50%
Ref Met
Ref Viol
Ref Viol, within 10 ps
2016.4
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Ref Viol, within 50 ps
2017.1
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Ref Viol, within 1% Fmax
Customer Obstacles to Using Incremental Compile
 A few customers raise opposition to using the flow
 Typical issues:
 “Reference DCP is a binary source file”
 “DCP file is too large to check in to version control systems”
 “When generating from scratch, I do not want to run implementation more than once”
 Responses
 Do not commit references to version control, files can be recreated
 Run Incremental Compile in parallel to standard runs
 Regularly update the reference DCP with the standard run DCP to break the chain
 Then ask “Are you OK using the Incremental Run in the lab while you close out timing on the standard runs?”
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Running the Incremental Compile Flow
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Incremental Compile Overview
 Take a previous run Reference checkpoint
 Reuse P&R data on the Incremental Run
Reference
Design
Place & Route
Incremental
Design
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Reference
DCP
read_checkpoint
-incremental
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Place & Route
Incremental
DCP
Incremental Flow “Teardown” - What’s Inside...
opt_design
read_checkpoint
-incremental
place_design
phys_opt_design
route_design
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opt_design is run before Incremental begins.
Netlist matching between the incremental and reference netlist
Make timing critical netlist modifications upfront
Matched cells are placed and matched nets are routed
Illegal placement and routing are automatically discarded
Unmatched cells are placed
Unfixed cells can be moved to improve WNS
phys_opt_design runs timing optimization routines like in the standard flow
Unmatched nets are routed
Unfixed nets may be modified to improve timing and congestion
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Flow Characteristics
read_checkpoint -incremental
No
Yes
Cell reuse
over 75%
Low Reuse Mode
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High Reuse Mode
All Standard Flow
Directives
Supported
Default
Directive
Explore
Directive
Target WNS = 0.00
Target WNS = WNS
from Reference DCP
Target WNS = 0.00
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Flow Characteristics – Most Benefit
read_checkpoint -incremental
Cell reuse
over 75%
Low Reuse Mode
High Reuse Mode
All Standard Flow
Directives
Supported
Default
Directive
Explore
Directive
Target WNS = 0.00
Target WNS = WNS
from Reference DCP
Target WNS = 0.00
Reference is timing closed
Netlist matching > 95%
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Incremental Compile – Project Mode
 Practical Recommendations:
 Control in the “Design Runs” Window
 Use useful naming e.g., impl_1_incr
 Run in addition to standard design flow runs
 Launch Incremental Compile runs first
launch_runs [get_runs –filter {INCREMENTAL_CHECKPOINT != “”}]
 Copy reference checkpoints to a new folder
 Name based on opt_design directive names
 Use different checkpoints for different opt_design directives
 Low reuse mode
 Requires invocation from post opt Tcl script
 Requires reports are added manually
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Incremental Compile – Non project mode
Advanced options to use with read_checkpoint –incremental my_chkpt.dcp
Advanced Option
Example Usage
-only_reuse
Reuse specific hierarchy cells
–only_reuse [get_cells my_hier]
Reuse block RAMs
-only_reuse [get_cells -hier -filter {PRIMITIVE_TYPE =~ BLOCKRAM.*.*}]
Reuse DSPs
-only_reuse [get_cells -hier -filter {PRIMITIVE_TYPE =~ ARITHMETIC.*.*}]
-is_fixed
Fixes cells so there is no movement
-dont_reuse
Opposite of only_reuse
-dont_reuse [get_cells do_not_reuse_hier]
-reuse_regions
Reusing physical regions
SLRs
-reuse_regions [list SLR0 SLR1]
Clock regions
-reuse_regions [list X0Y1 X0Y2]
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Maximizing Flow Benefits
 Consider impact of different tool options on
matching
Q: Do all incremental runs need to
reference the same checkpoint?
 synth_design
 Retiming could be significant
A: No! Use different checkpoints to
reference different synthesis and
opt_design options.
 opt_design
 Area v Default directives
 Remove any constraints to over-constrain
placer
 Design is already largely routed at place design. We have accurate
delays.
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Incremental Methodology – Choosing the Reference Checkpoint
Ensure phys_opt_design is “fully” run
Further iterations have little or no benefit
Add Steps to the reference checkpoint run
If WNS < 0.000 run ‘route_design –tns_cleanup’
Match ‘opt_design –directive’ +
synthesis options
Biggest QoR impact
Choose Lowest WNS
For WNS < 0.00, choose lowest TNS
Choose Lowest Congestion Level
For similar congestion, choose lowest % tiles
Choose a reference checkpoint from standard flow run
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Typical Use Cases
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Use Cases
 Hardware Debugging
 Add a new debug core
 Modify (change depth/probes)
 Implementing a bug fix
“Up to 2/3 of a design
cycle can be spent
debugging” – Anon
ALU 2014
 Rewire – use ECO
 Small Design Change
 Add IP block to BD
 Timing Closure
 Modify IP options
 RTL change
 Explore mode can improve by 50-100ps
 Add a pipeline
 Different Strategy
 Add a new module
 Design consistency
 Add a new lane
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Reusing Big Blocks
Some run inconsistency but
design still changing
significantly
 Fix placement of BRAMs,
URAMs and DSPs
 Create anchor points to guide placer
Take a good run and use as a
reference
WNS == 0.00
 No longer need to write out constraints
 Good process
 Need to test strategy against standard
flow
Run Standard Flow
Run Incremental Flow
Compare
Is there benefit?
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Analyzing Results
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Analysis – Identify Poor Reference DCP
 Poor cell matching
 Large design change
 Poor options
 Old or low quality reference
 Vivado version does not match
 Poor target WNS
 Flow divergence
 Get a new reference?
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Analysis – Identify Poor Reference DCP
 -hierarchical
 Gives a hierarchical view of reuse,
just like report_utilization –hier
 Identifies if just a single hierarchy has been modified or whole swathes in the design
 A little bit everywhere could be poor tool option matching
 One hierarchy change is probably a good small design change
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Analysis – Timing report
 Pin Reuse information in timing reports by default
 Tags
 Routing - Routing to the pin was reused
 Placement - Pin’s cell placement was reused, but Incremental used different routing
 Moved - The pin’s cell moved compared to the reference placement, no placement or routing reused
 New - The pin does not exist in the reference design, nothing to reuse
 Turn off using –no_label_reused
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Roadmap
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Roadmap - Incremental Synthesis
Reference Run
 Reuse of synthesis partitions
Incremental Run
RTL Change
 Average 40% reduction in total synthesis runtime
Revised RTL
Reference RTL
 Need to prevent cross boundary optimizations
from changing run to run
Synth Ref
Checkpoint
 Increase in Incremental P&R matched cells by 7%
Synthesis
Incremental
Synthesis
 2017.1 under param control
 2017.3 Target production
Checkpoint
 Improve QoR + runtime
P&R Ref Checkpoint
Place and
Route
 Prototype improved project
Incremental
Place and
Route
mode support
Checkpoint
 More directives for high reuse
Checkpoint
cases
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Call to Action:
 Get customers setup
 Setup parallel runs with Incremental Compile
 Respond to customer opposition
 Especially target large devices and difficult designs + debug phase
 Highlight use cases
 Ensure other runtime saving features are being used
 IP Cache/parallel runs
 Send multiple checkpoints to the factory
 FAE session lab included with memory stick - great for sharing with
customers
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Lastly…
Where to get more Information on this topic?
• Vivado
Design Suite User Guides - UG949, UG1231, UG904, UG986
Rate the Session Content
• Directly on https://www.Xilinx.com/tsc
Provide Presenter Feedback
• Email Presenter with session feedback / additional questions
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Incremental Methodology – Constraints
 Design targets the incremental run constraints
 Should be the same as reference run
 Overconstraining @place_design
 set_clock_uncertainty –setup <time> [get_clocks myclk]
 Should not be set in incremental run
 Tool targets routed WNS from reference checkpoint
 Fully routed paths will be now fail timing
 Unnecessary place and route optimization and less reuse
 Pblocks
 Pblocks have lower priority than reference checkpoint
 Only apply for placing new cells
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