Tel Aviv University
School of EE
ADVANCED SEMICONDUCTOR DEVICES
Lecture 6
MOS transistors
Part 3 – Short channel effects
1
Moore’s Law
• In 1965, Gordon Moore predicted the
exponential growth of the number of transistors
on an IC
• Transistor count doubled
every year since invention
• Predicted > 65,000
transistors by 1975!
• Growth limited by power
[Moore65]
Speed Improvement
• Clock frequencies have also increased exponentially
– A corollary of Moore’s Law
10,000
4004
1,000
8008
Clock Speed (MHz)
8080
8086
100
80286
Intel386
Intel486
10
Pentium
Pentium Pro/II/III
Pentium 4
1
1970
1975
1980
1985
1990
Year
1995
2000
2005
More Moore
• Transistor counts have doubled every 26
months for the past three decades.
1,000,000,000
100,000,000
10,000,000
Transistors
Intel486
1,000,000
Pentium 4
Pentium III
Pentium II
Pentium Pro
Pentium
Intel386
80286
100,000
8086
10,000
8080
8008
4004
1,000
1970
1975
1980
1985
Year
1990
1995
2000
Why?
• Why more transistors per IC?
– Smaller transistors
– Larger dice
• Why faster computers?
– Smaller, faster transistors
– Better microarchitecture (more IPC)
– Fewer gate delays per cycle
5
Scaling
• The only constant in VLSI is constant change
• Feature size shrinks by 30% every 2-3 years
– Transistors become cheaper
– Transistors become faster and lower power
– Wires do not improve
(and may get worse)
• Scale factor S
– Typically S  2
– Technology nodes
6
Dennard Scaling
• Proposed by Dennard in 1974
• Also known as constant field scaling
– Electric fields remain the same as features
scale
• Scaling assumptions
– All dimensions (x, y, z => W, L, tox)
– Voltage (VDD)
– Doping levels
7
Device Scaling
Parameter
L: Length
W: Width
tox: gate oxide thickness
VDD: supply voltage
Vt: threshold voltage
NA: substrate doping
b
Ion: ON current
R: effective resistance
C: gate capacitance
t: gate delay
f: clock frequency
E: switching energy / gate
P: switching power / gate
A: area per gate
Switching power density
Switching current density
Sensitivity
W/(Ltox)
b(VDD-Vt)2
VDD/Ion
WL/tox
RC
1/t
CVDD2
Ef
WL
P/A
Ion/A
Dennard Scaling
1/S
1/S
1/S
1/S
1/S
S
S
1/S
1
1/S
1/S
S
1/S3
1/S2
1/S2
1
S
8
Real Scaling
• tox scaling has slowed since 65 nm
– Limited by gate tunneling current
– Gates are only about 4 atomic layers thick!
– High-k dielectrics have helped continued scaling of
effective oxide thickness
• VDD scaling has slowed since 65 nm
– SRAM cell stability at low voltage is challenging
• Dennard scaling predicts cost, speed, power all
improve
– Below 65 nm, some designers find they must choose
just two of the three
9
Simple MOSFET Performance Metrics
10
Long channel MOSFET
Electrostatic
coupling
Charge injection
over a barrier
11
The short channel effects (SCE)
“VT roll-off”
• |VT| decreases with L
– Effect is exacerbated
by high values of |VDS|
• This is undesirable (i.e. we want to minimize it!) because circuit designers
would like VT to be invariant with transistor dimensions and biasing conditions
12
Qualitative Explanation of SCE
• Before an inversion layer forms beneath the gate, the
surface of the Si underneath the gate must be depleted (to
a depth Wdm)
• The source & drain pn junctions assist in depleting the Si
underneath the gate
– Portions of the depletion charge in the channel region
are balanced by charge in S/D regions, rather than by
charge on the gate
⇒ less gate charge is required to reach inversion
(i.e. |VT| decreases)
13
Short Channel Effect (SCE)
14
The smaller the L, the greater percentage of
charge balanced by the S/D pn junctions:
15
Quantitative Derivation of SCE:
Yau’s Model
• Depletion charge (Qdep) reduction:
• Threshold Voltage Lowering:
• Yau’s model’s assumptions:
Uses geometry relations instead of
solving Poisson’s equation
Assumes channel potential is linear
along lateral (i.e. channel) direction
L.-D. Yau, SSE (1974)
16
First-Order Analysis of SCE
17
SCE (Cont.)
Assume
electrostatic
neutrality
L  L'
L 
2
r
 L   W   rj  WD 
2
j
2
T
2
18
SCE (Cont.)
Assume: WD=WT
 r  L 
j
r
 W   rj  W
2
 L    rj  W
2
j
2

2

2
 W 2  rj2  2rjW


2W
L  r  2rjW  rj  rj   1 
 1


r
j



L  L ' rj 
2W
  1
 1

2L
L 
rj


rj 
L  L ' 2 L  L
L
2W

 1
 1   1
 1

2L
2L
2L
L 
rj

2
j
19
VT Roll-Off: First-Order Model
20
Short channel model
XD,max
21
Explanation
QB  Charge per unit area
 Total ch arg e / Area
 q  Nsub  Volume / area
q  Nsub  AABCD  W
=
L W
22
SCE modeling
23
YAU’s short channel model
• It is an oversimplified model
• It yield qualitative results only
• Should be modified
24
Modeling take care of the potential lowering near the source
25
Short channel effect: Source/channel barrier lowering
26
Drain Induced Barrier Lowering (DIBL -Qualitative
In short-Lg MOSFET:
• x- and y- components of the electric field are coupled
Drain bias will affect the barrier at source/channel
More band bending at given gate bias VT decreases
C. Hu,
Modern Semiconductor
Devices for Integrated
Circuits, Figure 7-5
27
“Quasi 2D” Poisson equation solution at the
high field region near the drain
Gauss law
X d ,maxW  s E y ( y  dy )  X d ,maxW  s E y ( y )  dyW  ox
X d ,max s E y ( y  dy )  X d ,max s E y ( y )  dy ox
 s X d ,max
dE y
dy
  ox
VG  V fb  s
dox
VG  V fb  s
dox
VG  V fb  s
dox
 dyWX d ,max qN sub
 dyX d ,max qN sub
 X d ,max qN sub
 ox VG  V fb   s qN sub



dy  s
X d ,max d ox
s
dE y
28
An approximate solution for the 2D Poisson equation near the
drain:
dE y  ox VG  V fb   s qN sub



dy  s
X d ,max d ox
s
d 2s
 2
dy
dy
dE y
Boundary conditions
d 2 s  ox VG  V fb   s qN sub
 2 


dy
s
X d ,max d ox
s
s (0)  Vbi
The potentials are referred to the source:
 s ( y )  VGT  (Vbi  VDS
l
s ( L)  Vbi  VDS
 y
 L y
sinh  
sinh 

l
l 


 VGT ) 
 (Vbi  VGT ) 
L
L
sinh  
sinh  
l
l
 s dox X d ,max
 3dox X d ,max
 ox
VGT  VGS  Vth
29
SCE modeling – general solution (No current)

 s ( y )  A  sinh 

y
 L y
  B  sinh 
C
l
 l 
l  3d ox X d ,max
L
30
SCE modeling – approximate solutions (As a function of L)
P sub
N+
source
N+
Drain
Vbi
L
31
Derivation for DIBL - A Quasi-2D Model (I)
1. Develop Poisson’s equation in the channel region,
including x- and y components.
32
Derivation for DIBL - A Quasi-2D Model (2)
2. Solve as a function of position (y)
3. Calculate the peak of , which
corresponds to VTH.
33
Short-Channel MOSFET VT
34
Drain induced barrier lowering - DIBL
.DIBL occurs when L is of the same order of magnitude of l
35
Drain Induced Barrier Lowering
(DIBL)
36
VT modeling including DIBL
 s ( y )  VGT  (Vbi  VDS
l  3d ox X d ,max
 y
 L y
sinh  
sinh 

l
l 


 VGT ) 
 (Vbi  VGT ) 
L
L
sinh  
sinh  
l
l
Find the maximum potential:
d s
0
dy
And calculate the gate voltage that makes this potential difference”
2 s   s ,max ( L, VG  VT , VDS )
Vth ( L,VDS )  Vth (long channel ) Vth ( L,, VDS )
Vth ( L,VDS )  3(Vbi  2 B )  VDS   e

L
l
 2 (Vbi  2 B )(Vbi  2 B  Vds )  e

L
l
37
VTH modeling including DIBL
Vth ( L,VDS )  Vth (long channel ) Vth ( L,, VDS )
Vth ( L,VDS )  3(Vbi  2 B )  VDS   e

L
l
 2 (Vbi  2 B )(Vbi  2 B  Vds )  e
Vth ( L,VDS )  VDS  1V   e

L
l
 VDS  e


L
l
L
l
38
Scale Length – A Simplified Knob
1. Tells how closely a MOSFET approaches a “short-channel” device
2. Provides the guideline to scale a MOSFET while maintaining
its electrostatic integrity.
39
VTH vs. Lg Plots: SCE + DIBL
40
State-of-the-Art MOSFET’s
VTH vs. Lg Plots
Intel’s 32nm Bulk
P. Packan, IEDM (2009)
41
State-of-the-Art MOSFET’s
VTH vs. Lg Plots
Samsung’s 20nm Bulk
H.-J. Cho, IEDM (2011)
42
Bulk effect + SCE
43
Sub-threshold Swing Degradation
A 2-D Capacitor Network Model
Gate
Drain
Source
Bulk
Impact of Lg Scaling on SS
(after Prof. M. Lundstrom)
44
IOFF vs. ION Plots
• Generated by “shifting” a device’s VTH under a fixed VDD
• To benchmark the effectiveness of technology advancement.
45
Narrow Channel Effect (NCE)
LOCOS – Local Oxidation
STI – Shallow Trench Isolation.
.Inhomogeneous oxide thickness
46
Narrow Channel Effect (NCE)
LOCOS – Local Oxidation
STI – Shallow Trench Isolation.
• Narrow Width Effect is caused by LOCOS process.
• Reverse Narrow Width Effect is caused by STI process.
• Introduce problems as transistor systematic variations.47
Narrow channel Effect
LOCOS – Local Oxidation
48
Narrow channel Effect
STI – Shallow Trench Isolation.
Reverse narrow width effect
49
State-of-the-Art MOSFET’s
Narrow Width Effects
IBM’s 20nm CMOS
H. Shang, VLSI-T (2012)
Samsung’s 20nm CMOS
H.-J. Cho, IEDM (2011)
50
Pocket implant – reduce leakage
Large angle ion implantation – LATI
Large angle ion implantation Device – LATID
51
Pocket implant – reduce leakage
Long channel
Short channel
52
Total VT change – two options
53
Gate Induced Drain Leakage (GIDL)
Illustration and Band Profiles
Id vs. Vgs Characteristics
T.-Y. Chan, IEDM (1987)
54
Intel’s 32nm Bulk CMOS
IOFF vs. ION Plots
NMOS
PMOS
P. Packan, IEDM (2009)
55
IBM’s 20nm Bulk CMOS
IOFF vs. ION Plots
PMOS
NMOS
H. Shang, VLSI-T (2012)
56
GIDL-Limited IOFF vs. ION Plots
Punch-through
Option 1: Bulk punc- through
58
Punchthrough
Second model: breakdown near the surface
59
Compare Punchthrough to DIBL
DIBL
Punchthrough
60
Parasitic BJT action
61
Lightly Doped Drain Structure
62
Parasitic Source-Drain Resist
63
64
3D MOST modeling
65
Source and Drain Structure
66
Electric Field Along Channel
67