University of Zagreb
Faculty of Electrical Engineering and Computing
2018 Student EMC Hardware
Design Competition
Team Members: Vedran Major, MSc student
Vanja Lapat, MSc student
Josip Bačmaga, PhD student
Faculty Advisor: prof. Adrijan Barić
May, 2018
Contents
1 Introduction
2
2 Overview of the Initial Switching Power
PCB layout . . . . . . . . . . . . . . . . . . .
Measurement setup . . . . . . . . . . . . . . .
Power efficiency calculation . . . . . . . . . .
Oscillator circuit . . . . . . . . . . . . . . . .
Conducted emissions . . . . . . . . . . . . . .
Supply
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3 Power Efficiency Boost
Component selection and modifications
Removing the diodes . . . . . . . .
Output inductor L1 . . . . . . . .
Low-side Schottky diode . . . . . .
Position of Cbyp . . . . . . . . . . .
Final calculation . . . . . . . . . .
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4 Reduction of Conducted EMI
Component selection . . . . . . . . . . . . . . . . . . . . . . . . . .
Input capacitance network: Ci1 , Ci2 , Ci3 connected to the pin
Output capacitance network: Co1 , Co2 . . . . . . . . . . . . .
Capacitors C1 , C2 , C3 . . . . . . . . . . . . . . . . . . . . . .
Input low-pass filter: L3 , L4 and CL1 , CL2 , CL3 , CL4 . . . . .
Ferrite beads L5 , L6 , L7 . . . . . . . . . . . . . . . . . . . . .
Decoupling capacitors C4 , C5 , C6 . . . . . . . . . . . . . . . .
RC snubber: RS and CS . . . . . . . . . . . . . . . . . . . . .
Resistor RO at the oscillator output . . . . . . . . . . . . . .
Zero-Ohm shorts . . . . . . . . . . . . . . . . . . . . . . . . .
Ferrite bead L2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout modifications . . . . . . . . . . . . . . . . . . . . . . . . . .
High-frequency signal trace . . . . . . . . . . . . . . . . . . .
Ground plane slots . . . . . . . . . . . . . . . . . . . . . . . .
Return current path . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap area . . . . . . . . . . . . . . . . . . . . . . . . . .
Input switching loop area . . . . . . . . . . . . . . . . . . . .
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U1-VIN
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5 Final Results
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6 Conclusion
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7 Appendix
List of Measurement Equipment
Bill of Materials . . . . . . . . .
Initial components . . . . .
Added components . . . . .
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1
Introduction
Switching DC-DC converters are more attractive for modern power electronic applications than the linear converters, primarily due to their higher power efficiency [1]. However, due to their switching operation, switching DC-DC converters are a major source
of conducted and radiated emissions, which is the major downside of these power supply
circuits [2]. Due to the rich spectrum of their switching voltage and current waveforms,
the switching DC-DC converters conduct both common-mode and differential-mode noise
currents back to the power line at the harmonics of the switching frequency [3]. Moreover, parasitics of the circuit components and copper traces form the switching loop that
acts as a series resonant circuit. The resonant circuit causes ringing in the switching
voltage and current waveforms which is one of the major causes of the broadband noise
in switching DC-DC converters [4].
The objective of this project is to modify the circuit and layout of the designed power
supply based on a buck controller integrated circuit (IC) using the existing printed circuit
board (PCB) in order to reduce the electromagnetic interference (EMI) measured at the
input of the designed circuit [5]. The evaluation parameters of the power supply circuit
after the modifications are the following [5]:
ˆ peak-peak value at the output of the crystal oscillator should be maintained larger
than 1.8 Vpp,
ˆ power efficiency of the converter should be larger than 85% (input voltage of 12 V,
output voltage of 3.3 V, load current of 1 A),
ˆ conducted emissions from 10 MHz to 350 MHz measured at the input of the power
supply using the existing line impedance stabilization network (LISN) should be as
low as possible.
2
2
Overview of the Initial Switching Power Supply Circuit
The schematic of the initial synchronous power switching power supply circuit is shown
in Fig. 1 and the nominal values of all passive components are given in Table 1. The
circuit is based on a buck controller IC LM3151 from Texas Instruments [6].
VIN
U1
D1
VIN
D2
VCC
Cbyp
R1
Cvcc Cen
HG
BST
QH
Cbst
L1
SW
EN LM3151
LG
SS
FB
GND
VOU T
QL
Co1
GND
D3
+
+ R4
IN VCC
Co2
GND
O
R2
PX
GND
X0
Figure 1: Schematic of the initial switching power supply circuit [5].
Cbyp
10 µF
Table 1: Nominal values of initial passive elements [5].
Cvcc
Cen
Cbst
Co1,o2
L1
R1
R2
4.7 µF 1 nF 470 nF 150 µF 1.6 µH 1 kΩ 300 Ω
R3
2 kΩ
Between VIN and GND is a 12-V voltage source. The high-side transistor QH and
low-side transistor QL are used as switches. The low-pass LC filter is formed by the
inductor L1 and capacitances Co1 and Co2 . This filter is used at the output for filtering
the high-frequency components of the switching waveforms. A buck converter operates in
two states. When the transistor QH is in the on-state, the energy to the load is provided
from the input source VIN . When the transistor QH is in the off-state, the energy to
the load is provided from the energy accumulated in the output stage (inductor L1 and
capacitors Co1 and Co2 ) and the current loop is closed through the low-side transistor QL
that is in the on-state. There is a short period of time between the conduction states of
both transistor switches. During this period, the body diode of the low-side switch QL
is conducting and forms a current loop with LC filter and load.
The switching behaviour is controlled by U1, which is a switcher controller IC for
synchronous step-down converters that operated at the switching frequency of 250 kHz.
The capacitors Cvcc , Cen and Cbyp are used to ensure the proper operation of U1 [6]. The
capacitor Cbst is a bootstrap capacitor used to drive the gate of QH . This capacitor is
charged during the off-time of QH .
The oscillator X0 generates the 100-MHz clock signal at its output pin O that is
routed to the SMA connector PX. The frequency is determined by the resistor R4 .
The diode D1 is used to prevent the DC voltage of the opposite polarity to be applied
to the input of the power supply circuit. The light-emitting diodes (LEDs) D2 and D3
are used as indicators of input and output voltages, while the resistors R1 and R2 are
used to limit the current flowing through LEDs.
The 3.3-Ω load resistor is connected between VOU T and GND.
PCB layout
The top and the mirrored bottom view of the initial switching power supply circuit are
shown in Fig. 2. All the components are placed in the top PCB layer, while the bottom
3
layer consists of the ground plane and few signal traces. The output of the clock oscillator
is routed to the edge-mount SMA connector. The wires used to connect the LISN to the
input of the circuit and load resistor to the output of the circuit are soldered to the square
pads on left and right side of the PCB. The dimensions of the PCB are 109 mm × 66 mm.
The ground planes in top and bottom layer are tied by the through-hole vias that are
not visible in Fig 2 as well as some vias placed on the signal nets. The PCB thickness is
approximately 1.5 mm.
Measurement setup
All the measurements are performed using the setup shown in Fig. 3(a). The circuit
is supplied from a DC voltage source Keysight E3646A, while a 50-Ω oscilloscope Agilent
MSO7034B is used to sense the signal at the output of the oscillator. The conducted
emissions at the input of the power supply circuit are measured using the spectrum
analyzer R&S ESRP EMI Test Receiver. The LISN and power supply boards are placed
on the 20-mm thick styrofoam. The complete setup is placed on the 2000 mm × 1000 mm
copper plane that is electrically connected to the ground potential. The equipment used
to supply the circuit and perform the measurements is also listed in Appendix.
When the oscilloscope is used to sense the generated clock signal, the LISN output is
terminated into a 50-Ω impedance. When conducted emissions are measured using the
spectrum analyzer, the oscillator output is terminated into a 50-Ω impedance.
The LISN and load resistor are connected to the power supply circuit as shown in
Fig. 3(b). The length of the connecting wires and the distance between them are defined
in [5] and are not changed during the measurement procedure. The ground plane of the
LISN circuit is connected to the main copper ground plane by soldering the copper traces.
Power efficiency calculation
In order to estimate the efficiency of the switching power supply circuit, the input
voltage between the nodes VIN and GND, the output voltage between the nodes VOU T
and GND and current at the input of the power supply circuit are measured using the
multimeter and current probe listed in Appendix. The values measured for the initial
power supply circuit are: VIN = 12.00 V, VOU T = 3.28 V, IIN = 398 mA. The resistance
of the load resistor is 3.3 Ω and the power efficiency can be calculated as:
η=
VOU T 2 /RL
3.282 /3.3
=
= 0.683 = 68.3%.
VIN · IIN
12.00 · 0.398
(1)
Therefore, the power efficiency of the switching power supply circuit has to be increased to meet the goal defined in [5].
Oscillator circuit
The time-domain waveform of the clock signal generated by the oscillator circuit using
the initial switching power supply circuit is shown in Fig. 4. The signal is recorded using
the 50-Ω channel oscilloscope connected by the coaxial cable to the edge-mount SMA
connector, while the output of LISN is terminated into 50 Ω. The peak-peak value of the
clock is approximately 2.5 Vpp and the clock frequency is 100 MHz.
4
(a)
(b)
Figure 2: PCB layout of the initial switching power supply circuit: (a) top view and
(b) mirrored bottom view.
5
(a)
(b)
Figure 3: (a) Measurement setup including used equipment and (b) connection of LISN
and load resistor to the power supply circuit.
Conducted emissions
Conducted emissions are measured at the input of the switching power supply circuit
using the provided LISN and the spectrum analyzer listed in Appendix, while the output
of the oscillator circuit is terminated into a 50-Ω impedance. The noise conducted to
the input of the initial switching power supply circuit is shown in Fig. 5. The conducted
noise is measured for three test cases:
ˆ circuit turned on (ON),
ˆ circuit turned off (OFF),
ˆ spectrum analyzer not connected to the setup (N.C.).
The peaks at 100 MHz, 200 MHz and 300 MHz in the conducted noise when the
circuit is powered on are caused by the harmonics of the 100-MHz clock signal generated
by the oscillator. The broadband noise of -60 dBm up to 150 MHz and -80 dBm from
150 MHz to 350 MHz can be attributed to the switching behaviour of the circuit and
parasitics of the components and PCB traces.
6
Oscillator output
Voltage, Vosc [V]
2.5
2
1.5
1
0.5
0
−0.5
0
5
10
15
20
25
30
Time, t [ns]
35
40
45
50
Figure 4: Initial power supply circuit: generated clock signal.
CE measured
Amplitude [dBm]
0
ON
OFF
N.C.
−20
−40
−60
−80
−100
0
50
100
150
200
250
Frequency, f [MHz]
300
350
Figure 5: Initial power supply circuit: conducted emissions.
The narrowband noise is present around 100 MHz even when the power supply circuit
is powered off, which means that the surrounding noise is coupled to the input power cord.
The noise measured when the spectrum analyzer is disconnected from LISN shows the
noise of the measurement instrument itself.
7
3
Power Efficiency Boost
The power efficiency of LM3151 synchronous buck controller IC against the load current is shown in Fig. 6. For the operating point of the power suply circuit used in this
project (VIN = 12 V, IL = 1 A) [5], the achievable power efficiency is approximately 89%.
In order to achieve power efficiency larger than 85% as defined in [5], the components that
cause a redundant power dissipation are removed from the circuit, but the functionality
of the switching power supply circuit is not disturbed.
Figure 6: LM3151 switcher controller: efficiency vs. load current [6].
Component selection and modifications
The modifications applied to the initial power supply circuit in order to increase its power
efficiency are marked in Fig. 7.
U1
VIN
VIN
D1
Cbyp
R1
VCC
D2
EN
SS
Cvcc Cen
HG
BST
QH
Cbst
L1
VOU T
SW
LM3151
LG
FB
GND
D3
+
QL
GND
DS
Co1
Co2
R2
+ R4
IN VCC
GND O
GND
X0
Figure 7: Modifications of the switching power supply circuit to increase power efficiency.
Removing the diodes
The two LEDs, D2 and D3 , that act as the input and output voltage indicators, dissipate
the power large enough to reduce the overall efficiency, especially the diode D3 that
is connected in parallel to the load. Therefore, both LEDs are removed from the PCB,
which has increased the power efficiency. The resistor R1 used to limit the current flowing
through D2 and resistor R2 placed in parallel to the load resistance are also removed from
the circuit.
8
The diode D1 is shorted out and removed since it has a forward voltage drop of 0.9 V
which causes a significant power dissipation.
Output inductor L1
In order to ensure the operation of the switching buck converter in the continuous
conduction mode (CCM), the inductance L1 should be larger than [7]:
L1,min =
VOU T · (1 − D)
,
2 · IL · fSW
(2)
where IL is the load current (1 A), D is the duty cycle and fSW is the switching frequency
(250 kHz). If the converter operates in CCM, than the duty cycle is defined as the ration
of the output and input voltage of the converter, which is D = 3.3/12 = 0.275 for the
converter used in this project. When the exact values are used in Eq. 2, the minimum
inductance is L1,min = 4.8 µH.
The existing power inductor L1 of 1.6 µH is replaced by the 10-µH IHLP-2020BZ
inductor from Vishay. Larger inductance leads to the smaller ripple of the current flowing
through the inductor [7], and the AC power inductor losses should also be decreased.
Furthermore, larger inductance leads to the lower cut-off frequency of the output low-pass
filter, and the high-frequency noise coupled from the circuit should also be reduced. The
selected inductor is packaged in a shielded case to minimize the noise coupling to other
parts of the circuit [8].
Low-side Schottky diode
The Schottky diode PMEG6030EP from NXP (DS in Fig. 7) with a forward voltage
drop lower than the internal body diode of the FET is placed across the low-side FET QL .
The Schottky diode has to have a reverse breakdown voltage larger than the maximum
input voltage (VIN = 12 V) and the forward current larger than the maximum output
current (IL,DC = 1 A).
Position of Cbyp
The 100-nF capacitor Cbyp , initially placed far away from the VIN pin of the buck
controller IC, is moved directly to the VIN pin to improve the operation of the buck
controller by decreasing the parasitic inductance of the PCB layout between the pin and
the capacitor.
Final calculation
The values of the input voltage, output voltage and input current measured after
all modifications are following: VIN = 12.00 V, VOU T = 3.29 V, IIN = 310 mA. The
resistance of the load resistor is 3.3 Ω and the power efficiency can be calculated as:
η=
VOU T 2 /RL
3.292 /3.3
=
= 0.882 (= 88.2%).
VIN · IIN
12.00 · 0.310
Therefore, the goal to achieve the power efficiency larger than 85% is achieved.
9
(3)
4
Reduction of Conducted EMI
The switching power converter used in this project is a typical non-isolated switching
DC-DC converter based on a controller IC, which uses only two lines to the input port.
Therefore, any current going in through one terminal of the input has to go out through
the other terminal, and the common mode noise conducted through the input power cord
should be theoretically zero [9].
The reduction of the noise conducted through the input power cord to the LISN is
based on filtering the differential-mode conducted EMI. The idea is to modify the existing
power supply circuit to minimize the propagation of the narrowband noise caused by the
clock oscillator and the broadband noise caused by the parasitics of the circuit.
The schematic of the switching power supply circuit after all modifications are applied
is shown in Fig. 8. The components that are added to the board in order to reduce the
conducted EMI are marked in red colour.
Component selection
Input capacitance network: Ci1 , Ci2 , Ci3 connected to the pin U1-VIN
The objective when selecting the input capacitors is to reduce the ripple voltage amplitude seen at the input of the switching power supply circuit. Large input ripple voltage
can cause large amounts of ripple current to flow in the bulk capacitors, causing excessive
power dissipation in the ESR parasitic [10]. The input capacitors should be chosen so
that their voltage rating is greater than the maximum input voltage, which is 12 V for
this project. The equation to calculate the input capacitance is shown in [6]:
Cin,min =
Io,max · D · (1 − D)
1 · 0.275 · (1 − 0.275)
=
= 1.33 µF.
fSW · ∆VIN,max
250 · 103 · 0.05 · 12
(4)
In Eq. 4, Io,max is the maximum load current (1 A) and ∆VIN,max is the maximum
allowable input ripple voltage (5% of VIN ) [6].
In this project, three parallel ceramic capacitors are placed at the input: Ci1 = 1 µF,
Ci2 = 47 µF and Ci3 = 47 µF. The capacitors are placed close to the high-side switch
QH to reduce the parasitic inductance of the input current loop formed by the FET
switches and the input decoupling capacitance network [11]. The capacitor Ci1 is placed
closest to QH because it is packed in a 0603 surface mount device (SMD) package size
and has the equivalent series resistance (ESR) lower than the other capacitors. The input
capacitance network has also a slight impact on the power efficiency of the circuit that is
calculated in the previous section.
Output capacitance network: Co1 , Co2
The minimum capacitance of the output capacitive network is defined in [6]:
Cout,min =
70
2
fSW · L
=
70
(250 · 103 )2 · 10−6
= 112 µF.
(5)
Typical hysteretic constant on-time converters require a certain amount of the ripple
output voltage that is fed back to the error comparator [6]. Therefore, no additional
capacitors are added in parallel to the existing 150-µF capacitors Co1 and Co2 to prevent
the further decrease of the ripple output voltage that is fed back to the buck controller.
10
Ci1 Ci2 Ci3
Cbyp
VIN
L2
CL1
C1
11
GND
L3
CL3
U1
HG Cbst
VIN
BST
VCC
SW
EN LM3151
LG
SS
GND FB
L4
CL4
CL2
Cvcc
Cen
QH
L1
VOU T
RS
QL
CS
Co1
L5
+
+
Co2
C2
C3
L6
DS
L7
C5
GND
R4
IN VCC
C4
GND O
RO
X0
Figure 8: Schematic of the final switching power supply circuit.
C6
Capacitors C1 , C2 , C3
The 22-µF capacitor C1 placed directly at the input of the board and the two capacitors, C2 = 100 µF and C3 = 22 µF, placed at the output of the board are used to
additionally smooth out the voltage perturbations at the input and load. The capacitors
C2 and C3 are placed at the point where the load connection wires are soldered to the
PCB, which is far away from the point where the output voltage is fed back to the buck
controller. Furthermore, C2 and C3 are packed in 1206 and 1210 SMD packages, and
their ESR is not too low to cause a faulty operation of the buck controller IC due to the
too low ripple voltage that is fed back to the controller IC.
Input low-pass filter: L3 , L4 and CL1 , CL2 , CL3 , CL4
The two-stage LC filter is added to the board, at the input of the circuit. The input
filter is designed based on the guidelines given in [12]. The broadband noise that has to
be filtered is in the frequency range from 10 MHz to 350 MHz, and the cut-off frequency
of the low-pass filter has to be lower than 10 MHz. Furthermore, if the self resonant
frequencies (SRFs) of the filter elements are too low, the low-pass filter can become a
high-pass filter and the high-frequency broadband noise would not be filtered. Therefore,
the components with SRF higher than 350 MHz are chosen.
Two shielded inductors, L3 = L4 = 1.5 µH, from Coilcraft, with SRF of 460 MHz are
used in the two-stage input filter. The capacitors CL1 and CL3 are 100-nF capacitors in
0603 SMD package that are used to reduce the total ESR of the capacitive part of the
filter. The 22-µF capacitors CL2 and CL4 are used to determine the capacitance of the
low-pass filter.
Ferrite beads L5 , L6 , L7
The three ferrite beads L5 , L6 , L7 are used to isolate the high-frequency oscillator
circuit from the rest of the circuit [3]. The BLM15HD182SN1D ferrite beads from Murata
with the frequency of the impedance peak higher than 500 MHz are chosen. The ferrite
beads are responsible for filtering the narrowband peaks of the measured conducted noise
due to the clock signal generated by the oscillator. The three ferrite beads are placed in
series to provide sufficient impedance at the frequencies of interest.
In this way, a power supply isolation is achieved to reduce the noise conducted from
the oscillator to the remainder of the circuitry through the power supply trace. Since the
power planes are isolated, the decoupling capacitors for the oscillator IC are necessary.
Decoupling capacitors C4 , C5 , C6
The capacitors C4 = 100 nF, C5 = 22 µF, C6 = 47 µF, are chosen to provide supply
for the oscillator circuit after it is isolated from the rest of the circuit using the ferrite
beads. The capacitors are placed close to the oscillator VDD and GND pins, while C4 is
in the smallest SMD package and it is placed closest to the oscillator IC.
RC snubber: RS and CS
The RC snubber circuit, RS = 5 Ω and CS = 1 nF, is used to reduce the high-frequency noise and it is designed using the guidelines from [13]. The impact of the RC
snubber on the switching voltage waveform is shown in Fig. 9. The ringing observed
12
before the snubber is added has the frequency of approximately 75 MHz, which is in the
frequency range of interest. The overshoot and oscillations are largely damped after the
RC snubber is added to the circuit.
The drawback of using the RC snubber is a power dissipation in the resistor RS which
reduces the overall power efficiency. However, the large part of that energy would be lost
through the oscillations if the RC snubber is not used, and no significant impact on the
power efficiency is observed after the snubber is added.
Voltage, VSW [V]
15
12
9
6
3
0
0
25
without snubber
with snubber
50
75
100
Time, t [ns]
Figure 9: Impact of the RC snubber on the switching node voltage waveform.
Resistor RO at the oscillator output
The damping resistor RO = 27 Ω is placed between the oscillator output and the SMA
connector to reduce the amplitude of the generated clock signal as well as the conducted
noise at the harmonics of the frequency of oscillations. This resistor helps to reduce
ringing and controls reflections of the generated clock signal [3]. The chosen value is low
enough to maintain the peak-peak value of the clock signal larger than 1.8 Vpp that is
defined in [5].
Zero-Ohm shorts
Several 0-Ω resistors are placed in the input power supply trace to short out the cut
in the PCB traces. These cuts are done to analyze the impact of other filtering elements
which did not show an improvement in the conducted noise measurements, but have
caused a power efficiency drop. Therefore, the filtering elements are removed, and trace
cuts are shorted by the 0-Ω “stitches”.
Ferrite bead L2
The BLM41PF800SN1L ferrite bead L2 from Murata is placed in the input power
trace to additionally reduce the noise conducted to the input power cord. The ferrite
bead L2 has a current rating large enough to withstand the input current.
13
Layout modifications
The layout of the switching power supply circuit is modified to minimize the propagation of the noise on the PCB. The modifications applied to the top and bottom layer are
marked in red color in Fig. 10. Two LEDs with corresponding current-limiting resistors
are removed from the board as well as the diode D1 at the input of the circuit as it was
described in previous section. The red rectangles shown in Fig. 10 mark the 0-Ω resistors
used to short the traces and planes.
High-frequency signal trace
The high-frequency clock signal is the most critical for the EMI of this power supply
circuit. The copper trace in the bottom layer that carries the high-frequency clock signal
generated by the oscillator is routed across the whole layer, which causes a coupling of
the high-frequency noise to other parts of the circuit. This high-frequency trace is cut to
keep the clock trace as short as possible and to minimize the high-frequency noise that is
coupled to the other parts of the circuit. The rest of the PCB trace is tied to the ground
plane using the 0-Ω resistors.
Ground plane slots
The copper slots in the top and bottom layer of the initial PCB design are shorted
by the 0-Ω resistors in order to avoid forcing the current to flow through a much larger
loop area and to cause an excessive PCB radiation that could couple to the input power
cord and cause excessive conducted noise. It is written in [3] that ground plane slots can
increase the PCB radiation in excess of 20 dB and it is recommended to avoid them to
minimize the EMI.
Return current path
The return current for high-frequency signals is confined to the area that has the
lowest impedance at the frequencies of interest [14]. Therefore, the path for the return
current in the bottom-layer ground plane is realized directly underneath the top layer
current-carrying traces in order to decrease the inductance, i. e. impedance of the return
current path.
The proper return current path in the bottom PCB layer is achieved using the closely
placed 0-Ω resistors directly underneath the current-carrying traces in the top PCB layer
that are marked by the large red rectangles in Fig. 10.
Bootstrap area
The large copper plane between the switching node of the converter and the bootstrap capacitor Cbst seen in Fig. 10(a) acts as a parasitic trace-ground capacitor for the
bootstrap circuit. The PCB trace is cut and 0-Ω resistor is placed in order to form the
lowest-inductance path for the bootstrap circuit. The copper plane is left floating since
it did not show any impact on both power efficiency and conducted emissions after it was
tied to the ground potential using the copper wires.
14
(a)
(b)
Figure 10: Modifications of the layout of the power supply circuit: (a) top view and (b)
mirrored bottom view.
15
Input switching loop area
The parasitic inductance of the current loop formed by the input decoupling network
and the FET switches is minimized by placing the 0-Ω resistor between the source node
of the low-side switch and the ground plane in the top PCB layer. In this way, the current
loop is formed through the top layer and not through the single through-hole via that
connects the top and the bottom PCB layers, which reduces the parasitic inductance, as
well as the corresponding radiated noise that can be coupled to the input power cord.
Besides the modifications that are shown in Fig. 10 and explained in this section,
some floating copper traces are tied to the ground plane using the 0-Ω resistors.
16
5
Final Results
The time-domain waveform of the clock signal generated by the oscillator circuit is
shown in Fig. 11. The peak-peak value of the clock signal is 1.83 V which meets the
goal defined in [5]. The comparison between the conducted emissions measured using the
initial and the final power supply circuit is shown in Fig. 12. The narrowband noise at the
frequencies of the harmonics of the clock signal is significantly reduced. The broadband
noise from 10 MHz to 350 MHz is also reduced after the applied modifications. The
measured noise from 90 MHz to 110 MHz can be attributed to the frequency modulated
(FM) radio broadcasting since the similar noise level is observed even if the switching
power supply circuit is powered off.
Oscillator output
Voltage, Vosc [V]
2
1.5
1
0.5
0
−0.5
0
2.5
5
7.5
10
12.5
Time, t [ns]
15
17.5
20
Figure 11: Output signal of the oscillator circuit.
CE measured
Amplitude [dBm]
0
initial
OFF
final
−20
−40
−60
−80
−100
0
50
100
150
200
250
Frequency, f [MHz]
300
350
Figure 12: Comparison of measured conducted emissions.
The comparison of the switching power supply circuit before and after all the modifications is shown in Table 2. The power efficiency and the peak-peak value of the generated
clock signal after all the modifications applied to the switching power supply circuit meet
17
Parameter
Power eff. [%]
Osc. output [Vpp]
NB noise sum [W]
BB noise sum [W]
Peak @100 MHz [dBm]
Peak @200 MHz [dBm]
Peak @300 MHz [dBm]
Initial
68.3
2.50
1.118 ·10−4
1.605 ·10−7
-13.7
-28.6
-30.5
Final
88.2
1.83
2.996 ·10−9
2.957 ·10−9
-63.7
-64.9
-68.3
Table 2: Final results: initial vs. final circuit (NB – narrowband, BB – broadband).
the goals defined in [5]. The peaks of the narrowband conducted noise measured at the
input power cord is reduced by 50 dB for 100 MHz and by almost 40 dB for 200-MHz
and 300-MHz harmonics of the clock signal. Both narrowband and broadband conducted
noise are significantly reduced after the applied modifications.
18
6
Conclusion
A step-down switching power supply circuit based on the LM3151 buck controller IC is
modified to achieve power efficiency larger than 85%, peak-peak value of the clock signal
larger than 1.8 Vpp and conducted emissions as low as possible.
The power efficiency is mainly increased by removing the components that cause an
excessive power dissipation and are not important for the functionality of the switching
power supply circuit. The final power efficiency is 88.2 % and the peak-peak value of the
clock signal is 1.83 Vpp, which meets the defined goals.
The components that are replaced and added to the board are chosen in a way to
minimize both broadband and narrowband conducted noise that is measured using the
existing LISN circuit. The PCB layout is modified in a way to minimize the propagation
of the noise on the PCB.
The peaks of the measured conducted noise at frequencies of the harmonics of the
generated clock signal are reduced by 50 dB for 100-MHz harmonic and by almost 40 dB
for higher harmonics. The broadband noise is lower than -80 dBm in the whole frequency
range of interest.
19
References
[1] A. I. Pressman, K. Billings, and T. Morey, Switching Power Supply Design, 3rd ed.
The McGraw-Hill Companies, USA, 2009.
[2] C. R. Paul, Introduction to Electromagnetic Compatibility, 2nd ed., ser. Wiley Series
in Microwave and Optical Engineering. Wiley-Interscience, 2006.
[3] H. Ott, Electromagnetic Compatibility Engineering, 1st ed.
Inc., Hoboken, New Jersey, 2009.
John Wiley & Sons,
[4] K. Kam, D. Pommerenke, F. Centola, C. W. Lam, and R. Steinfeld, “EMC Guideline for Synchronous Buck Converter Design,” in IEEE International Symposium on
Electromagnetic Compatibility, Aug 2009, pp. 47–52.
[5] D. Pommerenke, 2018 Student Hardware Design Competition – Rules, Missouri University of Science and Technology, Rolla, MO, USA, 2018.
[6] LM3151/LM3152/LM3153 SIMPLE SWITCHER CONTROLLER, High Input Voltage Synchronous Step-Down, Texas Instruments, Sept. 2011, datasheet.
[7] D. M. Robert W. Erickson, Fundamentals of Power Electronics, 2nd ed.
2001.
Springer,
[8] AN-2155 Layout Tips for EMI Reduction in DC / DC Converters, Texas Instruments, April 2013, Application Report.
[9] AN-2162 Simple Success With Conducted EMI From DC-DC Converters, Texas Instruments, April 2013, Application Report.
[10] J. Arrigo, Input and Output Capacitor Selection, Texas Instruments, Feb. 2006, Application Report.
[11] A. Bhargava, D. Pommerenke, K. W. Kam, F. Centola, and C. W. Lam, “DC-DC
Buck Converter EMI Reduction Using PCB Layout Modification,” IEEE Transactions on Electromagnetic Compatibility, vol. 53, no. 3, pp. 806–813, Aug 2011.
[12] A. Martin, AN-2162 Simple Success With Conducted EMI From DC-DC Converters,
Texas Instruments, April 2013, Application Report.
[13] Snubber Circuit for Buck Converter IC, ROHM Semiconductor, Oct. 2016, Application Note.
[14] C. R. Paul, Loop Inductance vs. Partial Inductance.
20
Wiley-IEEE Press, 2010.
7
Appendix
List of Measurement Equipment
Dual output DC power supply
6 1/2 digit multimeter
Mixed-signal oscilloscope
Current probe
Spectrum analyzer
Keysight E3646A
Keysight 34410A
Agilent MSO7034B
Agilent N2783B
R&S ESRP EMI Test Receiver
Bill of Materials
Initial components
Designator
U1
QH
QL
X0
Cbyp
Cen
Cvcc
Cbst
Co1 , Co2
Description
buck controller IC, LM3151
N-channel MOSFET, DMN6040
N-channel MOSFET, DMN6040
oscillator IC
SMD capacitor, 10 µF
SMD capacitor, 1 nF
SMD capacitor, 4.7 µF
SMD capacitor, 470 nF
SMD capacitor, 150 µF
Manufacturer
Texas Instruments
Diodes Inc.
Diodes Inc.
-/-/-/-/-/-/-
Added components
Designator
DS
L1
Ci1
Ci2 , Ci3 , C6
C1 , C3 , CL2 , CL4 , C5
C2
L3 , L4
CL1 , CL3 , C4
RS
CS
L2
L5 , L6 , L7
RO
Description
Schottky diode, 3 A, 530 mV
power inductor, 10 µH, 4 A
SMD capacitor, 1 µF, 0603, 50 V
SMD capacitor, 47 µF, 1210, 16 V
SMD capacitor, 22 µF, 1206, 16 V
SMD capacitor, 100 µF, 1210 6.3 V
SMD inductor, 1.5 µH, 2.6 A, 460 MHz
SMD capacitor, 100 nF, 0603, 50 V
SMD resistor, 4.99 Ω
SMD capacitor, 1 nF, 0603, 50 V
ferrite bead, 1 A
ferrite bead, 200 mA
SMD resistor, 27 Ω, 0805
21
Farnell order code
1829207
2125259
1845736
1735538
2494501
1650929
2287087
2332660
1752235
0722170
9526897
1515786
9332979