INS 2202 L
Digital Electronics Lab Manual
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Mark distribution:
Total marks: 60 (continuous evaluation ) + 40 (final exam).
Distribution of continuous evaluation marks:
Attendance - 10
Experiment completion on the same day - 10
Rough record and viva - 20
Fair record - 20 (fair record must be submitted on next day of each experiment, otherwise one mark will be
deducted for a delay of one day)
Note: All the students must do the experiments independently, not as a group. Due to the shortage of trainer
kits, each student can use the trainer kit once in every three days, if they want, on all other days the
experiments will be done using breadboards.
Ratheesh P.M.
Page 1 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 1: FAMILIARIZATION OF DIGITAL ICS & TRAINER KIT
AIM:
To familiarize with logic gate IC packages and to verify the truth tables of
those gates.
COMPONENTS AND EQUIPMENTS REQUIRED:
ICs 7400,7402,7404, 7408,7432,7486 and IC trainer kit.
THEORY:
LOGIC GATES:
In digital electronics a gate is a logic circuit with one output and one or
more inputs. Most logic gates are available as integrated circuits.
AND GATE:
The AND gate performs logical multiplication more commonly known as
AND operation. The AND gate output will be in high state only when all the inputs
are in high states.
C=A.B
7408 is a digital IC in the TTL family and contains four AND gates .For this
reason it is called quad two input AND gate. Every AND gate has two inputs in this
dual inline package(DIP).Pin 14 is the supply pin. For standard TTL device to work
properly, the supply voltage level must be between +4.75 and +5.25v.This is why
+5v is the normal supply voltage specified for all TTL devices. Pin 7 is the common
ground for the chip. The other pins are inputs and outputs.
OR GATE:
It performs logical addition. Its output will become high if any of the input is
in logic high.7432 is a quad two input OR gate.
C = A+B
NOT GATE:
It performs a basic logic functions called inversion or complementation .The
Ratheesh P.M.
Page 2 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
purpose of the inverter is to change one logic level to opposite level.IC 7404 is a hex
inverter.
B=A
NAND GATE:
A NOT gate following an AND gate is called NAND gate or NOT-AND
gate. Its outputs will be low when all the inputs are in high state.7400 IC is a quad
two input NAND gate.
C = (A.B)
NOR GATE:
A NOT gate followed by an OR gate is called NOT-OR gate or NOR gate.
Its output will be in low state if any of its input is high state.IC 7402 is a quad two
input NOR gate.
C = (A+B)
XOR GATE:
Its output will be high if one input is high state.IC 7486 is a quad two input XOR
gate.
C = A B+A B
PROCEDURE:
1.Test all the components and IC packages using a digital IC tester. Also assure
whether all the connecting wires are in good condition by testing for the continuity
using a multimeter or a trainer kit. Continuity of wires can be tested using a trainer
kit by shorting a 5v supply in the trainer to an LED of the panel. If wires are good
LED will glow.
2. Verify the dual in line package(DIP) pin out of the IC before feeding the inputs.
3. Set up the circuit and observe the output.
Ratheesh P.M.
Page 3 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
SYMBOLS AND TRUTH TABLES
1. AND GATE:SYMBOL FOR AND GATE
A
C
B
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
2. OR GATE:SYMBOL FOR OR GATE
A
C
B
TRUTH TABLE:
A
0
0
1
1
Ratheesh P.M.
B
0
1
0
1
C
0
1
1
1
Page 4 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
3. NOT GATE:SYMBOL FOR NOT GATE
A
C
TRUTH TABLE:
A
0
1
C
1
0
4. NAND GATE:SYMBOL FOR NAND GATE
A
C
B
TRUTH TABLE:
A
0
0
1
1
Ratheesh P.M.
B
0
1
0
1
C
1
1
1
0
Page 5 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
5. NOR GATE:SYMBOL FOR NOR GATE
A
C
B
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
C
1
0
0
0
6. XOR GATE:SYMBOL FOR XOR GATE
A
)
B
C
TRUTH TABLE:
A
0
0
1
1
Ratheesh P.M.
B
0
1
0
1
C
0
1
1
0
Page 6 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
7.XNOR GATE:SYMBOL FOR XNOR GATE
A
)
B
C
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
C
1
0
0
1
RESULT:
Familiarized with logic gate IC packages and to verify the truth tables of
those gates
Ratheesh P.M.
Page 7 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 2: REALIZATION OF BASIC GATES USING UNIVERSAL GATES
AIM:
To realize logic gates using universal gates.
COMPONENTS AND EQUIPMENT REQUIRED:
ICs 7400, 7402, and trainer kit.
THEORY:
NAND or NOR gates are known as universal gates. Because only basic logic gates can
be realized using either NAND or NOR gate.
USING NAND GATES:
NOT gate:
By connecting NAND gate we can realize the function of NOT gate. The output is
the compliment of input.
OR gate:
An OR gate can be realized by connecting 3 NAND gate. The output of two NOT gate
using NAND gate is inverted by a NAND gate to get an OR gate.
AND gate:
NAND gate is an AND gate followed by an inverter. In this output of NAND gate is
inverted by using a NAND gate inverter to get an AND gate.
NOR and EXOR gate:
By connecting four NAND gates, we obtain NOR or EXOR gates.
USING NOR GATES:
NOT gate:
By connecting NOR gate we can realize the function of an inverter. The output is the
complement of an input given to it.
Ratheesh P.M.
Page 8 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
OR gate:
NOR gate is an OR gate followed by an inverter, the output of the NOR gate is
inverted by using a NOR gate inverted to get an OR gate.
AND gate:
An AND gate function can be realized by connecting 3 NOR gates. In the output of
NOT gate using NOR gate is inverted by using an OR gate to get an AND gate.
NAND and EXOR gate:
By connecting a NOR gate together we can get NAND gate and 5 NOR gate EXOR gate
PROCEDURE:
1) Verify the components and wires whether they are in good condition.
2) Connection are made as per the fig. and observe the output corresponding to the input
combination and enter it in to the truth table
Ratheesh P.M.
Page 9 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
AND USING NAND:
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
OR USING NAND:
TRUTH TABLE:
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1
NOR USING NAND:
Ratheesh P.M.
Page 10 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
A
Y
1
0
0
1
Y
1
0
0
0
EXOR USING NAND:
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
NOT USING NAND:
TRUTH TABLE:
Ratheesh P.M.
Page 11 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
AND USING NOR GATE:
TRUTH TABLE:
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
OR USING NOR GATE:
TRUTH TABLE:
NAND USING NOR GATE:
Ratheesh P.M.
Page 12 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
TRUTH TABLE:
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
NOT USING NOR GATE:
TRUTH TABLE:
A
0
1
Y
1
0
RESULT:
Realized logic gates using universal gates.
Ratheesh P.M.
Page 13 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 3: HALF AND FULL ADDERS & SUBTRACTORS
AIM:
1. To design and set up a half adder using
a) EXOR gates and NAND gates
b) NAND gates only.
2. To design and set up a full adder using
a) EXOR gates and NAND gates
b) NAND gates only.
3. To design and setup a half subtractor using NAND gates only.
4. To design and setup a full subtractor using NAND gates only.
COMPONENTS AND EQUIPMENT REQUIRED:
ICs 7400, 7486, 7408 and IC trainer kit.
THEORY:
ADDER:
The simplest binary adder is called half adder. Half adder has two input bits and two
output bits. One output bit is sum and other bit is carry. They are represented by s and c
respectively in logic symbol. A half adder has no provision to add a carry from the lower order
bits when binary numbers are added. When two input bits and carry are to be added, the number
input bit become three and input combination increases to eight. For this a full adder is used like
half adder, it also has a sum bit and carry bit. The new carry generated is represented by Cin and
carry generated from the previous addition is represented by Cn-1.
SUBTRACTOR:
The simplest subtractor is half subtractor. These have two inputs bit and two output bit.
One bit is difference and other is borrow, represented by s and c. full subtractor can subtract three
bits, where third bit is borrow ones from the previous state and is represented as Cn-1.A half sub
tractor is an arithmetic circuit than subtract one bit from other. It used to subtract the LSB of the
subtracted from the LSB of the minor end.
When one binary number is subtracted from the other the half subtractor can be used
only for LSB subtraction. If there is a borrow during subtraction of 1st bit affect the subtraction in
the next higher column. The subtracted bit is subtracted from the minor end.
Ratheesh P.M.
Page 14 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
PROCEDURE:
1. Verify whether all the components and wires are in good condition.
2. Set up the half adder circuit and feed the input bit combinations.
3. Observe the output corresponding to input combinations and enter it in the truth table.
4. Repeat the above steps for a full adder circuit, half subtractor and full subtractor circuits.
Ratheesh P.M.
Page 15 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
HALF ADDER:
A
SUM
B
CARRY
HALF ADDER
TRUTH TABLE:
A
B
SUM
CARRY
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
1
A
B
0
0
1
1
0
0
0
1
C=AB
A
B
0
0
1
1
0
1
1
0
S=A
Ratheesh P.M.
Page 16 of 83
B
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
REALIZATION OF HALF ADDER:
HALF ADDER USING NAND GATE:
HALF ADDER USING NAND GATE:
FULL ADDER:
A
B
SUM
FULL ADDER
CARRY
C
Ratheesh P.M.
Page 17 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
REALISATION OF FULL ADDER:
SUM
CARRY
Ratheesh P.M.
Page 18 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
HALF SUTRACTOR:
Ratheesh P.M.
Page 19 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
REALISATION OF HALF SUBTRACTOR:
FULL SUBTRACTOR:
TRUTH TABLE:
Ratheesh P.M.
Page 20 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
REALISATION OF FULL SUBTRACTOR:
FULL SUBTRACTOR USING NAND GATE:
RESULT:
Designed and set up half adder, full adder, half subtractor and full subtractor circuits.
Ratheesh P.M.
Page 21 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 4:CODE CONVERTERS
AIM:
To design and set up the following circuit.
1)
A 4 bit binary to gray code converter.
2)
A 4 bit gray to binary code converter.
COMPONENTS AND EQUIPMENTS REQUIRED:
ICs 7486, 7408, and IC trainer kit.
THEORY:
To convert a binary number to corresponding gray code, the following rules are
applied.
1)
The MSB in the gray code is the same as the corresponding digit in the binary number.
2)
Going from left to right, add each adjacent pair of binary digit to get the next gray code
digit. Disregard carriers.
As the first step to design a binary to gray code converter, set up a truth table with binary
numbers B3,B2,B1,B0 and corresponding gray code numbers G3,G2,G1,G0. Set up a circuit
realizing the simplified logic expression obtained using k maps.
To convert gray code to binary, the following rules are applied.
1) The most significant digit in the binary number is same as the corresponding digit in the gray
code.
2) Add each binary digit generated to the gray code digit in the next adjacent position. Disregard
carries.
To design gray to binary code converter, set up the truth table and get simplified
expression using k maps for each binary bit as a function of gray code bits. Each gray code
number differs from the preceding number by a single bit.
PROCEDURE
1)Test all the components and ic packages using multimeters and digital ic tester.
2)Verify the truth tables of the circuit by feeding the input bit combinations
Ratheesh P.M.
Page 22 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
BLOCK DIAGRAM :( binary to gray code conversion)
Binary to gray code converter
Binary
Gray code output
Input
TRUTH TABLE:
BINARY
B3 B2 B1
1
1
Ratheesh P.M.
GRAY
BO G3 G2 G1 G0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
1
0
1
1
1
Page 23 of 83
0
0
0
0
1
0
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
REALISATION USING K-MAPS:
B 1B0
B 3B2
00
01
11
10
00
0
0
1
1
01
0
0
1
1
11
0
0
1
1
10
0
0
1
1
G3=B3
B 3B 2
B 1B 0
00
01
11
10
00
0
1
0
1
01
0
1
0
1
11
0
1
0
1
10
0
1
0
1
G2=B3⨁B2
B 3B 2
B 1B 0
00
01
11
10
00
0
1
1
0
01
0
1
1
0
11
1
0
0
1
10
1
0
0
1
G1=B1⨁B2
Ratheesh P.M.
Page 24 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
B 3B 2
B 1B 0
00
01
11
10
00
0
0
0
0
01
1
1
1
1
11
0
0
0
0
10
1
1
1
1
G0=B0⨁B1
CIRCUIT DIAGRAM:
Ratheesh P.M.
Page 25 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
TRUTH TABLE:
GRAY
BINARY
G3 G2 G1 G0 B3 B2 B1 B0
Ratheesh P.M.
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
1
0
1
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
0
1
0
Page 26 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Ratheesh P.M.
Digital Electronics Lab Manual
Page 27 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
CIRCUIT DIAGRAM:
RESULT:
Designed and set up a 4 bit binary to gray and a 4 bit gray to binary code converter
Ratheesh P.M.
Page 28 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 5: 4-BIT ADDER – SUBTRACTOR IC & BCD ADDER CIRCUITS
AIM:
To design and set up the following arithmetic circuits using 4 bit binary adder IC 7483.
1.4- bit binary adder.
2. 8 -bit binary adder.
3. 4- bit add/ subtract circuit.
4. single digit BCD adder.
COMPONENTS AND EQUIPMENT REQUIRED:
IC’S 7400,7483,7486, and IC trainer kit.
THEORY:
The 7483 IC is a TTL IC with 4 full adders in it. This means that it can add nibbles. To add
bytes, we need to use two 7483 ICs.
4- BIT BINARY ADDER:
A and B are input and Cout and S are output. CARRY IN pin is grounded. This circuit
is also called a nibble adder.
8 -BIT BINARY ADDER:
The easy part is adding the two 8 bit binary numbers by using the carry out of one and
carry in of the other. We input the 8 bit numbers with 8 switches(representing high or low) per
number to represent each bit.
4 BIT ADDER/ SUBTRACTOR CIRCUIT:
For the 4-bit binary numbers A = A4A3A2A1 and D=D4D3D2D1, assume that they are in
the 2's complement representation. This design implements addition A + D when the control
signal sub inputs 0. This design implements subtraction A - D when the control signal sub inputs
1. The 4-bit vector S = S4S3S2S1 will hold the results. EXOR gates function as controlled
inverters. When SUB=1,D4D3D2D1 I’s complemented. Now A4A3A2A1, complemented version of
D4D3D2D1, and 1 at Cin pin are added together. Cout is ignored.
Ratheesh P.M.
Page 29 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
SINGLE DIGIT BCD ADDER:
In the BCD addition, if sum exceeds 9(1001), 6(0110) must be added to the result to convert
it in to BCD number. For this purpose two 7483 IC s are required. One for binary addition and
other for addition of 6. A combinational circuit is set up so that its output Cout makes A 3A2A1A0
=0110 when S3S2S1S0 greater than 1001 or Cin=1.
PROCEDURE:
1. Test all components and IC packages using millimeters and digital IC testers.
2.set up a nibble adder and try a few nibbles addition.
3.set up byte adder and verify its working.
4. Set add/sub tractor circuit. Make SUB=0 and verify whether it works as a nibble adder.
5. To function as sub tractor, make SUB=1, A3A2A1A0=1010 and B3B2B1B0= 1001 then verify
S3S2S1S0=0001.
6. Keeping SUB=1 reverse the values of nibbles and verify the output =1111=2’s complement of
0001
7. Set up BCD adder and verify the result.
Ratheesh P.M.
Page 30 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
Ratheesh P.M.
Page 31 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
4 BIT ADDER/SUBTRACTOR:
Ratheesh P.M.
Page 32 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
C=S2S3+S1S3
SINGLE DIGIT BCD ADDER
RESULT:
Designed and set up a 4- bit binary adder, 8 -bit binary adder, 4- bit add/ subtract , single
digit BCD adder circuits using IC 7483.
Ratheesh P.M.
Page 33 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 6: MULTIPLEXERS, DEMULTIPLEXERS, DECODERS
USING LOGIC GATES.
AIM:
1) To study a 4:1 multiplexer using logic gates.
2) To study a 1:4 Demultiplexer using logic gates.
COMPONENTS AND EQUIPMENTS:
ICs 7411, 7432, 7404, 7400, IC trainer kit.
THEORY:
MULTIPLEXER:
MUX is a combinational circuit which selects one of the inputs and route it to the output. A MUX
has data input lines, data select lines, and output.
The logic symbol of a 4 line to 1 line MUX is shown in fig. according to 2 bit
binary code on the data select input, corresponding data input line will be selected and routed to
the output. For example if S1SO is 00, D0 will be selected and so on. From the truth table, It can
be seen that output.
Y=D0S1 S0+D1S0S1+D2S0S1+D3S0S1
This Boolean expression can be realized using gates
DEMULTIPLEXERS:
It does the reverse operation of multiplexer. The data on a line is directed to anyone of the
output line according to the binary code on data select lines. The logic symbol of a 1:4 DEMUX
is shown in fig. When the input on data select inputs S1 S0 is 00 logic state on the data line will
be available on D0 output. Input on data select inputs is 01; logic state on the data line will be
available on D1 output and so on.
PROCEDURE :
1) Test all IC’s and set up the circuit. Give a 4 bit binary combination at D0 through D3.
2) Feed all four combinations at S1 S0 one by one.
3) Observe corresponding output and verify it functions as MUX.
.
Ratheesh P.M.
Page 34 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
TRUTH TABLE:
S1
0
0
1
1
S0
0
1
0
1
Y
C0
C1
C2
C3
CIRCUIT DIAGRAM
Ratheesh P.M.
Page 35 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DEMUX:
S0
D0
S1
D1
DEMUX
D
D2
D3
TRUTH TABLE:
S1
0
0
1
1
S0
0
1
0
1
D0
D
0
0
0
D1
0
D
0
0
D2
0
0
D
0
D3
0
0
0
D
CIRCUIT DIAGRAM:
RESULT:
Studied a 4:1 multiplexer and 1:4 demultiplexer using logic gates
Ratheesh P.M.
Page 36 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 7:COMBINATIONAL LOGIC DESIGN USING DECODERS & MUX
AIM:
a)To familiarize 74151,74154 & 74150 IC’s
b) Combinational logic design using MUX IC 74151 and DEMUX IC 74154.
COMPONENTS AND EQUIPMENTS REQUIRED:
IC’s 74151, 74154, 7430(5 input NAND gate), and IC trainer kit (7430, 4710, 7400,
7432).
THEORY:
Multiplexer can be used to realize logic circuit. A multiplexer with number of selected lines
can be used to realize ‘n’ variable Boolean expression with additional logic gates or circuits with
n+1 variable Boolean expression can be realized with the same multiplexer.
An 8:1 multiplexer can be used to implement a 3 variable logic function and a 16 line to 1 line
MUX used to implement a 4 variable Boolean expression without additional logic gates. Suppose
the Boolean expression to be implemented is
F(A,B,C)=A B C+ A B C +A B C
The minterms in this expression correspond to 000,010,and 111.this expression can be
implemented using 74151by applying logic inputs to D0 D2 and D7 and logic 0 to other inputs.
Decoder can be used to realize logic circuits. a decoder is nothing but a DEMUX with
data input grounded. The 1:16 DEMUX ic 74154 can be used as a decoder also. It functions as a
4 to 16 decoder when its data input and strobe input are grounded. Since data input is grounded,
output is at active low. For example, if select input word ABCD is 1010, Y10 will be at logic 0
state and all other output will be at logic high state. Suppose Boolean expression to be
implemented using the decoder is
F(A,B,C,D)=A B C D + A B C D + A B C D +A B C D +A B C D
It means that minterms are corresponding to the numbers 2, 4, 7, 8, and 12.if the binary
numbers corresponding to these numbers are applied at the selected inputs, corresponding data
output will be zero. The output Y2 Y4 Y7 Y8 and Y12 must be inverted and OR to obtain F
Ratheesh P.M.
Page 37 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
according to de- Morgan’s theorem. NOT followed by OR is equivalent to NAND.
REALIZATION OF BOOLEAN EXPRESSION USING MULTIPLEXERS:
Function to be implemented by MUX is
F(A,B,C)=A B C+ A B C +A B C
I.e., F(A,B,C)=€ (0,2,7)Therefore input D0, D2, D7 should be connected to logic 1 and remaining
data input should be connected to logic 0.
IMPLEMENTATION OF BOOLEAN EXPRESSION USING A DECODER:
The function that to be implemented using a mux is
F(A,B,C,D)=A B C D + A B C D + A B C D +A B C D +A B C D
Decoder ic 74154 is used to realize the given function
F(A,B,C,D)=€ (2,4,7,8,12)the output of 74154 are active low, when active low
input are feed to a NAND gate input. It is equivalent to OR operator.
PROCEDURE:
1) Test all IC and wires before doing the experiment
2)Set up the circuit as shown in fig. And verify truth table
Ratheesh P.M.
Page 38 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
1)F(A,B,C)=A B C+ A B C +A B C
Ratheesh P.M.
Page 39 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
2)F(A,B,C,D)=A B C D+ A B C D+ A B C D+ A B C D +A B C D
RESULT:
Familiarized with 74151& 74154IC’s and designed Combinational logic design using
MUX IC 74151 and DEMUX IC 74154.
Ratheesh P.M.
Page 40 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 8: FLIP FLOPS USING GATES
AIM:
To design and set up the following flip flops
1: SR flip flop
2: JK flip flop
3: MSJK flip flop
4: D flip flop
5: T flip flop
COMPONENTS & EQUIPMENTS REQUIRED:
IC’s 7400,7410,7473,7474,7476, and trainer kit
THEORY:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to
store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change
state by signals applied to one or more control inputs and will have one or two outputs. It is the
basic storage element in sequential logic. Flip-flops and latches are a fundamental building block
of digital electronics systems used in computers, communications, and many other types of
systems.
Flip-flops and latches are used as data storage elements. Such data storage can be used for
storage of state, and such a circuit is described as logic IC. Flip-flops can be either simple
(transparent or opaque) or clocked (synchronous or edge-triggered); the simple ones are
commonly called latches. The word latch is mainly used for storage elements, while clocked
devices are described as flip-flops. A latch is level-sensitive, whereas a flip-flop is edge-sensitive.
TYPES OF FLOP FLOPS:
SR FLIP FLOP:
The SR flip-flop, also known as a SR Latch, This simple flip-flop is basically a one-bit memory
bistable device that has two inputs, one which will "SET" the device (meaning the output = "1"),
and is labeled S and another which will "RESET" the device (meaning the output = "0"), labeled
Ratheesh P.M.
Page 41 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
R. Then the SR description stands for "Set-Reset". The reset input resets the flip-flop back to its
original state with an output Q that will be either at a logic level "1" or logic "0" depending upon
this set/reset condition
JK FLIP FLOP:
The J-K flip flop is the most versatile of the basic flip flops. It has two inputs, traditionally
labeled J and K.If J and K are different then the output Q takes the value o J at the next cock
edge. If both J and K are both low then no change occurs. If J and K are both high at the clock
edge then the output will toggle from one state to the other. The JK flip-flop is an SRFF with
some additional SR NAND flip-flop suffers from two basic problems: number one, the S = 0 and
R = 0 condition or S = R = 0 must always be avoided, and number two, if S or R change state
while the enable input is high the correct latching action may not occur. Then to overcome these
two fundamental design problems with the SR flip-flop, the JK flip-Flop was developed gating
logic on the inputs which serve to overcome the SR=11 prohibited state in the SRFF.
Ratheesh P.M.
Page 42 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
MSJK:
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from
timing problems called "race" if the output Q changes state before the timing pulse of the clock
input has time to go "OFF". To avoid this the timing pulse period ( T ) must be kept as short as
possible (high frequency). As this is sometimes not possible with modern TTL IC's the much
improved Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the "Master" circuit, which
triggers on the leading edge of the clock pulse while the other acts as the "Slave" circuit, which
triggers on the falling edge of the clock pulse. This results in the two sections, the master section
and the slave section being enabled during opposite half-cycles of the clock signal.
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a
series configuration with the slave having an inverted clock pulse. The outputs from Q and Q
from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the
"Master" flip-flop being connected to the two inputs of the "Slave" flip-flop. This feedback
configuration from the slave's output to the master's input gives the characteristic toggle of the JK
flip-flop as shown below.
The input signals J and K are connected to the gated "master" SR flip-flop which "locks"
the input condition while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of
the "slave" flip-flop is the inverse (complement) of the "master" clock input, the "slave" SR flip-
Ratheesh P.M.
Page 43 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
flop does not toggle. The outputs from the "master" flip-flop are only "seen" by the gated "slave"
flip-flop when the clock input goes "LOW" to logic level "0".
When the clock is "LOW", the outputs from the "master" flip-flop are latched and any
additional changes to its inputs are ignored. The gated "slave" flip-flop now responds to the state
of its inputs passed over by the "master" section. Then on the "Low-to-High" transition of the
clock pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave"
flip-flop and on the "High-to-Low" transition the same inputs are reflected on the output of the
"slave" making this type of flip-flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data
to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flipflop is a "Synchronous" device as it only passes data with the timing of the clock signal. Timing
diagram is shown below.
Ratheesh P.M.
Page 44 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
D FLIP FLOP:
The D-flip-flop has only a single data input.
T FLIP FLOP:
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected
together and thus are also called a single input J-K flip flop. When clock pulse is given to the flip
flop, the output begins to toggle. Here also the restriction on the pulse width can be eliminated
with a master-slave or edge-triggered construction.
The T or "toggle" flip-flop changes its output on each clock edge, giving an output which is half
the frequency of the signal to the T input. Take a look at the circuit and truth table below.
PROCEDURE:
1: Test all components and IC package using multimeters and digital ic tester
2: Set up FF using gates and verify their truth table.
Ratheesh P.M.
Page 45 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
SR FLIP FLOP:
TRUTH TABLE:
INPUT
OUTPUT
S
R
Qn+1
0
0
Qn
0
1
0
1
0
1
1
1
X
JK FLIP FLOP:
TRUTH TABLE:
INPUT
OUTPUT
J
K
Qn+1
0
0
Qn
0
1
0
1
0
1
1
1
Qn
Ratheesh P.M.
Page 46 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
MASTER SLAVE JK FLIP FLOP:
D FLIP FLOP:
TRUTH TABLE:
Ratheesh P.M.
Page 47 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
T FLIP FLOP:
TRUTH TABLE:
INPUT
T
0
1
OUTPUT
Qn+1
Qn
Qn
RESULT:
Designed and set up SR flip flop,JK flip flop,MSJK flip flop,D flip flop and T flip
flop using logic gates
Ratheesh P.M.
Page 48 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 9: ASYNCHRONOUS COUNTERS
AIM:
To design and set up the following asynchronous counter and study their working.
1. 4 bit binary up counter
2. 4 bit binary down counter
3. Decade counter
4. 3 bit up/down counter using mode control
COMPONENTS AND EQUIPMENTS REQUIRED:
IC’s 7476, 7400 and trainer kit.
THEORY:
A counter is a circuit that produce a set of unique output combination in relation to the
number of applied input pulses. The number of unique outputs of a counter is known as its
modulus or mod number. In the asynchronous counters, the flip flops are not given the clock
simultaneously. Therefore the propagation delay increases with the number of flip flops used.
Four JK flip-flops must be used in toggle mode to count 16 states.
4- BIT BINARY UP COUNTER:
In the circuit set up all flip flops are clocked by the Q output of the preceding flip flops
holding their JK inputs at logic 1.7476 is a dual JK Master Slave flip flop with preset and clear. A
ripple counter comprising of N flip flops can be used to count up to 2 N pulses. A circuit with 4
flip flops gives a maximum count of 24= 16.The counter gives a natural binary count from 0 to 15
and resets to initial condition on 16th input pulse. Since the J and K inputs of the flip flops are
connected to logic 1, they act as a toggle flip flop. Flip flop output toggles at the negative
transition of the clock input. With the application of the first clock pulse Q 0 change from 0 to
1.Q1, Q2, Q3 remains unaffected. With the second clock pulse, Q0 becomes 0 and
Q1
becomes
1.At the arrival of fifteenth clock pulse all the Q outputs will become 1.At the 16th clock pulse all
Q outputs get resets and the cycle repeats. When the counting up progresses at Q outputs counting
down happens at Q̃ outputs.
4- BIT BINARY UP COUNTER:
In this circuit the succeeding flip flop [s are clocked by the Q̃ ou tputs of preceding flip
flops. The outputs are taken from Q outputs .Initially all Q outputs are set. At the arrival of 16 th
clock pulse all Q outputs become resets and cycle continues.
Ratheesh P.M.
Page 49 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DECADE COUNTER:
The circuit of the decade up counter is similar to 4 bit ripple up counter but with the aid
of logic circuit the count is limited to 0 to 9. As soon as the count reaches 10D ie,1010, the
NAND gates clear the FF and the counting restarts from zero.
3- BIT UP/DOWN COUNTER:
Bidirectional counters, also known as UP/DOWN counters, are capable of counting in
either direction through any given count sequence and they can be reversed at any point within
their count sequence by using an additional control input.
3-bit Up/Down synchronous counter using JK flip-flops configured to operate as toggle or
T-type flip-flops giving a maximum count of zero (000) to seven (111) and back to zero again.
Then the 3-Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse
sequence (7,6,5,4,3,2,1,0).
PROCEDURE:
1)Test all components and IC package using multimeters and digital ic tester
2)Set up the circuit for 4-bit up counter. Connect all the preset pins to high.
3)Tie up clear pins and connect to logic low input, so that all the flip flops are cleared. Then
connect all the clear pins to high.
4)Apply clock pulses and counter starts counting.
5)Set up circuits for down counter, and decade counter and repeat the above steps.
6)Set up 3-bit up/down counter and observe the up counting when mode control is 1 and down
counting when mode control is 0
Ratheesh P.M.
Page 50 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
4-bit binary up counter:
COUNTING SEQUENCE
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ratheesh P.M.
Q3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Q2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Q1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Page 51 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
4bit binary down counter
COUNTING SEQUENCE
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ratheesh P.M.
Q3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Q2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Q1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Q0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Page 52 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DECADE COUNTER:
COUNTING SEQUENCE
CLK
0
1
2
3
4
5
6
7
8
9
10
Ratheesh P.M.
Q3
0
0
0
0
0
0
0
0
1
1
0
Q2
0
0
0
0
1
1
1
1
0
0
0
Q1
0
0
1
1
0
0
1
1
0
1
0
Q0
0
1
0
1
0
1
0
1
0
1
0
Page 53 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
3-BIT UP/DOWN COUNTER:
MODE
0
0
0
0
0
0
0
0
MODE
1
1
1
1
1
1
1
1
Q2
0
0
0
0
1
1
1
1
Q2
1
1
1
1
0
0
0
0
Q1
0
0
1
1
0
0
1
1
Q1
1
1
0
0
1
1
0
0
Q0
0
1
0
1
0
1
0
1
Q0
1
0
1
0
1
0
1
RESULT:
Designed and set up 4 bit binary up counter, 4 bit binary down counter, Decade counter, 3
bit up/down counter using mode control circuits.
Ratheesh P.M.
Page 54 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 10:SYNCHRONOUS COUNTERS
AIM:
To design and set up the following circuit using JK flip flop
1. 4 bit up counter
2. 4 bit down counter
COMPONENTS & EQUIPMENTS REQUIRED:
ICS 7476,7473,7408,7406,7432 and trainer kit
THEORY:
A synchronous binary counter counts from 0 to 2N-1, where N is the number of bits/flipflops in the counter. In synchronous counter all the flip flop works in synchronous with input
clock pulse .To implement a synchronous counter, we need a flip-flop for every bit(Each flip-flop
is used to represent one bit) and an AND gate for every bit except the first and the last bit. The
diagram below shows the implementation of a 4-bit synchronous up-counter. From the diagram
we can see that the third flip-flop gets its J-K input from the output of a 2-input AND gate and the
fourth flip-flop gets its input from another 2-input AND gate. the output from each flip-flop is
only used as an input to AND gate. The implementation of a synchronous binary down counter is
exactly the same as that of a synchronous binary up counter except that the inverted output from
each flip-flop is used. It counts from 1111 to 0000.
PROCEDURE:
1. Find the number of flip-flops using the relation N = log2 m, m is the modulus of the
counter and N is the number of flip flops
2. Write down the count sequence (flip flop outputs)in a tabular form. Determine the flip
flop inputs which must be the present state for the desired next state using excitation
table of flip flop.
3. Prepare the Karnaugh map for each flip-flop minterms of flip-flop output as the input
variables and obtain the minimized expression
4. Set up the circuits using flip flops and other gates
Ratheesh P.M.
Page 55 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
DESIGN OF 4-BIT UP COUNTER:
Ratheesh P.M.
Page 56 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN OF INPUT VARIABLES USING KARNAUGH MAP:
J0=K0=1
K MAP OF J1
Q 1Q0
Q 3Q2
00
01
11
10
00
0
0
0
0
01
1
1
1
1
11
X
X
X
X
10
X
X
X
X
J1 =Q0
K MAP OF J2
Q 1Q0
Q 3Q2
00
01
11
10
00
0
X
X
0
01
0
X
X
0
11
1
X
X
1
10
0
X
X
0
J2=Q1Q0
K MAP OF J3
Q 1Q0
Q 3Q2
00
01
11
10
00
0
0
X
X
01
0
0
X
X
11
1
1
X
X
10
0
0
X
X
J3=Q2Q1Q0
Ratheesh P.M.
Page 57 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
K MAP OF K1
Q 1Q0
Q 3Q2
00
01
11
10
00
X
X
X
X
01
X
X
X
X
11
1
1
1
1
10
0
0
0
0
K1=Q0
K MAP OF K2
Q 1Q0
Q 3Q2
00
01
11
10
00
X
X
X
X
01
X
X
X
X
11
1
1
1
1
10
0
0
0
0
K2= Q1Q0
K MAP OF K3
Q 1Q0
Q 3Q2
00
01
11
10
00
X
X
X
X
01
X
X
X
X
11
1
1
1
1
10
0
0
0
0
K3= Q2Q1Q0
Ratheesh P.M.
Page 58 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
CIRCUIT DIAGRAM:
DESIGN OF 4-BIT DOWN COUNTER:
Ratheesh P.M.
Page 59 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN OF INPUT VARIABLES USING KARNAUGH MAP:
K MAP OF J1
Q 1Q0
Q 3Q2
00
01
11
10
00
1
1
1
1
01
0
0
0
0
11
X
X
X
X
10
X
X
X
X
J1 =Q0
K MAP OF J2
Q 1Q0
Q 3Q2
00
01
11
10
00
1
X
X
1
01
0
X
X
0
11
0
X
X
0
10
0
X
X
0
J2=Q1 Q0
KMAP OF J3
Q 1Q0
Q 3Q2
00
01
11
10
00
1
0
X
X
01
0
0
X
X
11
0
0
X
X
10
0
0
X
X
J3=Q2 Q1 Q0
Ratheesh P.M.
Page 60 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
K MAP OF K1
Q 1Q0
Q 3Q2
00
01
11
10
00
X
X
X
X
01
X
X
X
X
11
0
0
0
0
10
1
1
1
1
K1=Q0
K MAP OF K2
Q 1Q0
Q 3Q2
00
01
11
10
00
X
1
1
X
01
X
0
0
X
11
X
0
0
X
10
X
0
0
X
K2= Q1 Q0
K MAP OF K3
Q 1Q0
Q 3Q2
00
01
11
10
00
X
X
0
1
01
X
X
0
0
11
X
X
0
0
10
X
X
0
0
K3= Q2 Q1 Q0
Ratheesh P.M.
Page 61 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
CIRCUIT DIAGRAM:
RESULT:
Designed and set up 4 bit up counter and 4 bit down counter circuist using JK flip flop
Ratheesh P.M.
Page 62 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 11:SEQUENCE GENERATOR
AIM:
To design and set up sequence generator circuit.
COMPONENTS AND EQUIPMENTS REQUIRED:
IC 7473,7400,7408,7432 and trainer kit.
THEORY:
Binary sequence generators are used to generate a sequence of bits. They are also called
pulse train generators. A binary is useful to switch on and off lights or devices in a predetermined
order. One technique of generation of N-length sequence is to use a mode-N asynchronous
counter with additional logic circuit. Logic circuit will derive the required binary sequence from
the counter states. Fig shows a mod 5 asynchronous counter modified to generate a 5 length
binary sequence. It generate a binary sequence 10110.
PROCEDURE:
1) Set up the mod 5 counter and verify its working.
2) Observe binary sequence output.
Ratheesh P.M.
Page 63 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
TRUTH TABLE:
Q2
0
0
0
0
1
1
1
1
Q1
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
Y
1
0
1
1
0
X
X
X
DESIGN OF INPUT VARIABLES USING KARNAUGH MAP:
K MAP
Q2Q1
Q0 0
1
00
01
11
10
1
0
1
1
X
X
0
X
S=Q1+Q2 Q0
CIRCUIT DIAGRAM:
1
CLOCK
RESULT:
Designed and set up sequence generator circuit.
Ratheesh P.M.
Page 64 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 12:JOHNSON AND RING COUNTER
AIM:
1. To design and set up four bit ring counter and Johnson counter using JK flip flop.
2. To design and set up 4 bit ring/Johnson counter with mode control using D flip flop.
COMPONENTS AND EQUIPMENTS REQUIRED:
Ics 7476,7474 and IC trainer kit.
THEORY:
Ring counter and Johnson counter are basically shift registers.
RING COUNTER:
It is constructed using JK flip flops by connecting Q and Q outputs from one flip flop to
the J and K inputs of the next flip flop. The outputs of the final flip flop are connected to the
inputs of the first flip flop. To start the counter, the FF is set using preset facility and the
remaining flip flops are reset using clear input. When the clock signal arrives, this set condition
continues to shift around the ring.
As it can be seen from the truth table, there are four unique output states for this counter,
rendering a mode 4 counter. Ring counter is called a divide by N counter where N is the number
of flip flops.
JOHNSON COUNTER :
The modulo number of a ring counter can be doubled by making a small change in the
ring counter circuit. The Q and Q outputs of the last flip flop are connected to the J and K inputs
of the first flip flop respectively. This is the Johnson counter.
Initially all the flip flops are reset. After the first clock pulse FF 0 is set and the remaining
FFs are reset. After the fourth clock pulse all the FFs are set. After fifth clock pulse FF0 is reset
and remaining FFs are set. After the eighth clock pulse all FFs are reset
There are eight different output conditions creating a mode 8 Johnson counter. Johnson
counter is also called twisted ring counter or divide by 2N counter.
Ratheesh P.M.
Page 65 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
PROCEDURE :
1. Test all the ICs and connecting wires.
2. Set up the ring counter. Apply monopulses using debouncer switch in the trainer
kit to the clock input.
3. Note down the states of the ring counter outputs on the truth table for
successive clocks.
4. Repeat the steps 1 and 2 for the Johnson counter.
5. Enter the states in a truth table for 8 clock pulses.
Ratheesh P.M.
Page 66 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
Ratheesh P.M.
Page 67 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Ratheesh P.M.
Digital Electronics Lab Manual
Page 68 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
RESULT:
Designed and set up 4 bit ring counter,johnson counter and ring/johnson counter using mode
control
Ratheesh P.M.
Page 69 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 13:SHIFT REGISTERS
AIM:
To design and set up and verify the performance of a serial in parallel out shift register using
JKFF.
COMPONENTS AND EQUIPMENT REQUIRED:
ICs 7476, 7474,7408,7404,7432 and trainer kit.
THEORY:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in
which the output of each flip-flop is connected to the "data" input of the next flip-flop in the
chain, resulting in a circuit that shifts by one position the "bit array" stored in it, shifting in the
data present at its input and shifting out the last bit in the array, at each transition of the clock
input. More generally, a shift register may be multidimensional, such that its "data in" and stage
outputs are themselves bit arrays: this is implemented simply by running several shift registers of
the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often
configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also
types that have both serial and parallel input and types with serial and parallel output. There are
also bi-directional shift registers which allow shifting in both directions: L→R or R→L. The
serial input and last output of a shift register can also be connected to create a circular shift
register.
These are the simplest kind of shift registers. The data string is presented at 'Data In', and is
shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the
far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data
Out') is shifted out and lost. The data are stored after each flip-flop on the 'Q' output, so there are
four storage 'slots' available in this arrangement; hence it is a 4-Bit Register.
SERIAL IN PARALLEL OUT (SIPO):
This configuration allows conversion from serial to parallel format. Data is input serially,
as described in the SISO section above. Once the data has been inputted, it may be either read off
at each output simultaneously, or it can be shifted out and replaced.
Ratheesh P.M.
Page 70 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
PROCEDURE:
1)Test all components and ic package using multimeter and digital ic tester.
2)set up serial input shift register using JKFF. Clear all FF using CLEAR pin. Feed 1011 to
the serial input starting from LSB using PRESET and CLEAR pin. a low input to CLEAR
and PRESET will make Q output from 0 to1 resp..
3)apply 1 HZ clock and observe the bits are shifting right.
Ratheesh P.M.
Page 71 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
RESULT:
Designed and set up and verify the performance of a serial in parallel out shift register
using JKFF.
Ratheesh P.M.
Page 72 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 14:COUNTER ICS
AIM:
To study counter ICs 7493,7490,7492,74163,74192.
COMPONENTS AND EQUIPMENTS REQUIRED:
IC 7490,7493,7492,74192,74163 and trainer kit.
THEORY:
The 7490:
The 74LS90 is a simple counter, i.e. it can count from 0 to 9 cyclically in its natural
mode. It counts the input pulses and the output is received as a 4-bit binary number through pins
QA, QB, QC and QD. The binary output is reset to 0000 at every tenth pulse and count starts from 0
again. A pulse is also generated (probably at pin 9) as it resets its output to 0000. The chip can
count up to other maximum numbers and return to zero by changing the modes of 7490. These
modes are set by changing the connection of reset pins R 1 - R4. For example, if either R1 & R2are
high or R3 & R4 are ground, then it will reset QA, QB, QC and QD to 0. If resets R3 & R4are high,
then the count on QA, QB, QC and QD goes to 1001.
The 7492:
The 7492 / 74LS92 counter IC is a 4-Bit ripple counter (4 cascaded counting elements).
The individual counting circuits inside are partitioned into two blocks, one is a divide by two
counter and the other capable of divide by 6, which when combined together effectively
implements a divide by 12, perfect for the hour tracking register for a digital clock .
The 7493:
This 14 pin DIP MSI chip is an asynchronous 4-bit binary counter. This IC is made of a
mode-2 counter followed by a mode-8 counter.Therefore,it can be configured as mode-2,mode-8
or mode-16 counter without any additional hardware.
If the clock is applied at input A and QA is connected to input B it function as a mode-16
binary ripple counter. The outputs are Q3,Q2,Q1 and Q0.If the clock is applied at input B,output
appeares at Q3,Q2 and Q1 will be of a mode-8 counter. A high level at both reset inputs R1 and
R2 will make all the flip flops reset.
The 74163:
These are synchronous counters so their outputs change precisely together on each clock pulse.
This is helpful if you need to connect their outputs to logic gates because it avoids the glitches which
Ratheesh P.M.
Page 73 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
occur with ripple counters.The count advances as the clock input becomes high (on the rising-edge).
The decade counters count from 0 to 9 (0000 to 1001 in binary). The 4-bit counters count from 0 to
15 (0000 to 1111 in binary).
For normal operation (counting) the reset, preset, count enable and carry in inputs should all be
high. When count enable is low the clock input is ignored and counting stops.The counter may
be preset by placing the desired binary number on the inputs A-D, making the preset input low, and
applying a positive pulse to the clock input. The inputs A-D may be left unconnected if not required.
The reset input is active-low so it should be high (+Vs) for normal operation (counting). When
low it resets the count to zero (0000, QA-QD low), this happens immediately with the 74160 and
74161 (standard reset), but with the 74162 and 74163 (synchronous reset) the reset occurs on the
rising-edge of the clock input.
The 74192:
These are synchronous counters so their outputs change precisely together on each clock pulse.
This is helpful if you need to connect their outputs to logic gates because it avoids the glitches which
occur with ripple counters. These counters have separate clock inputs for counting up and down. The
count increases as the up clock input becomes high (on the rising-edge). The count decreases as
the down clock input becomes high (on the rising-edge). In both cases the other clock input should
be high.For normal operation (counting) the preset input should be high and the reset input low.
When the reset input is high it resets the count to zero (0000, QA-QD low).The counter may
be preset by placing the desired binary number on the inputs A-D and briefly making
the preset input low. Note that a clock pulse is not required to preset, unlike the 74160-3 counters.
The inputs A-D may be left unconnected if not required.
PROCEDURE:
1. Test all components and connecting wires.
2. verify the working of 7493 as 4 bit binary counter.
3. Verify the working of 7490 as mode-10 counter.
4. verify the working of 7492 as divide by 12 counter.
Ratheesh P.M.
Page 74 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
PIN OUTS AND CIRCUIT DIAGRAM
IC 7490
DECADE COUNTER USING 7490
12
9
8
11
11
1
7490
14
+5V
5
2
3
6
7
10
IC 7492
Ratheesh P.M.
Page 75 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DIVIDE BY 12 COUNTER USING 7492
12
11
9
8
11
1
7492
14
+5V
5
6
7
10
IC 7493
4-BIT BINARY COUNTER USING 7493
12
9
8
11
11
1
7493
14
+5V
5
2
3
10
RESULT:
Studied various counter ICs 7490,7493,7492,74192 and 74163
Ratheesh P.M.
Page 76 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
EXP 15:SEVEN SEGMENT DISPLAY AND DECODER DRIVER
AIM:
To study seven segment display and decoder driver IC 7447.
COMPONENTS AND EQUIPMENTS REQUIRED:
IC 7447 and IC trainer kit.
THEORY:
The appropriate outputs a-g become low to display the BCD (binary coded decimal)
number supplied on inputs A-D. The 7447 has open collector outputs a-g which can sink up to
40mA. The 7-segment display segments must be connected between +Vs and the outputs with a
resistor in series (330
with a 5V supply). A common anode display is required.
Display test and blank input are active-low so they should be high for normal operation.
When display test is low all the display segments should light (showing number 8).
If the blank input is low the display will be blank when the count input is zero (0000).
This can be used to blank leading zeros when there are several display digits driven by a chain of
counters. To achieve this blank output should be connected to blank input of the next display
down the chain (the next most significant digit).
The 7447 is intended for BCD (binary coded decimal) which is input values 0 to 9 (0000
to 1001 in binary). Inputs from 10 to 15 (1010 to 1111 in binary) will light odd display segments
but will do no harm.
PROCEDURE:
1) Test all the components and IC packages using multimeter of digital IC tester.
2) Set up the circuit and observe the decimal display
Ratheesh P.M.
Page 77 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
DESIGN:
pin out of 7447:
TRUTH TABLE:
INPUTS
OUTPUTS
D
C
B
A
a
b
c
d
e
f
g
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
1
0
1
1
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Ratheesh P.M.
Page 78 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
CIRCUIT DIAGRAM:
RESULT:
Studied seven segment display and decoder driver IC 7447
Ratheesh P.M.
Page 79 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Ratheesh P.M.
Digital Electronics Lab Manual
Page 80 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Ratheesh P.M.
Digital Electronics Lab Manual
Page 81 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Ratheesh P.M.
Digital Electronics Lab Manual
Page 82 of 83
Dept. of Instrumentation, CUSAT
INS 2202 L
Digital Electronics Lab Manual
74151
Ratheesh P.M.
74154
Page 83 of 83
Dept. of Instrumentation, CUSAT