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14th International Power Electronics and Motion Control Conference, EPE-PEMC 2010 Common Mode Voltage in a Motor Drive System with PFC Firuz Zare, Jafar Adabi, Alireza Nami, Arindam Ghosh Queensland University of Technology, Brisbane, Australia [email protected] , [email protected] , [email protected] , [email protected] Abstract— Common mode voltage generated by a power converter in combination with parasitic capacitive couplings is a potential source of shaft voltage in an AC motor drive system. In this paper, a three-phase motor drive system supplied with a single-phase AC-DC diode rectifier is investigated in order to reduce shaft voltage in a three-phase AC motor drive system. In this topology, the common mode voltage generated by the inverter is influenced by the ACDC diode rectifier because the placement of the neutral point is changing in different rectifier circuit states. A pulse width modulation technique is presented by a proper placement of the zero vectors to reduce the common mode voltage level, which leads to a cost effective shaft voltage reduction technique without load current distortion, while keeping the switching frequency constant. Analysis and simulations have been presented to investigate the proposed method. Keywords— Common mode voltage, shaft voltage, diode rectifier, Adjustable speed drive, Space vector modulation I. INTRODUCTION Adjustable Speed Drive (ASD) systems are largely used in a wide range of modern systems, from household appliances to automated industry applications. The concept in the ASD systems is the use of a power electronics module to convert a constant frequency (50 or 60 Hz) AC voltage source to an AC variable frequency waveform to achieve an adjustable speed [1-2]. Regarding the growing requirements of speed control, pulse width modulated (PWM) inverters are used in ASD systems. The development of PWM-based drive systems increased the efficiency, performance, and controllability in AC motor applications, low acoustic noise and more efficient power conversion. However, as the switching speed of the power switches is increased to allow higher carrier frequencies, new concerns arose due to the interface of power converters and AC motor characteristics which was previously seen only in wave transmission devices like antenna and broadcast signal equipments. The effects of the high frequency voltage components introduced by the PWM technique are usually neglected when the electromechanical performance of the motor is analysed. Many small capacitive couplings exist in the motor drive systems which may be neglected in low frequency analysis, but 978-1-4244-7855-2/10/$26.00 ©2010 IEEE the conditions are completely different in high frequencies [3-6]. As a consequent of PWM patterns in three-phase inverter, a voltage will be generated between a neutral point and the ground, which is called common mode voltage. This voltage acts as a source for many unwanted problems in motor drives such as shaft voltage and bearing currents due to the existence of parasitic capacitances in the motor. It will be shown that the switching state creates the common-mode voltage regardless of the motor impedance [7-8]. An LC filter can be used to eliminate the low order harmonics and remove the pulse width modulated signal from the pulse shape generated by an inverter and the common mode voltage will therefore be eliminated. The main drawback of using the filter is its bulky size especially in large motor drive systems. Then, a proper PWM technique is the best possible solution to reduce or eliminate the common mode voltage. Assuming no parasitic coupling, an induction motor will only experience differential mode voltages and will behave as an ordinary three-phase sinusoidal AC supply [9-10]. However, as the switching speeds of a converter are increased due to switching device improvements, the parasitic capacitive coupling becomes a dominant side effect. Two major parasitic coupling paths what can affect shaft voltage are the stator windings to the stator iron and the stator windings to the rotor iron [11-12]. The capacitive couplings in the motor structure and common mode voltage generated by the inverter forms a model for the ASD system, which leads to a voltage across the rotor and stator frames called shaft voltage. Fig.1.a shows the structures of an AC motor where the parasitic capacitive couplings exist between the stator winding and rotor (Cwr), the winding and stator frame (Cws), the rotor and stator frame (Crs), and outer and inner races of the ball bearing (CBO, CBI). A simple high frequency model of the motor is shown in Fig.1.b and shaft voltage can be calculated as: Vshaft = C wr × Vcom C b + C rs + C wr (1) Shaft voltage is the main cause of the motor bearing current and leads to bearing damage and decrement of the bearing lifetime. Shaft voltage is influenced by various factors such as: the design of the generator, capacitive T4-57 couplings between different parts of the machine structure, the configuration of the main supply, voltage transient on the machine terminals, and switching states in PWM pattern. Generally, the solutions to reduce this phenomenon are based on the motor design consideration (to decrease the effective capacitive couplings in the first step of the design (13)) and the common mode voltage reduction by proper PWM techniques which are studied in [14-15] via PWM without zero vectors in three-phase in inverters, multilevel inverter topology , and reducing DC link voltage. Cws C rs CBO Cwr Regarding the different placements of the neutral point, proper switching states will be applied in the PWM pulse pattern to decrease the common mode voltage. II. COMMON MODE VOLTAGE AND SHAFT VOLTAGE IN ASD SYSTEMS Fig.2 shows a DC-AC converter connected to an AC motor assuming that the ground (g) is connected to the negative point of the DC link (n). Basically, a three-phase inverter consists of a DC link and three pairs of switching components. The switches turn on and off to generate an AC voltage of the output. The six-switch combination of this inverter has eight permitted switching vectors which have been shown in Fig.2.b. In a three-phase system, (Vag Vbg Vcg) are the leg voltages of a three-phase converter, respectively. Vog is the voltage between the neutral point and the ground (common mode voltage). In this section, a constant DC voltage is considered as a DC source for the inverter. CBI Shaft Rotor Stator winding Cwr Stator frame Cws (a) winding Rotor + Cwr Vcom Cws Crs Cb Vshaft - Stator frame (a) (b) Fig.1. (a) Structure of an AC motor with different parasitic capacitive couplings (b) common mode model In this paper, a single-phase diode rectifier is used to supply a three-phase motor by a single-phase AC voltage source. As the input current of the rectifier is highly distorted, a Power Factor Correction (PFC) unit with boost converter technique is used to improve the current quality of the AC source. A survey on power factor correction of the single-phase rectifiers is presented in [16] and the design of a single-phase rectifier with improved power factor and low THD using boost converter technique is investigated in [17]. In the ASD system with single-phase rectifier topology, the common mode voltage generated by the inverter is influenced by the AC-DC diode rectifier, because the placement of the neutral point is changing in different rectifier circuit states. Zero switching vectors are the most important vectors in terms of common mode voltage generations. (b) Fig.2. (a) A three-phase converter (b) eight possible switching vectors Regardless of the type of modulation technique, in each switching cycle (Ts) different switching states will be employed. For instance, in a Space Vector Modulation T4-58 (SVM) pulse pattern, a control strategy is implemented to treat the sinusoidal voltage as a constant amplitude vector rotating at constant frequency. The PWM technique approximates the reference voltage (Vref) by a combination of eight switching patterns (V0 to V7). A three-phase voltage is transformed into a vector in the stationary dq coordinate frame which represents the three-phase voltage in abc coordinate. The vectors V1 to V6 divide the plane into six sectors (each sector: 60 degrees). Vref is generated by two adjacent non-zero vectors (V1 to V6) and two zero vectors (V0 and V7), and the duration of each vectors depend on the magnitude of reference voltage. Suppose that the vectors (V0, V1, V2, V7, V2, V1, V0) are employed for the switching sequence in sector I, according to Fig.2, three leg voltages of the converter can be calculated as follows: ⎧V ag ( t ) = V ao ( t ) + V og ( t ) ⎪⎪ ⎨V bg ( t ) = V bo ( t ) + V og ( t ) ⎪ ⎩⎪V cg ( t ) = V co ( t ) + V og ( t ) (2) By adding two sides of Eq.2: Vag (t) + Vbg (t ) + Vcg (t) = Vao (t ) + Vbo (t ) + Vco (t) + 3 × Vog (t ) (3) It is obvious that the sum of three-phase voltages is equal to zero ( Vao ( t ) + Vbo ( t ) + Vco ( t ) = 0 ). Therefore, the common mode voltage can be calculated as: Vog (t ) = Vag (t ) + Vbg ( t ) + Vcg (t ) 3 (4) The switching states of the proposed converter, the leg voltages and the resultant common mode voltage are shown in Table.1. According to the switching states in this table and the proposed switching sequence, the three leg voltages of the inverter are shown in Fig.3. Fig.3. leg and common mode voltages for proposed pulse pattern TABLE I. SWITCHING STATES, OUTPUT LEG VOLTAGE OF THREE-PHASE INVERTER vector V1 V2 V3 V4 V5 V6 V7 V0 S1 1 1 0 0 0 1 1 0 S3 0 1 1 1 0 0 1 0 S5 0 0 0 1 1 1 1 0 Vag Vdc Vdc 0 0 0 Vdc Vdc 0 Vbg 0 Vdc Vdc Vdc 0 0 Vdc 0 Vcg 0 0 0 Vdc Vdc Vdc Vdc 0 Vcom Vdc/3 2Vdc/3 Vdc/3 2Vdc/3 Vdc/3 2Vdc/3 Vdc 0 It is obvious that the common mode voltage can be controlled by an appropriate switching pattern. Note that the ground placement is an important issue in common mode voltage calculation. Suppose that the ground is connected to the positive point of DC link, V0 is the zero vector which is generating the maximum negative common mode voltage (all three lower switches are turned on and all leg voltages will be -Vdc). Consequently, the common mode voltage will be -Vdc. The same scenario is valid for the V7 which leads to a common mode voltage Vdc. These zero vectors should be eliminated in switching sequences to reduce the common mode voltage significantly but elimination of the zero switching vectors leads to a variable switching frequency or more current ripple. The scenario of the ground placement changing takes place in the single phase diode rectifier topology which is used as a voltage source for a three phase inverter system and will be discussed in detail in the following sections. III. COMMON MODE VOLTAGE IN THREE-PHASE ASD SYSTEM SUPPLIED WITH A SINGLE-PHASE DIODE RECTIFIER WITHOUT PFC A. Circuit Description Fig.4.a shows an ASD supplied by a three-phase inverter system. The DC link voltage of the inverter is regulated by a single phase diode rectifier connected to an AC supply. As shown in Fig.4.b, while the AC voltage is in positive half a cycle, the diodes D1D4 are in forward bias to charge the DC link capacitor (Interval 1 according to Fig.4 and 5), so that ground is connected to the bottom of the DC link. In the discharging interval (Interval 2), the diode rectifier will be disconnected from the DC-link as DC link voltage is greater than the input voltage. Same charging (Interval 3) and discharging (Interval 4) intervals occurs in the negative half a cycle; however due to the forward bias across D2D3, ground is connected to the point “p” of the DC link in the charging period (see Fig.4.c). The DC link voltage waveform in all intervals is demonstrated in Fig.5. According to the circuit configuration in the different subintervals, the ground is not fixed in all intervals in contrast with configuration in Fig.2.a, and it is changed between the point “n” in the positive half a cycle and the point “p” in the negative half a cycle. This can affect the common mode voltage by choosing the switching vectors. This issue will be analyzed with simulation results in the following sections. T4-59 shows the common mode voltage for the proposed system. It shows that by applying V0 and V7, we have the maximum common mode voltage level in both positive and negative half a cycles. By applying V0 to an inverter, three lower switches of the inverter are turned on. If the ground is connected to the positive point of DC link (charging state of capacitor in negative half a cycle of the rectifier), all three leg voltages would be Vng and based on the Eq.4, common mode voltage would be Vng which is the maximum negative value of the common mode voltage. The same scenario is valid for applying V7 especially when the ground is connected to the negative point of DC link (charging state of capacitor in positive half a cycle of the rectifier). All three leg voltages would be Vpg, and consequently, the common mode voltage will be Vpg. p Single Phase AC Source D1 S1 D3 a D2 S3 AC Motor o b S2 D4 S5 S4 c S6 g Single Phase AC-DC diode rectifier n (a) Three Phase DC-AC Inverter positive half cycle p Interval 1 Interval 2 p D1 D3 i i Cdc-link D2 Cdc-link D4 300 g n n Interval 4 200 100 0 ng p &V ) p -100 (V pg D3 i i Cdc-link Cdc-link D2 dc (b) negative half cycle Interval 3 g D1 DC link (V ) g -200 -300 D4 300 c om n Common mode (V n ) 200 g (c) Fig.4. (a) an ASD system supplied with a single-phase diode rectifier and circuit behavior in (b) charging and (b) discharging states of the capacitor in positive and negative half a cycle B. Simulation Results Simulations have been conducted based on the configuration shown in Fig.4 in which a 300 volts AC voltage is regulated through a single-phase diode rectifier connected to a DC link capacitor of 100 µF. Space vector modulation technique (fs=5 kHz) is implemented in the proposed system to reduce maximum levels of the common mode voltage. Voltage waveforms across the DC link and the positive and negative points of the DC link with respect to the ground are shown in Fig.5. As mentioned in Table.1 and shown in Fig.3, common mode voltage is changed between different voltage levels. Note that the voltage levels at this table are based on a constant DC source which is grounded to the lower point of the DC link. Here, with the single-phase rectifier as a source of inverter, both the positive and negative point of the DC link have a voltage with respect to the ground. Therefore, the common mode voltage is changing between maximum positive and minimum negative DC link voltage. Different space vector switching sequences have been tested to analyze the effects of the switching pattern on common mode voltage. In this case, a typical pulse pattern of (V0, V1, V2, V7, V2, V1, V0) has been employed for the inverter. Fig.5 also 100 0 -100 -200 -300 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 Ti m e (s ) Fig.5. DC link voltage, voltages of positive and negative points of DC link respect to the ground and common mode voltage for switching sequence of (V0, V1, V2, V7, V2, V1, V0) As shown in Fig.5, the worst case of common mode voltage happens on the maximum voltage of the positive point of DC link (Vpg) and the minimum voltage of negative point of the DC link while the capacitor is charging and its value is at its maximum value. It is clear that in the discharging states of the capacitor, the DC link voltages decreases which leads to a lower common mode voltage. Fig.6 shows the leg voltage and the common mode voltage in two different switching cycles in positive and negative half a cycles. It is obvious that by zero switching vectors V0 and V7, we will have maximum common mode voltage levels of +300 and -300 volts respectively. As shown in Fig.5, applying zero vectors leads to maximum common mode voltage. Using only active voltage vectors (V1-V6) can reduce the common mode voltage significantly, but a main drawback is the quality of load current. Removing V0 and V7 requires adding another active vector in order to have a constant T4-60 switching frequency. This modulation method increases the load current harmonics. In the inverter system connected to a single-phase diode rectifier, there are some choices which are possible to minimize the common mode voltage with keeping the zero vectors in the switching sequences by using the different ground placement as a benefit. Fig.7 shows the leg voltages and common mode voltage in two different switching cycles in positive and negative half a cycle for proposed switching sequence. Negati ve half a cycle Leg a Positive half a cycle Leg a 300 300 200 200 100 300 300 200 200 200 200 100 100 100 100 0 0 Leg b 300 300 200 200 100 Leg b 100 300 0 300 200 200 Leg c 200 100 100 0 Com m on m o de 300 -100 100 100 -200 -300 0 Ts 0 Ts Ts Fi.6. Leg voltages and common mode voltage in two different switching cycles in positive and negative half a cycle for switching sequence of (V0, V1, V2, V7, V2, V1, V0) In a without PFC system, the zero voltage vectors should be applied in the charging intervals (V0 and V7 should be applied in charging intervals of positive and negative half a cycles respectively), because the ground is connected to either positive or negative points of the DC link and applying these vectors leads to zero leg voltages. In this case, the common mode voltage generated by the inverter is influenced by the AC-DC diode rectifier. In the positive half a cycle, ground is connected to the lower point so that V0 is the suitable zero switching vector. A switching sequence of (V0, V1, V2, V1, V0) is employed for the proposed system in the positive half a cycle. It can be seen that the maximum common mode voltage level in the positive half a cycle is decreased by one-third because the ground during the capacitor’s charging state in this half a cycle is connected to the negative point of DC link, and applying V0 (in which all three bottom switches of the inverter are switched on) leads to a zero common mode voltage instead of achieving maximum positive value. In the negative half a cycle where the positive point of the DC link is connected to the ground, V7 is the proper option. Also, a switching sequence of (V7, V2, V1, V2, V7) is employed for the proposed system. It can be seen that the maximum common mode voltage level in the negative half a cycle is decreased by one-third because the ground during the capacitor’s charging state in this half a cycle is connected to the positive point of DC link and applying V7 (in which all three upper switches of the inverter is switched on) leads to a zero common mode voltage instead of achieving maximum negative value. The comparison between the common mode voltage obtained in Fig.5 (with V0 and V7 in a switching cycle) and Fig.8 (V0 in the first half a cycle and V7 in the negative half a cycle) shows the influence of the proposed pulse pattern. 300 200 dc -100 0 Fig.7. Leg voltages and common mode voltage in two different switching cycles in positive and negative half a cycle for switching sequence of (V0, V1, V2, V1, V0) in positive half a cycle and (V7, V2, V1, V2, V7) in negative half a cycle 100 0 ng 200 Ts -300 0 -100 pg 300 0 Com m on m ode (V &V ) DC link(V ) 0 Com m on m ode -200 -300 300 200 ) 0 0 -200 100 0 Com m on m ode 0 200 100 Leg c 300 200 0 Leg c Leg b 0 Le g c 300 c om Vol tage(V) 0 L eg b 300 0 Vol tage(V) 100 0 300 0 Vol tage(V) N e g a ti ve h a l f a cycl e Leg b Common mode (V Vol tage(V) Po s i ti ve h a l f a c ycl e Leg a 100 0 -100 -200 -300 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 Ti m e (s ) Fig.8. DC link voltage, voltages of positive and negative points of DC link respect to the ground and common mode voltage for switching sequence of (V0, V1, V2, V1, V0) in positive half a cycle and (V7, V2, V1, V2, V7) in negative half a cycle As shown in Fig.9, the input current is distorted significantly and using a power factor corrector is necessary to improve the input current quality and the system power factor. A PFC unit is used to shape the input current to a sinusoidal waveform in phase with the T4-61 input voltage which will be discussed in the next section and common mode voltage analysis will be mentioned. 60 40 20 0 -20 -40 -60 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 Ti m e (s ) Fig.9. input current of the proposed system IV. COMMON MODE VOLTAGE IN THREE-PHASE ASD SYSTEM SUPPLIED WITH A SINGLE-PHASE DIODE RECTIFIER WITH A PFC SYSTEM A. Circuit Description Fig.10.a shows the structure of an ASD system with a single phase diode rectifier and PFC system where the input current is controlled using a boost converter technique. Current control technique benefits power electronic converters. Hysteresis current control is a simple current control with fast dynamic response [18]. Therefore, in this topology the inductor current will be compared to a reference current and forced to be kept inside the upper and lower hysteresis bands. This results in a sinusoidal current waveform at the input side as shown in Fig.11. Also, a space vector modulation strategy is employed for the inverter switching control. Fig.10.b shows the behavior of the proposed system in the positive half a cycle of the input voltage. When the input voltage is positive, the neutral line is connected to the negative DC link line for the half a cycle. The positive DC link line has maximum potential with respect to the neutral which has a significant impact on the common mode voltage. Also, Fig.10.c shows the behaviour of the system in the negative half a cycle where the neutral point is connected to the inductor. B. Simulation Results Simulations have been conducted for the circuit topology shown in Fig.10.a, in which a hysteresis current control is used to control the PFC switch (to generate an 11A sinusoidal current). A space vector modulation with a switching frequency of 5 kHz is used to control the threephase inverter. Other parameters are the same as those in Section 3.2. Fig.11 shows the inductor and input current controlled within the hysteresis bands which generates a sine wave current. It is clear that the quality of the input current has been improved significantly with a PFC unit. In d cu to r cu r r e n t 15 Current(A) 10 5 0 (a) -5 In p u t c u r re n t 15 Current(A) 10 5 0 -5 -10 -15 0 (b) 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 Ti m e (s ) Fig.11. Inductor and input currents with a PFC (c) Fig.10. (a) a schematic of an ASD system supplied by a single-phase diode rectifier with PFC in (b) positive half a cycle and (c) negative half a cycle A typical pulse pattern of (V0, V1, V2, V7, V2, V1, V0) has been employed for the inverter. Fig.12 shows the DC link voltage and the voltages of the positive and negative points of the DC link with respect to the ground (Vpg and Vng). Applying V0 and V7 to the pulse pattern leads to maximum common mode voltage, which changes between voltages Vpg and Vng. T4-62 (V pg ng &V ) dc DC link(V ) 300 200 100 0 -100 -200 -300 200 Common mode (V c om ) 300 100 0 -100 -200 -300 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 Ti m e (s ) Fig.12. DC link voltage, voltages at positive and negative points of DC link with respect to the ground and common mode voltage for switching sequence of (V0, V1, V2, V7, V2, V1, V0) As mentioned in the previous section, by using one of the zero switching vectors, the benefit of changing the neutral point location can be used. A switching sequence of (V0, V1, V2, V1, V0) is employed to minimize the common mode voltage. Fig.13 shows the leg voltages and common mode voltage with proposed switching sequence. L e g a (Va ) 300 200 100 200 300 a Leg a(V ) L e g b (Vb ) 0 system with PFC, the neutral point is connected to the negative point for the whole duration of positive half a cycle. Therefore applying V0 leads to decrement of the common mode voltage by one-third in positive half a cycle. This strategy will not help to remove the maximum level of common mode voltage (-300 volts) in negative half a cycle. A switching sequence of (V7, V2, V1, V2, V7) has also been tested which gives different leg and common mode voltages as shown in Fig.14. According to Fig.10.c, in the negative half a cycle, the neutral point is connected to the inductor. Based on Fig.13, the maximum common mode voltage level in the negative half a cycle occurred when the voltage of the positive point to the ground is in its minimum value (around zero). Therefore applying V7 minimizes the common mode voltage in negative half a cycle by one third. The maximum common mode voltage value still exists in the positive half a cycle. As mentioned in the previous section, a solution to reduce the shaft voltage is to use only V0 voltage vector in the positive half a cycle in which it has the lowest potential with respect to the neutral. V7 will be applied in the negative half a cycle where the neutral line is connected to PFC inductor and negative DC link is connected to the source voltage. Therefore, it is better to apply V7 as a zero vector in negative half a cycle to create the lowest possible common mode voltage without distortion of the load current. Fig.15 shows the leg voltages and the common mode voltage of the system with the proposed PWM strategy. Comparison of the common mode voltage achieved in Fig.15 with the voltage shown in Fig.12 shows the effectiveness of proposed switching strategy on the common mode voltage. This method is a cost effective technique which leads to a lower possible shaft voltage in adjustable speed drives supplied with a singlephase diode rectifier. c L e g c(V ) 0 200 100 b Leg b(V ) 0 0 300 200 0 300 c Leg c(V ) 200 100 0 200 100 0 300 -100 c om ) 200 -200 -300 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 Common mode(V C o m m o n m o d e (V c o m ) 200 0.008 Ti m e (s ) Fig.13. Leg voltages and common mode voltage for switching sequence of (V0, V1, V2, V1, V0) As shown in Fig.10.b, in the positive half a cycle, neutral point is connected to the negative point of the DC link capacitor. The difference between PFC and not using PFC is that the neutral point in a system without PFC is connected to the negative point only in capacitor’s charging state in the positive half a cycle. However, in a 100 0 -100 -200 -300 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 Ti m e ( s ) Fig.14. Leg voltages and common mode voltage for switching sequence of (V7, V2, V1, V2, V7) T4-63 [6] a Leg a(V ) 300 200 100 [7] b Leg b(V ) 0 300 200 [8] 100 c Leg c(V ) 0 300 200 100 [9] 0 300 Common mode(V com ) 200 [10] 100 0 -100 [11] -200 -300 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 Ti m e (s ) Fig.15. Leg voltages and common mode voltage for switching sequence of (V0, V1, V2, V1, V0) for positive half a cycle and sequence of (V7, V2, V1, V2, V7) for negative half a cycle. V. CONCLUSIONS [12] [13] [14] A three-phase inverter system supplied by a single-phase diode rectifier with and without PFC has been studied in terms of common mode generation. Different placements of the ground in different diode rectifier ciscuit intervals can influence the common mode voltage. Therfore, a PWM technique is presented by a proper placement of the zero vectors to reduce the common mode voltage level. This method leads to a cost effective shaft voltage reduction technique without load current distortion and keeping the switching frequency constant. Analysis and simulations have been presented to verify the proposed method. [15] [16] [17] [18] ACKNOWLEDGMENT The authors thank the Australian Research Council (ARC) for the financial support for this project through the ARC Discovery Grant DP0774497. REFERENCES [1] [2] [3] [4] [5] J.C. Rama, A. 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