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Multilevel Converters:
Fundamental Circuits and
Systems
By H i rof u m i A k agi , Fellow IEEE
ABSTRACT | This paper provides a chronological overview
of the topology for multilevel converters, and discusses their
different terminology usages and characteristics. The multilevel
converters include three-level neutral-point-clamped (NPC)
and neutral-point-piloted (NPP) inverters, three-level and fourlevel flying-capacitor (FLC) inverters, and a family of modular
multilevel cascade converters. Some have already been put into
commercial use, some have been on a research and development
stage, and others have been on an academic research stage.
This paper pays much attention to six family members of the
modular multilevel cascade converters, intended for grid-tied
applications and medium-voltage high-power motor drives.
KEYWORDS | Capacitor-clamped inverters; cascaded H-bridge
converters; diode-clamped inverters; flying-capacitor (FLC)
inverters; grid-tied applications; motor drives; multilevel
converters; neutral-point-clamped (NPC) inverters; pulsewidth
modulation (PWM)
I. I N T RODUC T ION
Multilevel converters or more strictly speaking, multilevel
voltage-source converters bring multilevel waveforms of
voltage to their alternating current (ac) terminals. The prefix
“multi” of the technical term “multilevel” means any positive
integer more than two, in contrast to traditional two-level
voltage-source converters. Moreover, the multilevel converters do not include any transformer for synthesizing or
forming multilevel voltage waveforms although the technical
term does not include any explicit information about that.
Throughout this paper, “inverters” take the positive
direction of power flow from the direct current (dc) input to
the ac output, whereas “rectifiers” from the ac input to the
Manuscript received January 6, 2017; revised February 6, 2017; accepted
February 15, 2017. This work was partially supported by the Japan Society for
the Promotion of Science under Grants-in-Aid for Scientific Research (A) with
project number 25249029.
The author is with the Department of Electrical and Electronic Engineering, Tokyo
Institute of Technology, Tokyo 152-8552, Japan (e-mail: akagi@ee.titech.ac.jp).
dc output. On the other hand, “converters” pay no attention to the direction of power flow, or represent direct
ac-to-ac power conversion.
A. Historical Review of Multilevel Converters
In 1979, Nabae, Takahashi, and Akagi invented a
three-level neutral-point-clamped (NPC) inverter capable of being free of simultaneous switching of two seriesconnected bipolar junction transistors (BJTs) per arm.
They designed, built, and tested an adjustable-speed
motor drive that combined a three-phase three-level NPC
inverter using 12 BJTs, 12 free-wheeling diodes, and six
clamping diodes with an induction motor rated at 200
V and 2.2 kW. They presented a short paper including
experimental results of the motor drive in March 1980 [1].
Then, they presented the full paper at the 1980 IEEE IAS
Annual Meeting in October, which was followed by its
IEEE Transactions paper in September 1981 [2]. On the
other hand, Baker applied for a circuit patent including
the NPC inverter topology in 1979 although he did not
disclose any experimental verification in his patent [3].
Since the three-level NPC inverter was put into practical use at the beginning of the 1990s, it has been recognized as the dawn of “classic” multilevel inverters. Today,
this inverter is often referred to as the three-level diodeclamped inverter, the naming of which comes from the
use of six clamping diodes.
In 1992, Meynard and Foch invented the three-level
flying-capacitor (FLC) inverter [4]. It is often referred
to as the three-level capacitor-clamped inverter, paying
attention to a capacitor for clamping the ac output terminal of each phase leg to half of the dc input voltage.
In 1994, Robicon Corporation, presently a part of
Siemens AG, put medium-voltage high-power motor
drives using multilevel inverters on the market [5]. The
emergence of these products surprised and impressed
research scientists and engineers who were engaged
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
in research and development of medium-voltage motor
drives. The per-phase circuit configuration of the multilevel
inverter is based on the cascade connection of the ac output
terminals of modular single-phase full-bridge or “H-bridge”
inverter cells with pulsewidth modulation (PWM). Since
1994, this multilevel inverter has been recognized as the
origin of “modern” multilevel inverters.
In 1996, Lai and Peng presented a static synchronous
compensator (STATCOM) for reactive-power control in
power transmission systems [6], [7]. This topology is based
on the cascade connection of multiple H-bridge (singlephase full-bridge) cells with staircase modulation (SCM).
The actual switching frequency of SCM is equal to the line
frequency, intended for switching-loss reduction.
In 2003, Marquardt and his coauthors presented the
circuit configurations named modular multilevel converters (MMCs), and described its basic principles of operation
[8]–[11]. Since then, many research scientists and engineers of power electronics have conducted comprehensive
research on the MMCs intended for applications to HVDC
(high-voltage direct current) and BTB (back-to-back) systems, as well as medium-voltage motor drives.
B. Terminology Issue
The name/designation of a “modular multilevel converter” makes it impossible for the beginners of power electronics to distinguish one circuit configuration from the others. The reason is that both terms “modular” and “multilevel”
do not have enough information to identify their circuit
configurations. Moreover, it is reasonable to call the modular multilevel converter as a “cascade multilevel converter”
because the converter is based on the cascade connection
of the arm-side terminals of multiple modular bidirectional
choppers. Nevertheless, it is also appropriate to use the term
“modular multilevel converter” as a proper noun.
On the other hand, the multilevel inverter that Robicon
Corporation has put on the market is referred to as a “cascade
multilevel inverter” [7], a “cascaded H-bridge inverter” [12],
or a “chain-link multilevel inverter” [13]. This means that
different manufactures or companies use different names,
like trade names. However, the multilevel inverter can be
considered also as a “modular multilevel inverter” because it
is one of the modular multilevel inverters on the basis of the
cascade connection of multiple modular H-bridge cells. This
may lead to the following confusion: When a power electronics engineer uses either “modular multilevel converter”
or “cascade multilevel converter” in his/her technical paper/
article or presentation, the other engineers cannot identify
the circuit configuration or may have a misunderstanding
about it in the worst case [14].
C. A Solution to the Issue
To avoid the aforementioned confusion, this paper introduces a combination of a given/first name and a family/last
2 Proceedings of the IEEE
name to the modern multilevel converters including six different circuit configurations. The family/last name of “modular multilevel cascade converters” merges the two terms
“cascade multilevel converters” and “modular multilevel
converters” together [14]. The following given/first names
are assigned to the six family members:
• single-star bridge cell (SSBC) or a “cascade multilevel
converter with star configuration” in [7];
• double-star bridge cell (DSBC) or an “MMC with fullbridge submodules” in [15];
• triple-star bridge cell (TSBC) or a “modular multilevel
matrix converter” in [16];
• single-delta bridge cell (SDBC) or a “cascade multilevel converter with delta configuration” in [7];
• double-delta bridge cell (DDBC) or a “hexagonal converter” in [17];
• double-star chopper cell (DSCC) or an “MMC with
half-bridge submodules” in [15].
These given/first names can be used to identify the
six individual circuit configurations. Note that the DSCC
converter can be considered as a special case of the DSBC
converter from a topological point of view, as described in
Section V-B.
D. Overview of This Paper
This paper makes an extensive description of multilevel
converters, laying emphasis on fundamental circuits and
systems. It starts with three-level NPC and neutral-pointpiloted (NPP) inverters, and three-level and four-level FLC
inverters, followed by the modular multilevel cascade converter (MMCC) family.
Finally, this paper provides an intensive discussion on
a DSCC-based back-to-back (BTB) system for an asynchronous intertie between two power systems, as well as two sets
of motor drives based on a DSCC inverter and a TSBC converter. Attention is paid to a difference in motor-driving performance between the two converters. Three downscaled
systems were designed, built, and tested in the author’s laboratory. Experimental waveforms obtained from the downscaled systems are included to reveal the characteristics of
the two converters.
II. T H R EE-L E V EL N P C A N D N PP
I N V ERT ER S
Fig. 1 shows the following two circuit configurations on a
per-leg basis; the three-level NPC inverter in (a) and the
three-level NPP inverter in (b), where an insulated-gate
bipolar transistor (IGBT) is used as a switching device.
Historically, Nabae et al. [2] made an in-depth
description of topology, control, and verification of the
NPC inverter. In addition, they introduced the NPP
inverter resulting from the NPC inverter. Holtz built and
tested a prototype of the NPP phase leg, using thyristors
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
in 1977 [18]. Because the thyrsitor-based NPP phase leg
needs a forced-commutation technique, it looks much more
complicated in circuit configuration than the IGBT-based
NPP phase leg shown in Fig. 1(b). Guennegues et al. [19]
named this topology the “NPP inverter” for the first time,
applying it to high-speed motor drives.
The NPC and NPP inverters look slightly different in
topology. However, they are theoretically the same in operation, control, and waveform. The NPC inverter takes the following advantages over a traditional two-level inverter that
consists of two series-connected IGBTs per arm without the
two clamping diodes shown in Fig. 1(a):
• The NPC inverter brings a three-level voltage to the
ac terminals. This means that a voltage step at the ac
terminals in the NPC inverter is reduced to half of that
in the two-level inverter.
• The NPC inverter requires no simultaneous switching
of the two series-connected IGBTs per arm.
a nonnegligible built-in voltage whereas the SiC-MOSFET
has no built-in voltage.
Since the beginning of the 1990s, the three-level NPC
inverters have been put into practical use for various industrial medium-voltage and low-voltage motor drives, including
steel-mill drives [20]. Since 1999, the Japanese high-speed
train or the “Shinkansen” has been using a three-level NPC
rectifier/inverter system capable of regenerative braking.
A three-level active NPC (ANPC) inverter [21] was first
introduced in 2001 for the purpose of improving the unequal
loss distribution of the original NPC inverter shown in Fig. 1.
This circuit configuration is characterized by replacing each
clamping diode with a pair of an IGBT and a diode connected
in antiparallel each other. The original NPC inverter is sometimes referred to as the passive NPC (PNPC) inverter to avoid
the confusion of it with the ANPC inverter.
III. F I V E-L E V EL N P C I N V ERT ER S
The NPP inverter would be preferable to the NPC inverter
when the maximum dc input voltage is lower than, for example, 750 V. The reason is because a single 1.2-kV IGBT can
be used as a switching device per arm, and as two 600-V
IGBTs connected in anti-series for voltage clamping. Thus,
the NPP inverter has been used as low-voltage photovoltaic
(PV) inverter for grid-tied applications. However, the NPC
inverter using 1.2-kV IGBTs and 1.2-kV free-wheeling diodes,
as well as 1.2-kV clamping diodes, would be preferable for the
1.5-kV​d​ c​PV inverter. In particular, the NPC inverter would be
superior to the NPP inverter in efficiency and cost if silicon
carbide (SiC)-MOSFET dual modules and Schottky barrier
diode (SBD) dual modules were available. The reason comes
from the following fact: The NPC inverter per leg consists of
two 1.2-kV SiC-MOSFET dual modules and a single 1.2-kV
SiC-SBD dual module. On the other hand, the NPP inverter
consists of a single 2.5-kV SiC-MOSFET dual module and a
single 1.2-kV SiC-MOSFET dual module in which the two
SiC-MOSFETs are connected in anti-series. As a result, a set
of the two series-connected 1.2-kV SiC-MOSFETs in the NPC
inverter is lower in on-state resistance than the single 2.5-kV
SiC-MOSFET in the NPP inverter. On the other hand, a set
of two series-connected 1.2-kV Si-IGBTs is higher in on-state
voltage than a single 2.5-kV Si-IGBT because the Si-IGBT has
Fig. 2 shows a three-phase “three-leg” five-level NPC inverter
equipped with a single dc-voltage-balancing circuit [22]. This
comes from a straightforward extension of the three-level
NPC inverter shown in Fig. 1(a). Note that all the IGBTs and
diodes used in Fig. 2 have the same voltage rating of 4.5 kV for
driving the 6.6-kV induction motor. The voltage at midpoint
M with respect to the negative dc bus can be regulated to
4.5 kV (= 9 kV/2) by control without any auxiliary circuit.
However, the individual voltages across capacitors ​​C​dc1​​​ and​​
C​dc2​​​, as well as those across capacitors C
​​ ​dc3​​​ and ​​C​dc4​​​, should
be regulated to 2.25 kV (= 4.5 kV/2) by the voltage-balancing circuit shown in Fig. 2. Unless the balancing circuit
exists, capacitors ​​C​dc2​​​ and ​​C​dc3​​​ continue discharging, while
capacitors ​​C​dc1​​​ and ​​Cdc4
​ ​​​continue charging. A single threephase six-pulse diode rectifier is connected directly to the 6.6kV ac mains without transformer. Each arm of the diode rectifier consists of four diodes connected in series. Therefore, a
practical solution to harmonic mitigation would be to install
Fig. 1. Per-leg circuit configurations of the three-level NPC and NPP
Fig. 2. A three-phase ªthree-legº five-level NPC inverter with a
dc-voltage-balancing circuit [22].
inverters. (a) The NPC inverter [2]. (b) The NPP inverter [19].
Proceedings of the IEEE 3
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 4. Per-leg circuit configurations of the three-level and fourlevel FLC inverters [4]. (a) The three-level FLC inverter. (b) The
four-level FLC inverter.
I V. T H R EE-L E V EL A N D FOU R-L E V EL
F L C I N V ERT ER S
Fig. 3. Another three-phase ªsix-legº five-level NPC inverter with
three isolated dc-power supplies [25], [26].
a transformerless hybrid active filter [23] at the 6.6-kV ac
mains side, in order to comply with harmonic guidelines in
an actual system. See Fig. 16(a).
Hasegawa and Akagi [22] designed, built, and tested
the 200-V, 5.5-kW, 50-Hz induction motor drive system
using a three-phase “three-leg” five-level NPC inverter.
Experimental waveforms obtained from the downscaled system verified the effectiveness and validity of the five-level
NPC inverter shown in Fig. 2. However, no company or
manufacturer has commercialized any three-phase “threeleg” four-level or five-level NPC inverter although academic
research is going on [22], [24].
Fig. 3 shows another three-phase five-level inverter
based on a “six-leg” three-level NPC inverter. Unlike
Fig. 2, it requires three isolated dc-power supplies combining a three-phase 36-pulse transformer with three sets
of three-phase 12-pulse diode rectifiers [25], [26]. Several
companies in Japan, Europe, the United States, and so on,
have already commercialized such a “six-leg” five-level NPC
inverter capable of driving medium-voltage high-power
motors. When the five-level inverter drives a three-phase
induction motor having open-end stator windings, the three
isolated dc-power supplies can be replaced with a single dcpower supply. However, this circuit configuration requires
six power cables to send electric power from the five-level
inverter to the open-end-winding motor with six ac-input
terminals. Therefore, no manufacturer would prefer six
power cables to three power cables when the open-endwinding motor were far away from the five-level inverter.
4 Proceedings of the IEEE
Fig. 4 shows three-level and four-level FLC inverters. For
example, the three-level FLC inverter is required to maintain the FLC voltage at half the dc input voltage. Some scientists and engineers of power electronics have done extensive research on capacitor-voltage control, including natural
balancing based on phase-shifted-carrier PWM, focusing
on motor drives [27]–[30]. Alstom Power and Grid, presently a part of General Electric, brought medium-voltage
motor drives using four-level FLC inverters to the market.
On the other hand, the five-level FLC inverter needs three
flying capacitors per phase leg, and their voltage ratings are
different from each other. Moreover, the five-level inverter
is much more complicated in control than the four-level
inverter.
Recently, attention has been paid to research on fourlevel and five-level converters based on combinations of
three-level FLC phase legs with three-level NPC, ANPC, or
NPP phase legs. A five-level ANPC inverter was introduced
in 2005 [31], each leg of which is based on a combination of
the three-level ANPC leg and the three-level FLC leg.
Fig. 5(a) shows the per-leg circuit configuration of the
four-level “nested” NPC inverter proposed in 2014 [32]. It is
based on a combination of the inner three-level NPC phase
leg with the outer three-level FLC phase leg. Fig. 5(b) shows
the per-leg circuit configuration of the five-level “nested”
NPP inverter introduced in 2016 [33]. It can be considered
as a combination of the inner three-level FLC phase leg with
the outer three-level NPP phase leg. Much effort has been
made toward capacitor-voltage balancing and switching-frequency reductions with relation to PWM methods.
V. A FA M I LY OF MODU L A R
MU LT IL E V EL C A SC A DE CON V ERT ER S
In 1971, McMurry patented a basic idea of multiple cascaded bridge cells [34]. In 1981, Alesina and Venturini published an IEEE Transactions paper describing a generalized
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 5. Per-leg circuit configurations of four-level and five-level
nested inverters. (a) The four-level nested NPC inverter [32].
(b) The five-level nested NPP inverter [33].
concept of multiple cascaded bridge or chopper cells [35].
However, it was impossible to verify their idea and concept
in the 1970s and 1980s. The remarkable development of
power electronics over the last three decades has made it
possible to put the multilevel converters on the market.
A. Circuit Configurations of Six MMCC Family
Members
Figs. 6–8 depict six converter circuit configurations
belonging to the family of modular multilevel cascade converters. The common concepts hidden in the family members are based on “modular” structure, “multilevel” voltage,
and “cascade” connection. These concepts allow power
electronics engineers to use the term “modular multilevel
cascade converter (MMCC)” as a family name. However,
the family name alone cannot identify the individual family members. Therefore, a given/first name should be introduced to each family member as if to identify each converter
configuration.
Fig. 6 shows the following three converter circuit configurations; the SSBC converter, the DSBC converter, and
the TSBC converter. The reason for naming is that the three
converters are based on one (single), two (double), and
three (triple) set(s) of three star-connected clusters, respectively, and that each cluster consists of multiple “bridge
cells” connected in cascade. This paper refers to a string of
the multiple bridge cells as a “cluster,” to distinguish it from
existing terms “arm” and “leg” used for traditional two-level
converters.
Fig. 6(a) has no current path or branch connected
between the cluster midpoint ​M​and the supply neutral
point O
​ ​. Hence, no current would flow between points ​M​
and O
​ ​even if any voltage ​v​MO​ appeared between points ​M​
and O
​ ​. An appropriate adjustment of ​v​MO​ allows the SSBC
converter to achieve cluster-voltage balancing [40]–[42].
Note that the intentionally injected voltage ​v​​MO​​does not
appear in the cluster line-to-line voltages.
Fig. 6. Three circuit configurations of modular multilevel xSBC
converters, where ​x = S​, ​D​, and ​T​. Each of the five white boxes is the
same as the SSBC surrounded by four straight dashed lines in the
left. (a) The SSBC (single-star bridge-cell) converter. (b) The DSBC
(double-star bridge-cell) converter. (c) The TSBC (triple-star bridgecell) converter.
Fig. 6(b) has a current path connected between two mid​ ​. The voltage difference between v​ ​JO​ and ​v​KO​​
points ​J​and K
is given by
​​v​JK​​  = ​
vJO
​ ​​ − ​v​KO​​  = ​
vac
​ ​​ .​
(1)
Therefore, appropriate adjustments of v​
​​ JO​​​ and ​​v​KO​​​ allow the
DSBC converter to achieve bidirectional power conversion
between the three-phase supply voltage ​​v​S​​​ and the singlephase ac voltage source ​​v​ac​​​.
Fig. 7 shows the following two converter configurations;
the SDBC converter and the DDBC converter. The reason
for naming is that the two converters are based on one
(single) and two (double) set(s) of three delta-connected
clusters, respectively, and that each cluster consists of
multiple “bridge cells” connected in cascade.
Fig. 7. Two circuit configurations of modular multilevel xDBC
converter, where ​x = S​and ​D​. Each of the eight white boxes is the
same as the cluster surrounded by four straight dashed lines in the
left. (a) The SDBC converter. (b) The DDBC converter.
Proceedings of the IEEE 5
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
the bridge cells become always positive. As a result, this
constraint makes it possible to replace all the bridge cells in
Fig. 7(b) with all the chopper cells in Fig. 8.
C. Comparisons Among the Six MMCC Family
Members
Fig. 8. Circuit configuration of the DSCC converter.
Fig. 8 shows the circuit configuration of the DSCC converter. The naming is based on two (double) sets of three
star-connected clusters, each of which consists of multiple
“chopper cells” connected in cascade. The DSCC converter
consists of two identical SSCC converters. However, one
SSCC converter is opposite in cluster positive voltage to the
other, as shown in Fig. 8.
B. Topological Discussion on the DSBC and DSCC
Converters
The DSBC converter can connect a single-phase ac voltage source ​​v​ac​​​between two midpoints J​ ​and ​K​, as shown in
Fig. 7(b). On the other hand, the DSCC converter can connect a dc voltage source ​​Vdc
​ ​​​between two midpoints ​P​and ​N​,
as shown in Fig. 8. The dc voltage source is given by
​​V​dc​​  = ​
vPO
​ ​​ − ​v​NO​​ .​
(2)
The dc voltage in (2) can be considered as a special case of
the ac voltage source ​​v​ac​​​in (1). Consider the following con​​ dc
​ ​​​:
straint between ​​V​S​​​ and V
__
__
​Vdc
​ ​​  ≥ 2 ​√ 2 ​ ​ V​S​​ / ​√ 3 ​​.
(3)
where ​​VS​ ​​​is the three-phase supply line-to-line root mean
square (rms) voltage. Whenever the above constraint is
effective in Fig. 7(b), the arm-side or ac-side voltages of all
Tables 1 and 2 summarize comparisons among the six
family members. The “IGBT-count ratio” in the third row
signifies the a count ratio of the IGBTs used in each member with respect to those in the SSBC under the following
assumptions:
• the six members have the same power and voltage ratings, using the same blocking-voltage IGBTs;
• as for the DSBC, TSBC, and DDBC converters, their
ac output voltage is the same in rms voltage as the
three-phase supply voltage;
• as for the DSCC converter, the dc__voltage
__ ​​V​dc​​​ meets
the following equation: ​​V​dc​​  = 2 ​√ 2 ​ ​ V​S​​ / ​√ 3 ​​.
Note that the IGBTs have different current ratings
because the count of the IGBTs differs among the six
members. The “applicability” in the last row includes
technical aspects as well as the potential market size for
each member.
D. Circulating Current
The “circulating current” defined in [36]–[38] plays
an important role in achieving voltage balancing of all the
bridge-cell or chopper-cell capacitors. Note that the SSBC
has no circulating current flowing inside it although it
can inject a common-mode zero-sequence voltage instead.
From a practical point of view, therefore, the SSBC has been
used as a STATCOM for positive-sequence reactive-current
control and as a battery-energy storage system (BESS) for
positive-sequence active-current control at the lowest cost
among the six members. The reason is that the SSBC has
a minimum cell count among the six family members, as
shown in Tables 1 and 2.
The SSBC can use the common-mode zero-sequence
voltage ​vMO
​ ​ for achieving capacitor-voltage balancing of all
the floating bridge cells in the STATCOM [39]–[42], and
for achieving state-of-charge (SOC) balancing control, faulttolerant control, and active-power control of the individual
bridge cells in the BESS [43]–[46].
Table 1 Comparisons Among the Family Members of Modular Multilevel Cascade Converters: Part I
6 Proceedings of the IEEE
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Table 2 Comparisons Among the Family Members of Modular Multilevel Cascade Converters: Part II
The SDBC allows an ac current to circulate among
three delta-connected clusters [47]. This circulating current plays an essential role in exchanging active power
among the three clusters although the circulating current is
accompanied by a slight increase in conduction and switching losses. The SDBC is more suitable for a STATCOM for
negative-sequence, as well as positive-sequence, reactivecurrent control [48], and a BESS for negative-sequence
reactive-current control as well as positive-sequence activecurrent control.
Both DSCC and DSBC have two degrees of freedom in
the circulating currents [14]. The TSBC has four degrees
of freedom whereas the DDBC has one degree of freedom.
Although both TSBC and DDBC can achieve three-phase
ac-to-ac direct power conversion, the TSBC is superior to
the DDBC in capacitor-voltage-balancing performance. The
reason is because the TSBC is more flexible than the DDBC
in terms of circulating-current control.
• the two single-phase transformers can be reduced significantly in volume and weight because they are operating at the ac-link frequency of 500 Hz;
• galvanic isolation, as well as voltage matching, among
the three-phase supply and the two motors can be
achieved by the two single-phase 500-Hz transformers;
• each motor-side DSBC converter can drive an ac
motor loaded with any speed-to-torque profile, including a constant rated-torque profile, in the whole range
of motor frequencies from 0 to 50 Hz;
• the two motors can run independently.
E. Applications of SSBC and DSBC Converters to
Motor Drives at Present and in the Near Future
Fig. 9 shows the well-known multilevel motor drive based
on an SSBC converter, which combines a multiwinding phaseshifted line-frequency transformer with multiple three-phase
six-pulse diode rectifiers [5]. Some companies in the world
have already established a good business market of mediumvoltage motor drives for fan, blower, and pump applications.
Each two-level phase leg shown in Fig. 9(b) can be replaced
with a three-level NPC phase leg shown in Fig. 1(a).
Fig. 10 shows a new motor drive system based on multiple DSBC converters [49]. The common line-side DSBC
plays an important role in achieving direct power conversion from a three-phase line-frequency, say 50 Hz, to a single-phase medium frequency, say 500 Hz. Multiple motorside DSBC converters are responsible for achieving direct
power conversion from the single-phase medium-frequency
to three-phase motor frequencies ranging, for example,
from 0 to 50 Hz. The system shown in Fig. 10 has the following advantages:
• the three DSBC converters have bridge-cell capacitors
with significantly reduced volume and weight because
they are operating at the ac-link frequency of 500 Hz;
Fig. 9. Medium-voltage multilevel motor drive system based on a
three-phase seven-level SSBC converter with three bridge cells per
phase [5]. (a) Power circuit. (b) Power cell.
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
A. Circuit Configuration
Fig. 10. Multiple-motor drive system based on ac-link DSBC
converters [49].
These advantages will bring the multiple-motor-drive
system to the market in the near future. It is possible to
replace the DSBC converters and the single-phase transformers with TSBC converters and three-phase transformers.
V I. A D OW NSC A L ED B AC K-T O -B AC K
(BT B) S YST E M USI NG T WO DSCC
CON V ERT ER S
This section presents a three-phase BTB system without
dc-link capacitor between the two identical 17-level DSCC
converters [50]. Each DSCC converter consists of 16 chopper cells per phase leg. The so-called “phase-shifted-carrier
PWM” is applied to the two DSCC converters that are
the same in circuit and control. Experimental waveforms
obtained from the BTB system are compared to simulated
waveforms obtained from the software package, “PSCAD/
EMTDC” under the same operating conditions, circuit
parameters, and control gains. Both waveforms agree well
with each other not only in steady states but also in transient states. This means that both experiment and simulation are reliable enough to look into more practical systems
and fault-ride-through (FRT) performance [51].
Fig. 11 shows the overview of the three-phase 200-V,
10-kW, 50-Hz BTB system designed, built, and tested in the
author’s laboratory. Note that the two noncoupled inductors per leg in Fig. 8 are replaced with a single center-tapped
inductor ​LZ​ ​ per leg in DSCC-A and DSCC-B. This replacement brings the two noncoupled inductors to significant
reductions in volume and weight [37]. The ac terminals of
each DSCC converters are connected to the three-phase
200-V ac mains through a per-phase ac-link inductor ​​Lac
​ ​​,
a starting circuit, and a line-frequency transformer for galvanic isolation. Each of the two line-frequency transformers
is rated at 200 V, 15 kVA, and 50 Hz. The positive directions
of ​​i​dc​​and ​p​ are defined as the direction from DSCC-A to
DSCC-B (left to right). Fig. 12 presents the photograph of
the 400-V​dc
​ ​, 10-kW BTB system, including the digital controller and data acquisition systems. This BTB system was
used in the following experiments.
Table 3 summarizes the circuit parameters of Fig. 11,
which were used in both experiment and simulation. The
dc reference voltage of each dc floating capacitor is set to​
v​*C​=​ 50 V, so that the dc-link voltage reference should be
set to ​v​*dc​=​ 400 V. Each triangular-carrier frequency is set
at ​f​C​=​ 450 Hz, and its dead or blanking time is 8 ​μ​s. Note
that 16 triangular-carrier signals are phase-shifted by 22.5°
(= 360°/16) to each other. Therefore, each DSCC converter
produces a 17-level waveform (line-to-neutral) with a voltage step as low as 25 V at the ac terminals.
The unit capacitance constant of the dc capacitors in
Table 3, H
​ ​C​is defined by
3nC ​V​  2 ​​
C
​​H​C​​  = ​ ______
​ .​
2P
(4)
The energy stored in all the dc capacitors is divided by
the rated power of the converter [52]. The SI unit of ​H​C​​ is
[J/W] or [s]. The unit capacitance constant is useful and
Fig. 11. Overview of the three-phase 200-V, 10-kW, 50-Hz downscaled BTB system with no dc-link capacitor between DSCC-A and DSCC-B [50].
8 Proceedings of the IEEE
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 12. Photograph of the experimental BTB system of Fig. 11.
effective in designing dc capacitors and in comparing dc
capacitors in one BTB system to another one with different voltage and current ratings. The reason is that the unit
capacitance constant can be considered as a kind of per-unit
value although per-unit values have no physical unit.
B. Operating Performance Under Transient States
Figs. 13 and 14 show the experimental and simulated
waveforms in DSCC-A, where the active-power reference​
p​​*​ was changed from 10 to −10 kW with a ramp function
in 20 ms. Note that ​q​*A​ and ​q​*B​ were set to zero. This means
that DSCC-A changes its operation from the rated rectification to the rated inversion whereas DSCC-B does it from the
rated inversion to the rated rectification. Such an extremely
fast response makes a significant contribution to enhancing
transient system stability and frequency-regulation capabil- Fig. 13. Experimental waveforms to a ramp change in ​p​*​from 10-kW
ity in contingency situations such as emergency disconnec- (rated) rectification to 10-kW inversion where ​q​A* ​ = q​ ​B* ​ = 0​.
tions of large-capacity synchronous generators in thermal
power plants from either power system. However, such a
No overcurrent occurred in the supply currents i​​S​​, the
fast response may not be required under normal operating
arm
currents ​i​P​and i​​N​, the circulating current ​iZ​ ​, and the dcconditions.
link current ​idc
​ ​. The dc-link current was changing from 25 A
(​=​ 10 kW/400 V) to −25 A. Moreover, the mean dc-capacTable 3 Circuit Parameters of Fig. 11
itor voltages and the mean dc-link voltage were well regulated to their references even during the transient period.
The experimental and simulated waveforms agree well with
each other even under such a transient-state condition.
Fig. 15 shows the experimental and simulated waveforms to a small step change in ​p​*​ from 8 to 10 kW, where
​q​*A​ = ​q​*B​ = 0​. The experimental waveform in Fig. 15(a)
is almost the same as the simulated waveform in Fig. 15(b)
except for a few small spikes superimposed on the experimental waveform. These spikes were just unintentional electrical noises that occurred on the PC-based data acquisition
system. The time constant obtained from the experimental
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 15. Experimental and simulated waveforms to a small step
*
change in ​​p​​  ​​from 8 to 10 kW (a) Experiment. (b) Simulation.
inductor that is more bulky but less expensive than a magneticcore inductor. This system is the world’s first long-distance
HVDC system based on DSCC converters. It was reported
that this system was able to successfully ride through a twophase voltage sag occurring upstream of Potrero substation on
March 18, 2016. At that time, the DSCC converter at the side
of Potrero substation was operating with inversion mode.
Table 5 summarizes the ratings and specifications of the
DSCC-based BTB system rated at 750 MW [54]. This is due
to be installed at the Tres Amigas superstation on the border
of the western interconnection, the eastern interconnection,
and ERCOT interconnection in the United States. One power
module consists of eight chopper cells, and each arm consists
of 47 power modules. The final installation capacity will reach
5 GW, including three sets of 750-MW BTB systems based
on DSCC converters, and three sets of 920-MW BTB systems
based on traditional line-commutated thyristor converters.
V III. MODUL AR MULTILEVEL DSCC AND
TSBC CONVERTERS FOR MOTOR DRIVES
Fig. 14. Simulated waveforms to a ramp change in ​p​*​from 10-kW
(rated) rectification to 10-kW inversion where ​q​A* ​ = ​q​B* ​ = 0​.
and simulated waveforms in Fig. 15 is as short as about
0.9 ms, which is almost the same as the theoretical value
of 0.94 ms [50].
Historically, the following two main streams exist in basic
research on both DSCC and TSBC converters: One has
come from three-phase two-level voltage-source inverters
and matrix converters [9], [55]–[57]. The other has come
Table 4 The 400-MW HVDC System in Trans Bay Cable Project [53]
V II. PR AC T IC A L A PPL IC AT IONS OF
DSCC CON V ERT ER S T O H V D C A N D BT B
S YST E MS
Several BTB and long-distance HVDC systems based on
DSCC converters are operating in the world. In addition,
there are some ongoing BTB and HVDC projects in Europe,
the United States, China, Japan, and other countries.
Table 4 summarizes the ratings and specifications of the
long-distance HVDC system referred to as the Trans Bay Cable
project, CA, USA [53]. Each DSCC converter has six inductors
in total or a single inductor per arm. Each one is an air-core
10 Proceedings of the IEEE
Table 5 The 750-MW BTB Unit in Tres Amigas Superstation [54]
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 16. Possible front-end power-circuit configurations for a DSCC-
filter combining a three-level NPC converter with a single tuned passive filter at the front end, to meet harmonic
guidelines [73]. The required power ratings of the passive
and active filters are 25% and 6%, respectively, of that of the
diode rectifier [23].
Fig. 16(b) is the case when a three-phase 12-pulse diode
rectifier sits at the front end. A three-phase 12-pulse transformer can be employed for voltage matching and galvanic
isolation between the supply and the motor. Another shunt
hybrid active filter is connected to mitigate the most dominant 11th- and 13th-harmonic currents, where the passive
and active filters require the power ratings of 8% and 0.8%,
respectively, with respect to the power rating of the 12-pulse
diode rectifier [74].
Fig. 16(c) uses an 18-pulse diode rectifier at the front
end. This rectifier would meet harmonic regulations without any harmonic filter, but at the expense of using a complicated phase-shifted multiwinding transformer. The three
power circuit configurations using the diode rectifiers are
suitable for large-capacity fans, blowers, and pumps in
terms of reliability and availability because neither fastspeed control nor regenerative braking is required for these
applications.
Fig. 16(d) shows a back-to-back (BTB) system using two
DSCC converters, which provides the function of regenerative braking. Three-phase sinusoidal currents can be drawn
from the supply due to three-phase multilevel voltage waveforms produced by the front-end DSCC rectifier. This may
result in eliminating both harmonic filter and transformer
from the system.
based motor drive: (a) six-pulse diode rectifier equipped with a
shunt hybrid active filter; (b) 12-pulse diode rectifier equipped with
a shunt hybrid active filter; (c) 18-pulse diode rectifier at the front
end; and (d) DSCC rectifier at the front end [71].
B. Experimental Motor Drives Using a DSCC
Inverter and a TSBC Converter
from the SSBC converter shown in Fig. 6(a) [14], [17],
[36]–[38], [50], [58]–[70]. The former has no inductor connected in series with each arm or cluster, whereas the latter
has it. The existence of the inductor allows a circulating current to flow through the corresponding arm or cluster. This
makes it possible to adjust the circulating current actively
and appropriately for providing voltage-balancing capability
of all the chopper-cell or bridge-cell capacitors [36]–[38].
A. DSCC-Based Motor Drive Systems
Fig. 16 shows four possible power circuit configurations
at the front end of a motor drive using a DSCC converter
[71]. Note that no dc-link capacitor is required between
either diode or DSCC rectifier and the DSCC inverter [72].
Fig. 16(a) uses a three-phase six-pulse diode rectifier at
the front end. This configuration is characterized by eliminating a line-frequency transformer from the motor drive
system. However, it requires installing a shunt hybrid active
Fig. 17 illustrates the circuit configuration of a threephase DSCC inverter with eight chopper cells per arm,
which is used for the following experiments. Two arms
in each phase are connected in series via a center-tapped
inductor. The center tap of each inductor is directly connected to one of the three motor terminals.
Fig. 18 depicts the 400-V, 15-kW downscaled motor drive
system using the DSCC inverter. The mean dc-capacitor-voltage reference of each chopper cell, ​V​*C​was set to 70 V.
Fig. 19 illustrates the circuit configuration of a threephase TSBC converter with four bridge cells per cluster,
which is used for the following experiments. The TSBC
converter consists of three star-connected subconverters or SSBC converters, each of which consists of three
clusters. Each cluster is connected directly to one of
the three terminals in a three-phase three-leg inductor.
The use of the three three-phase three-leg inductors for
the TSBC converter makes it possible to reduce their
size and weight dramatically, compared with using nine
noncoupled inductors [67]. The neutral point of each
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 17. Circuit configuration of the three-phase 17-level DSCC
inverter used for experiments.
Fig. 19. Circuit configuration of the three-phase nine-level TSBC
converter used for experiments.
subconverter is connected to one of the three motor
terminals.
Fig. 20 depicts the 400-V, 15-kW downscaled motor drive
system using the TSBC converter. The mean dc-capacitorvoltage reference of each bridge cell ​V​*C​was set to 200 V.
The following two three-phase induction motors with
the same power rating were used for experiments: One is
rated at 50 Hz, 380 V, 15 kW, four poles, and 1460 r/min
while the other is at 38 Hz, 320 V, 15 kW, six poles, and 750
r/min. The former is a general-purpose motor, and the latter
is a specially designed low-speed, high-torque motor.
Fig. 21 shows the photograph of two sets of induction
motors and generators used in the following experiments.
The two motors are the same in power rating but are
Fig. 18. The 400-V 15-kW downscaled DSCC inverter system used
for experiments [71].
12 Proceedings of the IEEE
significantly different in volume and weight because their
rated frequencies are different.
Table 6 summarizes the circuit parameters of the DSCC
inverter. Table 7 summarizes circuit parameters of the
TSBC converter.
C. Comparisons in Startup Performance When the
50-Hz Induction Motor Was Driven
Figs. 22 and 23 show the experimental startup performance of the 50-Hz induction motor loaded at 40% torque,
which were driven by the DSCC inverter and the TSBC
converter, respectively. The motor-speed reference ​N​*rm​​ was
Fig. 20. The 400-V 15-kW downscaled TSBC-converter system used
for experiments [71].
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Table 7 Circuit Parameters of Fig. 19 (TSBC Converter)
Fig. 21. Photograph of the 50-Hz, 380-V, four-pole, 15-kW induction
motor (back-left side), the 38-Hz, 320-V, six-pole, 15-kW induction
motor (front-left side), and mechanically coupled induction
generators (right side). Note that mechanical-coupling covers for
safety were removed to take this photograph.
increased up from 0 to 1500 r/min with a ramp rate of 90 r/
min/s for both experiments.
In Fig. 22, the ac-voltage-mitigating control discussed in
[61] was switched over, according to the motor frequency
as follows.
• ​t = ​
t0​ ​​​ to ​​t​1​​​(0 to 20 Hz): It was active where a squarewave circulating current and a square-wave commonmode voltage of 200 V and 100 Hz were superimposed.
• ​t ≥ ​
t​1​​​(20 Hz): It was inactive completely.
Note that the mitigating control gradually deactivates
from 10 to 20 Hz, where both circulating current and common-mode voltage were reduced linearly. The peak value of
the arm current ​iPa
​ ​took the maximum of 39 A at 1 Hz and 18
A at 50 Hz. The maximum peak-to-peak voltage fluctuation
of v​ C1a
​ ​was 19 V at 15 Hz.
In Fig. 23, two kinds of ac-voltage-mitigating controls
were switched over as follows.
• ​t ≥ ​
t​3​​​ (40 Hz): The mitigating control in [66] was
activated completely.
The peak value of the cluster current i​ ​​ua​ ​​in a low-frequency range was 10 A, and the maximum value around
50 Hz was 41 A. The voltage fluctuation of ​​v​  u1
Ca ​​​  was 67 V at
50 Hz. These experimental results find out clear differences
in peak-to-peak voltage fluctuation and arm or cluster current between the DSCC inverter and the TSBC converter.
Fig. 24 shows the voltage and current waveforms of the
DSCC inverter where the motor was loaded at 40% torque,
and running at 30 r/min. Each of the positive and negative
arm currents in a​ ​phase ​i​​Pa​​and i​​​Na​​, includes the following three-frequency components: 100-Hz square-wave
circulating current, 1-Hz motor current, and small switching-ripple components. The rms value of the positive arm
current ​​i​Pa​ was 15 A in rms (47% on a 32-A base). The
capacitor-voltage fluctuation ​v​C1a​ was 11 V in peak-to-peak
(16% on a 70-V base).
• ​t = ​
t​0​​​ to t​ = ​
t​1​​​ (0 to 14 Hz): The control proposed
in [65] was active.
• ​t = ​
t​1​​​ to ​t = ​
t​2​​​ (14 to 35 Hz): Neither control was
active.
• ​t = ​
t2​ ​​​ to ​t = ​
t3​ ​​​ (35–40 Hz): The other control
in [66] was being gradually activated where both
circulating current and dc common-mode voltage
were increasing linearly.
Table 6 Circuit Parameters of Fig. 17 (DSCC Inverter)
Fig. 22. Experimental startup performance of the DSCC-driven 50Hz induction motor loaded at 40% torque.
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Fig. 23. Experimental startup performance of the TSBC-driven
50-Hz induction motor loaded at 40% torque.
Fig. 25. Experimental steady-state performance of the DSCC-
D. Operation of the DSCC-Driven 50-Hz Motor and
the TSBC-Driven 38-Hz Motor at the Rated
Frequency and Torque
Fig. 25 shows the steady-state waveforms of the DSCCdriven 50-Hz induction motor at the rated motor frequency
and torque. Two kinds of voltage ripples were included in
the dc-link voltage ​vdc
​ ​​:
• one came from the 12-pulse diode rectifier: it was
absorbed by the capacitor of each chopper cell;
• the other came from the DSCC inverter: it had no effect
on the motor-drive performance because its voltage
step were as small as half the single-capacitor voltage.
Installing a simple filter on the dc link would eliminate
the voltage ripples from the DSCC inverter [72]. Each of
three-phase line-to-line voltages, ​vMab
​ ​​, ​​vMbc
​ ​, and ​vMca
​ ​, has a
driven 50-Hz, four-pole induction motor loaded at the rated torque
​ 1500 r/min.
at ​​N​  r*m ​ =​
27-level voltage waveform. The multilevel line-to-line voltages resulted in producing three-phase sinusoidal motor
currents ​i​Ma
​ ​​, i​​​Mb​​, and ​i​​Mc​​. The arm current waveforms ​i​Pa
​ ​​
and ​​i​Na​ included dc, 50-Hz, and switching-ripple components, where the switching-ripple component was negligibly small. Capacitor voltages ​​vC1a
​ ​​and ​v​​C9a​​were balanced
perfectly with its peak-to-peak value of 6.3 V (9.6%). The
experimental results shown in Fig. 25 suggest that it would
be possible to reduce a unit capacitance constant of the
DSCC inverter from 52 to 24 ms if a peak-to-peak capacitor
voltage fluctuation of 25% were acceptable [71].
Fig. 26 shows the steady-state waveforms of the TSBCdriven 38-Hz induction motor at the rated motor frequency
and torque. Each of three-phase line-to-line voltages at the
wu
supply side, ​v​uv
​ ​vw
a​ ​​, ​v
a​ ​, and ​v​a​ ​, had a nine-level voltage waveu v
form. This made ​i​S​​, ​​i​S​, and ​i​wS​​sinusoidal at unity power factor. Moreover, three-phase line-to-line voltages at the motor
side ​v​Mab​​, v​​ ​Mbc​, and ​vMca
​ ​and currents ​i​Ma​​, ​​i​Mb​, and ​iMc
​ ​​ were
controlled to produce the rated torque with a negligible
amount of torque ripple. Cluster currents ​i​ua​​, ​i​ ​ub​, and i​​uc​​ were
controlled to sinusoidal waveforms with small current ripples. The peak-to-peak capacitor voltage fluctuation in ​v​u1
Ca​​,​​
w1
v​v1
,
​
and
v
​
​
​
was
only
50
V
(25%)
[71].
Ca
Ca
E. Discussion on the Two Motor Drives
Fig. 24. Experimental steady-state performance of the DSCCdriven 50-Hz induction motor loaded at 40% torque and ​​f​M​​ =​1 Hz.
14 Proceedings of the IEEE
The following simple question may rise, “Which is suitable
for motor drives, the DSCC inverter or the TSBC converter?”
The answer depends strongly on the torque-to-speed profile
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Table 8 Motor Drive Systems From Benshaw [75]
Both manufacturers use three-phase 12-pulse to
36-pulse diode rectifiers at the front end. Since the diode
rectifiers have no capability of regenerative braking, practical applications of the DSCC-based motor drives to industry include fans, blowers, and pumps for energy savings.
The adoption of the DSCC-based motor drives shown in
Fig. 16(a) and (d) will make it possible to eliminate the
12-pulse to 36-pulse multiwinding line-frequency phaseshifted transformers from the medium-voltage motor drive
systems in the near future.
X. FUTURE SCENARIOS AND CONCLUSION
Fig. 26. Experimental steady-state performance of the TSBC-driven
*
​=​
38-Hz, six-pole induction motor loaded at the rated torque at ​N​rm
750 r/min.
of a load driven by the motor. The DSCC inverter brings
capacitor-voltage fluctuations to all the chopper cells in a lowfrequency range including the startup, whereas the TSBC
converter brings them to all the bridge cells as the motor frequency gets close, and equal to, the supply frequency, even
when any appropriate mitigating control is applied.
Hence, the exact answer to the above question can
be summarized as follows: The DSCC inverter is suitable
for a high-speed motor drive of a load with a quadratictorque-to-speed profile such as fans, blowers, pumps,
and centrifugal compressors. The TSBC converter is
suitable for a low-speed motor drive of a load with a constant high-torque profile such as mills, kilns, conveyors,
and extruders.
I X . PR AC T IC A L A PPL IC AT IONS OF
DSCC I N V ERT ER S T O MO T OR DR I V E S
No company or manufacturer has commercialized mediumvoltage motor drives using TSBC converters due to some
reasons including cost. However, traditional line-commutated cycloconverters will be replaced with the TSBC converters in the near future.
Benshaw, presently taken over by Regal Beloit
Corporation, and Siemens AG have put medium-voltage
motor drives using DSCC inverters on the market. Table 8
summarizes electric specifications of the product from
Benshaw [75], and Table 9 from Siemens AG [76].
This paper has provided an overview and discussion on classic and modern multilevel converters for grid-tied applications and motor drives, paying attention to their fundamental circuits and systems. The classic and modern multilevel
converters include NPC, NPP, and FLC inverters, and a
family of modular multilevel cascade converters. Some have
already established a good business market, some have been
on a research and development stage, and others have been
on an academic research stage.
The author would summarize a future scenario on the
multilevel converters as follows.
• For medium-voltage multilevel converters, a research
challenge would be to enhance the cost-effectiveness
of four-level and five-level converters based on combinations of three-level FLC converters with three-level
NPC, ANPC, or NPP converters.
• For high-voltage multilevel converters, a research
challenge would be to reduce both volume and weight
on passive components including transformers,
inductors, and capacitors, in particular, bridge-cell or
chopper-cell capacitors indispensable to the family of
modular multilevel cascade converters.
Table 9 Motor Drive Systems From Siemens AG [76]
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
Another future scenario would be to make good use of
SiC-MOSFET/SBD modules for multilevel converters. The use of the modules results in improving both
“power efficiency” and “energy efficiency.” This makes
the multilevel converters smaller in size and lighter in
weight. Some scientists and engineers of power electronics, including the author of this paper, have been dreaming “a multilevel converter became higher in efficiency
than a line-frequency (50 or 60 Hz) transformer when
the converter and the transformer had the same voltage
and current ratings.” Sophisticated design and fabrication of a multilevel converter using the next-generation
SiC-MOSFET/SBD modules will make the dream come
true in the near future.
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[15]
[16]
[17]
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[24]
Fortunately or unfortunately, no versatile multilevel
converter exists from a practical point of view. This fact
would encourage scientists and engineers of power electronics to do further research on multilevel converters in a
broad sense.

Acknowledgement
The author would like to thank a former Ph.D. candidate,
Dr. W. Kawamura who is currently working for Toshiba
Mitsubishi Electric Industry Corporation (TMEIC), another
former Ph.D. candidate, Dr. N. M. L. Tan who is currently
Associate Professor at Universiti Tenaga Nasional, Malaysia,
and two Ph.D. candidates, Y. Okazaki and P. Sochor, for
their assistance in completing this paper.
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Aka gi: Multilevel Conver ter s: Fundamental Circuit s and Systems
ABOUT THE AUTHORS
Hirofumi Akagi (Fellow, IEEE) was born in Okayama, Japan, in 1951. He received the Ph.D. degree
in electrical engineering from Tokyo Institute of
Technology, Tokyo, Japan, in 1979.
Since 2000, he has been Professor in the
Department of Electrical and Electronic Engineering at Tokyo Institute of Technology. Before
that, he was with Okayama University, Okayama,
Japan and the Nagaoka University of Technology,
Nagaoka, Japan. His research interests include power conversion systems
18 Proceedings of the IEEE
and its applications to industry, transportation, and utility. He has
authored and coauthored some 130 IEEE Transactions papers and three
invited papers in the Proceedings of the IEEE.
Dr. Akagi has received six IEEE Transactions Prize Paper Awards and
14 IEEE IAS Committee Prize Paper Awards. He is the recipient of the 2001
IEEE PELS William E. Newell Power Electronics Award, the 2004 IEEE IAS
Outstanding Achievement Award, the 2008 IEEE Richard H. Kaufmann
Award, and the 2012 IEEE PES Nari Hingorani Custom Power Award.
He served as the President of the IEEE Power Electronics Society for
2007Ð2008, and as the IEEE Division II Director for 2015Ð2016.