# A study on power flow and short circuit algorithms capable of analyzing the effect of load current on fault current using the bus impedance matrix

```2016 IEEE Electrical Power and Energy Conference (EPEC)
A Study on Power-Flow and Short-Circuit Algorithms
Capable of Analyzing the Effect of Load Current on
Fault Current Using the Bus Impedance Matrix
Insu Kim
Ronald G. Harley
Electrical Engineering
Alabama A & M University
Normal, AL, 35711, USA
[email protected]
Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA, USA
Professor Emeritus at the University of KwaZulu-Natal in
South Africa, [email protected]
Abstract—In short-circuit studies, load makes difficult to
determine fault current that flows in positive-, negative-, and
zero-sequence networks. Therefore, it is often ignored because the
magnitude of load current is much less than that of fault current
that flows from generators when a fault occurs. As distributed
generation (DG) resources such as photovoltaic systems, wind
farms, and non-linear generators based on power electronics have
being deployed into power system networks, load current that
flows from them may affect a magnitude of fault current. Thus,
the objective of this study is to develop a short-circuit algorithm
that analyzes the effect of load current on fault current. For this
purpose, using the bus impedance matrix and the iterative
current compensation method presented in [1], this study initially
develops a power-flow analysis algorithm that iterates to calculate
current to be injected and determines voltage. Then, the proposed
short-circuit algorithm uses as input data the results of powerflow calculation. To verify the algorithms developed in MATLAB,
a distribution system with a DG resource is presented in a case
study. Then, this study (a) calculates the power flow of the
distribution system, (b) generates a single line-to-ground fault,
and (c) changes the capacity of load, the capacity of a DG
resource, and the location of a fault. Finally, it examines the effect
of load and DG on a magnitude of fault current.
Index Terms—Power-flow algorithm, bus impedance matrix,
short-circuit current, sequence network, fault, and load current.
I. INTRODUCTION
Short-circuit studies, also known as fault analysis, are
necessary for planning and upgrading power systems
equipment. For example, a rating of equipment in power
systems should withstand the maximum short-circuit current
caused by electric faults. Therefore, many studies have
presented various methods for short-circuit studies [2-10].
However, these studies ignored load current because not only
its magnitude is significantly lower than the magnitude of fault
current but also it makes difficult to calculate fault current that
flows in positive-, negative-, and zero-sequence networks.
However, as high-capacity distributed generation (DG)
resources have being deployed into power system networks,
load current flowing from DG resources could affect fault
current. Therefore, various commercial power system analysis
software packages such as CYME provide the following two
methods in their short-circuit analysis module: (a) ignoring the
load currents and (b) including them. For this purpose, the
CYME software package (version of 7.2) only replaces the
prefault voltages calculated by the power-flow module with the
nominal voltage [11]. Therefore, to more accurately calculate
the short-circuit current affected by loads, this study presents a
novel method that (a) transforms an electric load to an
equivalent impedance, (b) adds it to the bus impedance matrix,
and (c) uses the prefault voltages changed by the power-flow
results. In addition, previous work did not examine the effect of
not only load with various capacities (i.e., from 0 PU to 0.9 PU)
but also a DG resource with various capacities (i.e., from 0.1
PU to 0.5 PU) on short-circuit current. Thus, this study (a)
presents a case study that generates a single line-to-ground
(SLG) fault while changing load capacities, DG capacities, and
fault locations and (b) examines the effect of electric load and
a DG resource on a magnitude of fault current.
This paper is organized as follows: Section 2 describes the
problem statement and Section 3 presents the short-circuit
theory that analyzes load current. Section 4 introduces a
distribution network as a case study. Section 5 calculates shortcircuit current of the distribution network using the proposed
method. Section 6 summarizes major conclusions of this paper.
II. PROBLEM STATEMENT
In short-circuit studies, the voltage of a bus that a fault
occurs is often assumed as unity for simplicity. That is, a
decrease or increase in the voltage of the bus caused by load
before a fault occurs is often ignored. Therefore, to calculate
more accurate fault current, a short-circuit study needs to take
load into account. Furthermore, since single- or three-phase DG
resources with various capacities have been deployed into
power grid networks, the effect of current that flows from DG
resources on fault current should not be ignored. Therefore, this
study will develops a short-circuit algorithm able to analyze
fault current affected by load and DG resources. For this
purpose, a method that transforms an electric load to an
equivalent impedance and adds it to the bus impedance matrix
is presented.
III. SHORT-CIRCUIT STUDY
A. Bus Impedance Matrix
A power grid network with n nodes in Fig. 1 can be shown
2016 IEEE Electrical Power and Energy Conference (EPEC)
by currents injected from n nodes and voltages induced at n
nodes relating to the reference:
(1)
V  Zbus I ,
where Zbus is referred to as the bus impedance matrix.
Fig. 1. A power grid network with n nodes.
To build the bus impedance matrix, this study used the four
well-known rules presented in [2, 12]. If the bus impedance
matrix with a size of n × n is available, the matrix can be used
for power-flow and short-circuit calculation.
B. Short-Circuit Current
The bus impedance matrix is used to calculate short-circuit
current. For example, if a SLG (single line-to-ground) fault
occurs on the phase a of line i, fault currents of zero-, positive, and negative-sequence networks are calculated by
Vf
I 0  I1  I 2 
,
(2)
Z0 (i, i )  Z1 (i, i )  Z 2 (i, i )  3Z f
where
I0, I1, and I2 = the zero-, positive-, and negative-sequence
currents of faulted bus or line i, respectively,
Vf = the voltage of the Thevenin equivalent voltage source in
the positive-sequence network before a fault,
Z0 (i, i ) , Z1 (i, i ) , , and, Z 2 (i, i ) = the zero-, positive-, and
negative-sequence (open-circuit driving-point) impedances of
faulted bus or line i in bus impedance matrices ,respectively
Zf = fault impedance.
Many short-circuit studies ignore current that flows to load
for simplicity. That is, Vf is usually assumed as 1.0∠0°, PU,
accurate short-circuit current ,this,study,calculates,Vf using the
power-flow method that uses the bus impedance matrix and
iterative current compensation method presented in [1]. In fact,
Vf often decreases than when compared to neglecting load.
C. Transformation of Load to Equivalent Impedance
If current flows from buses i to j through an inductive line
(e.g., when ignoring the capacitance of the line), the voltage at
node j drops by as much as impedance of the line multiplied by
current that flows from buses i to j. Since load current affects
fault current, this study transforms load to impedance by
2
*
Z j  V j / Sscheduled
,j ,
(3)
where
Zj = the equivalent impedance of load connected to bus j,
Vj = the voltage at bus j, calculated from the power-flow
algorithm that uses the bus impedance matrix and iterative
current compensation method presented in [1].
Then, the impedance is added to the bus impedance matrix.
Therefore, this study can calculate more accurate short-circuit
current because of not ignoring load current.
IV. CASE STUDY
In Fig. 2, this study presents a distribution system with a DG
source in order to verify the iterative bus impedance method
able to calculate not only power flow in the normal steady state
but also short-circuit current affected by load. The distribution
system includes a substation with a delta-wye connected
transformer with a capacity of 100 MVA at 115/12.47 kV,
distribution lines, a wye-wye connected distribution
transformer with a capacity of 100 kVA at 0.38 kV, a
synchronous generator with a capacity of 100 kVA, and a load
with 20 MW at 12.47 kV and a power factor of 1.0. This study
assumes that the system is fully balanced and transposed in
three phases. Therefore, this study performs per-phase analysis
using only the positive-sequence impedances of the generators
and transformers (because their zero- and negative-sequence
voltages and currents are zero) and the single-phase impedances
of the lines approximated by
(4)
Za  (2Z1  Z0 ) / 3 ,
where
Za = the approximate impedance of phase a [2, 13].
Then, this study initially calculates the power flow of the
system and generates a SLG (single line-to-ground) fault on the
high-voltage side of the distribution system, phase a of feeder
1, and on the low-voltage side, feeder 2. A fault impedance, Zf,
is assumed as 0.
Fig. 2. A distribution system with a synchronous generator at the end [14, 15].
V. SIMULATION RESULTS
Using the four rules in [2, 12], the proposed method builds
a bus impedance matrix of the distribution system in Fig. 2 and
calculates power flow until it achieves convergence. Then, it
applies the voltage of a bus to which a load is connected to
equation (3), calculates an equivalent impedance of the load,
and updates the bus impedance matrix. To examine the effect
of load on fault current, the proposed method decomposes the
distribution system into zero-, positive-, and negative-sequence
networks. For example, a load of 20 MW (or 0.2 PU at a power
factor of 1.0 and a voltage of 0.98276∠-4.711° PU) can be
converted to an impedance of 4.8291 + j0 by equation (3). The
voltage of 0.98276∠-4.711° PU is calculated by the algorithm
presented in [1].
This study examines the effect of not only load with various
capacities (i.e., from 0 PU to 0.9 PU) but also DG with various
capacities (i.e., from 0.1 PU to 0.5 PU) on the magnitude of
fault current when a SLG (single line-to-ground) fault occurs
either before or after a bus to which the load is connected.
TABLE I and TABLE II show the fault current that flows from
the faulted line to the ground if a SLG fault occurs on either
feeders 1 or 2. First, in all the cases, the higher load current
2016 IEEE Electrical Power and Energy Conference (EPEC)
flows, the lower fault current flows compared to the case that
the higher voltage drops buses experience because the lines are
usually inductive. In other words, the voltage in equation (2)
decreases, so a magnitude of fault current decreases. Thus, load
current should not be ignored because it affects magnitudes and
phase angles of fault current. Second, as a DG source with
higher capacity (e.g., 0.5 PU) is connected, the higher fault
current flows. It is because both the substation and the DG
source contribute to fault current at the same time, which is
comparable to [14]. Last, a SLG fault close to the substation
(e.g., a fault on feeder 1) seems to cause higher fault current
than that far from the substation (e.g., a fault on feeder 2). It is
because the capacity of the DG source is lower than that of the
substation. Fig. 3 and Fig. 4 show the trends in the magnitude
of fault currents. It indicates that as the capacity of a load
increases and the capacity of a DG source decreases, the
magnitude of fault currents decreases.
TABLE I. FAULT CURRENTS OF FEEDER 1 (SLG FAULT ON FEEDER 1)
DG
0 PU (No Load) 0.1 PU (10%) 0.5 PU (50%) 0.9 PU (90%)
0.1 PU 3.6030∠-84.52° 3.5989∠-84.61° 3.5793∠-84.98° 3.5509∠-85.36°
DG 0.3 PU 4.3805∠-84.62° 4.3751∠-84.91° 4.3416∠-86.08° 4.2836∠-87.30°
0.5 PU 4.9628∠-84.48° 4.9573∠-84.80° 4.9243∠-86.10° 4.8701∠-87.47°
TABLE II. FAULT CURRENTS OF FEEDER 2 (SLG FAULT ON FEEDER 2)
DG
0 PU (No Load) 0.1 PU (10%) 0.5 PU (50%) 0.9 PU (90%)
0.1 PU 1.6748∠-87.49° 1.6709∠-88.64° 1.6406∠-93.52° 1.5702∠-99.69°
DG 0.3 PU 3.5978∠-86.42° 3.5956∠-87.07° 3.5730∠-89.80° 3.5205∠-92.91°
0.5 PU 5.0185∠-86.38° 5.0178∠-86.83° 5.0040∠-88.67° 4.9686∠-90.68°
on fault current while changing load capacities, DG source
capacities, and fault locations. The results from the case study
show that the higher load current flows, the lower fault current
flows compared to the case that ignores load current. It is
because that the higher load current flows, the higher voltage
drops buses experience. Therefore, load current should not be
ignored because it affects magnitudes and phase angles of fault
current. Next, as a DG source with higher capacity (e.g., 0.5
PU) is connected, the higher fault current flows because both
the substation and the DG source contribute to fault current.
Last, a SLG fault close to the substation (e.g., a fault on feeder
1) seems to cause higher fault current than that far from the
substation (e.g., a fault on feeder 2).
This study calculated the short-circuit current of only a
simple single-phase distribution network, using the bus
impedance matrix. It should be extended for three-phase
distribution systems with sufficiently large feeders that may be
not balanced. In addition, it did not examine various fault types
(e.g., double line-to-line, double line-to-ground, and threephase faults), various load types (e.g., constant impedance and
current loads), and connections of three-phase transformers.
Implementing these topics in a future study should provide a
more accurate and efficient algorithm for power-flow and shortcircuit studies.
REFERENCES
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Fig. 3. Fault currents when a fault occurs on feeder 1.
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Fig. 4. Fault currents when a fault occurs on feeder 2.
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VI. CONCLUSION
The objective of this study is to develop a short-circuit
analysis algorithm able to examine the effect of load on fault
current. To verify the proposed algorithm, a case study that
generates a SLG (single line-to-ground) fault on a distribution
system is presented. Then, this study examines the effect of load
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