695d29ef7ab784ad0dfa448fb9bd8feeaaf8

advertisement
2 Reliability of Semiconductor Devices
Contents
2.1
i
What is Reliability
2- 1
2.1.1
Concept of reliability
2- 1
2.1.2
Indication of reliability
2- 1
2.2
Reliability Test
2- 5
2.2.1
Concept of reliability test
2- 5
2.2.2
Reliability evaluation method using TEG
2- 9
2.2.3
Reliability test method
2-10
2.2.4
Failure criterion
2-15
2.2.5
Accelerated life test
2-16
2.2.6
Reliability test by sampling
2-23
2.2.7
Screening
2-27
2
2.
Reliability of Semiconductor Devices
Reliability of Semiconductor Devices
2.1
2.1.1
What is Reliability
Concept of reliability2.1)
JIS Z 8115 “Glossary of Terms Used in Reliability” defines the term “reliability” (of a semiconductor device)
as the “property (of a semiconductor device) of being able to provide the required function during the specified
period under the given conditions”. To indicate a specific level of “reliability”, the “reliability” is used, and it
is defined as the “probability of provision of the required function (by a semiconductor device) during the
specified period under the given conditions”.
So “reliability” is a property that can be indicated by three independent parameters:
1. Use environment
2. Time
3. Function
However, considering the machines that use semiconductor devices, it can be said that the use environment of
semiconductor devices is limited. So “reliability” generally means the “stability of the function as the time
elapses” (in other words, “reliability” means “non-deterioration of the function”.). Note that the term “time”
includes the “number of times (frequency)”.
A large difference between “reliability” and “quality” is that “quality” problems occur in the early stages
(it is not necessary to consider the parameter of “time” for “quality”.).
2.1.2
Indication of reliability2.1)
a) Reliability function
The reliability function “R(t)” indicates the ratio of the conforming products that can function properly when
the time “t” elapses after starting use. The following formula expresses the reliability function:
(2.1)
Where, n: Total number of samples
c(t): Number of failures when time “t” elapses
b) Unreliability function (failure distribution function)
The unreliability function “F(t)” indicates the total number of failures (number of cumulative failures) that
are detected by elapse of the time “t” after starting use. The following formula expresses the unreliability
function:
(2.2)
R(t) and F(t) are monotone decrement/increment functions. Of course, the following equation is true.
(2.3)
Figure 2.1 shows the relation between R(t) and F(t).
T04007CE-2 2012.1 2-1
2
Reliability of Semiconductor Devices
1
R(t)
F(t)
0.5
t
Figure 2.1 Relation between R(t) and F(t)
c) Failure density function
The failure density function “f(t)” is used for indication of the failure occurrence rate in the unit time for
all the samples when the time “t” elapses after starting use. The following formula expresses the failure density
function.
(2.4)
R(t) and F(t) can be expressed using f(t) as follows:
(2.5)
(2.6)
d) Failure rate function (also referred to as hazard rate function)
The failure rate function “λ(t)” is used for indication of the possible failure occurrence rate in the next unit
time for the samples still operating properly when the time “t” elapses after starting use. The following
formula expresses the failure rate function:
(2.7)
R(t) can be expressed using λ (t) as follows:
(2.8)
The failure rate function is also referred to as the instantaneous failure rate, and is frequently used for
expression of the reliability of semiconductor devices.
Generally, the instantaneous failure rate described above can express the accurate failure rate from the
theoretical point of view. Practically, however, it is difficult to calculate the failure rate for a very short unit
time. So, in many cases, the average failure rate of 1,000 hours, 1 month, or 1 year is used preferably.
T04007CE-2 2012.1 2-2
2
Mean failure rate ≡
Reliability of Semiconductor Devices
Total number of failures detected in specified period
Total operation time in specified period
“%/103h” and “FIT
10-9/h” are used as the units for expressing the average failure rate.
e) Cumulative hazard function
The failure rate function “λ (t)” is accumulated to express the cumulative hazard function “H(t)” as follows:
(2.9)
The relation between R(t) and H(t) is shown in the following equation:
(2.10)
f) Mean time to failure (MTTF)
Like the failure rate, the time to failure is also used frequently. The time to failure is defined as the time required
for the semiconductor devices to cause a failure after starting use. The mean value of the time to failure is
referred to as the mean time to failure (MTTF). The following formula expresses the mean time to failure:
(2.11)
g) Semiconductor device failure distribution
The failure occurrence condition of an electronic part or an electronic device is generally illustrated as shown
in Figure 2.2. The curve shown in Figure 2.2 is referred to as the bath-tub curve because of its shape.
Failure rate λ (t)
General electronic device
or electronic part
Semiconductor device
Early failure
period
Random failure period
Assumed
Wear-out failure
period
Time t
Figure 2.2
Typical failure rate curves for electronic device or part and semiconductor device
T04007CE-2 2012.1 2-3
2
Reliability of Semiconductor Devices
Early failures are mainly caused by the problems of the manufacturing process, and this type of failure will
be gradually reduced as the time elapses. To ensure a stable supply of good products to the market, thorough
quality control and process control are needed. In addition, early failures should be thoroughly eliminated by
debugging, such as by burn-in or aging. We will deliver products that will not cause any early failures.
It can be said that random failures can lower the reliability of a product. The reliability depends on the design
quality. If derating is carried out or environmental stresses can be reduced, the random failure rate can be reduced.
Regarding semiconductor devices, the properties are stabilized during this period.
Regarding the wear-out failures, the failure rate will be increased as the product is worn out or becomes
fatigued. For semiconductor devices, occurrence of wear-out failures depends on the device type. Generally,
however, it is not yet clarified. If a wear-out failure occurs, recurrence preventive measures, such as 100%
replacement, will be taken. This type of measure, however, may cause early failures. So the measures should
be taken carefully.
T04007CE-2 2012.1 2-4
2
2.2
Reliability of Semiconductor Devices
Reliability Test
Concept of reliability test2.2)
2.2.1
a) What is a “reliability test”?
The ultimate purpose of the “reliability test” is to ensure that semiconductor devices manufactured by a
semiconductor manufacturer, assembled and adjusted by an assembly contractor, and finally delivered to
customers can perform for the intended period.
It is, therefore, important to determine the target reliability before starting the reliability test. The reliability
is defined as the “probability of provision of the required function (by a system, machine, or part) during the
intended period under the specified conditions”. So it is important to clarify
1) what device (system equipment or part) is to be subject to the reliability test,
2) under what conditions the device is used (regarding “under the specified conditions”),
3) how long the device is used (regarding “during the intended period”), and
4) what criteria should be set (regarding “provision of the specified function”).
After that, based on these clarified items, it is the most important to determine
5) the target reliability (allowable probability).
Various stresses are applied to semiconductor devices, and the stress type depends on the device
manufacturing/use stage, such as the assembly stage (assembly of the device into equipment), adjustment
stage, field installation stage, and operation stage.
Table 2.1 shows examples of environmental stresses and operational stresses. The reliability test simulates
or accelerates these stresses (stresses that may be applied to semiconductor devices). The test method
described later specifies the standard stresses.
Table 2.1
Examples of main environmental stresses and
operational stresses that may be applied to semiconductor devices
Soldering
Solvent
Shock, fall
Vibration, resonance
Tension
Bending
Operational stress
Thermal Electromagnetic
stress
stress
Natural stress
Temperature and change
in temperature
Humidity and change in
humidity
Rain, water
Wind
Lightning
Pressure (low, high)
Dust, dirt
Mold, microbes
Radiation
Electromagnetic waves
Corrosive atmosphere
Artificial stress
Environmental stress
Current
Voltage
Surge, noise
Electric field, magnetic
field
Temperature rise
Local heating
Factor for determination
of stress type
Continuous or intermittent
Time length
Frequency
Repeating speed
Periodicity
Multiple stresses
Change in stress
Speed
Stress application order
T04007CE-2 2012.1 2-5
2
Reliability of Semiconductor Devices
b) Purposes and types of reliability test
For semiconductor devices, the reliability test is performed at each stage of development and mass production.
When a semiconductor device is developed, the reliability test will be performed to check the design, material,
and process. When a semiconductor device is mass-produced, the reliability test will be performed as a quality
assurance inspection or failure rate test to predict the reliability of the device. In this way, the purposes and the
types of the reliability test greatly depend on the device manufacturing stage.
The main purposes and types of reliability test are shown in Table 2.2.
Table 2.2
Purposes and types of reliability test
Purpose
Type
Sample
To clarify the reliability level
(To be performed at the research and
development stage)
Standard test
Accelerated test
Marginal test
Service test
Wafer process TEG
Assembly process TEG
Basic circuit TEG
Product
To examine whether standardization is needed
(To be performed at the research and
development stage)
Simulation test
Marginal test
TEG
Product
To ensure reliability
Form test
(To be performed at the mass-production stage) Qualification test
Lot assurance test
Product
Standard test
To carry out screening
(To be performed at the mass-production stage)
Product
The reliability test generally has problems of “time and cost”. This means that the durability test and the
life test require a lot of time, and a failure may not occur if the test is performed under the assumed normal use
conditions. So, we should take some measures:
The test should be accelerated by simulating practical use.
Similar samples should be tested at the same time to compare them with each other.
Possible failures
should be preliminarily assumed, and test conditions that can cause the assumed failures should be adopted.
Otherwise, we should perform the accelerated test by sampling using a statistical method.
As the devices are upgraded and complicated, evaluation of the completed products only will be imperfect
and non-economical. So evaluation of elements will be important. Considering this, we are performing
upstream-control type evaluation and important-part broad evaluation using various TEGs (test element
groups).
c) Reliability test and classification
For the reliability test, the following items should be determined considering the object of the test, product
application, purpose of the test, etc.:
1) Appropriate test method (test items, test type)
2) Test conditions
3) Failure criterion
4) Acceptance/rejection criterion
T04007CE-2 2012.1 2-6
2
Reliability of Semiconductor Devices
This means that the test plan depends on the test type: 1) test for determination of the limit (ability clarification
test) and 2) test for judging whether the product can be accepted by the specified standards (quality assurance
test). When we select the environmental conditions and stresses for the test, we should consider the objective
failure mode, device process, structure, package, use conditions, etc.
As shown in Table 2.1, there are various stresses, such as electric stress, temperature stress, humidity stress,
mechanical stress and special environments. There also are various stress application methods, such as single
stress application method, series stress application method and composite stress application method.
The main stress application tests and their purposes are shown in Table 2.3.
Table 2.3
Various types of stress application tests and their purposes
Test type
Purpose
1. Weatherability tests
1) Moisture soaking and soldering heat stress
series test
2) Continuous operation test
3) High-temperature storage test
4) Low-temperature storage test
5) Temperature humidity storage test
6) Temperature humidity bias test (THB test)
7) Unsaturated steam pressure compression
bias test (USPCBT)
8) Temperature cycle test
9) Moisture resistance (Cyclic) test
10) Thermal shock test
11) Sealing test
12) Low air pressure test
13) Salt mist test
࡮To evaluate whether semiconductor devices stored or
in use are resistant to the environmental conditions
࡮To evaluate whether semiconductor devices are
resistant to repeated rapid temperature change or
storage
࡮To evaluate whether semiconductor devices placed at
high relative humidity are resistant to long-time use or
storage
2. Mechanical tests
1) Terminal strength test
2) Mounting strength test
3) Vibration (Sinusoidal) test
4) Shock test
5) Acceleration (Steady state) test
6) Drop test
7) Solderability test
8) Resistance to soldering heat test
࡮To evaluate whether semiconductor devices being
transported are resistant to mechanical stresses caused
by careless handling
For the terminals, the purpose is to evaluate whether
terminals are resistant to the external forces that may
be applied during device mounting, wiring or use.
࡮To evaluate solderability of terminals, and to evaluate
whether terminals are resistant to high temperature
during soldering
3. Other tests
1) Electrostatic discharge sensitivity test
2) Latch-up test
3) Permanence of marking test
࡮To evaluate whether the semiconductor devices being
transported, assembled or used are resistant to such
special environmental conditions.
Conventionally, single stresses are tested in many cases due to the failure mode and the failure mechanism
analysis. However, as the devices are upgraded and the use conditions are complicated, series stresses and
composite stresses are applied in practical use. For this reason, testing for these types of stresses is demanded
now.
T04007CE-2 2012.1 2-7
2
Reliability of Semiconductor Devices
In addition, it is necessary to examine the stress strength, stress application method from the viewpoint of
time, and whether the screening or sampling method should be adopted. Table 2.4 shows classification of
reliability tests.
Table 2.4
Classification of reliability tests
Test place
Stress strength
1. Field test
Stress application method
from viewpoint of time
1. Normal life test
1. Life test
Reliability
test
1. Destructive test
2. Simulation test
(Test in
laboratory)
2. Non-destructive
test
2. Marginal test
2. Accelerated life test
3. Forced deterioration test
4. Step stress test
5. Storage test
1. Operation
test
1. Normal use test
2. Storage test
3. Screening
2. Environmental test
d) Concept of reliability test
When carrying out the reliability test, we are very careful about the following items:
In the development stage:
1) Setting of target reliability
Setting of target reliability depending on the use environment, use conditions, and use period
2) Reliability test procedure
Wafer process evaluation test using TEG (test element group)
Assembly process evaluation test using TEG
Basic design evaluation test using TEG
Total test using devices
3) Ability clarification and failure prediction using marginal test
4) Failure examination
Failure mode, failure mechanism, failure distribution, acceleration factors
In the mass-production stage, we are emphasizing implementation of the optimum reliability test regarding
time so that we can ensure delivery quality. For all the items described above, we will accumulate the test results
and will effectively use the results for quality improvement and reliability improvement. In addition, we will
thoroughly analyze the nonconforming products detected by testing, and will feed back the analysis results
to the development division and the factory to improve the products. We always think of the reliability test
as a method to satisfy our users and to ensure quality and safety of our products.
T04007CE-2 2012.1 2-8
2
2.2.2
Reliability of Semiconductor Devices
Reliability evaluation method using TEG2.3)
Due to further miniaturization and integration of semiconductor devices, it is now difficult to investigate
the causes of failures when failures occur by only carrying out the device reliability test. So, we evaluate
reliability using the TEG (test element group) of each process element, such as oxide film and wire, before
starting the reliability test of devices to be finally delivered. There are several TEGs: TEG for evaluation of
the wafer process, TEG for evaluation of the assembly process, and TEG for evaluation of circuit operation.
Using these TEGs, we evaluate reliability to examine the following items:
Cause and mechanism of degradation for each process element
Reaction speed of each degradation mechanism (acceleration factors of temperature, voltage, current, etc.)
Which degradation mechanism has the greatest influence on the device properties in actual use
We feed back the results of examination to the corresponding processes so that we can improve the processes
and can increase reliability. In addition, we add dimensional limits, voltage limits, etc. to the design manual
(design rules) so that we can develop highly reliable semiconductor devices. Table 2.5 shows the characteristics
of reliability evaluation when TEGs are used and when semiconductor devices are used. TEGs and semiconductor
devices have their own advantages and disadvantages when used for reliability evaluation, so both are
indispensable to improve reliability of semiconductor devices. In recent years, we have enlarged the scale of
the TEGs so that we can use the TEGs to extract the problems of large-scale integrated circuits and to verify
the process dispersion.
Table 2.5
Characteristics of reliability evaluation when TEGs are used and
when semiconductor devices are used
Reliability evaluation using TEG
Reliability evaluation using semiconductor devices
࡮Enables evaluation of each failure mechanism. ࡮It is difficult to determine the failure
mechanism.
࡮Facilitates the high acceleration test.
࡮Facilitates wafer evaluation at the early stages. ࡮It is difficult to carry out the high acceleration
test.
࡮It is difficult to extract the problems of large࡮Facilitates extraction of the problems of largescale integrated circuits.
scale integrated circuits.
࡮It is difficult to examine the process dispersion.
࡮Mainly used for evaluation of the process or
࡮Used for evaluation of the manufacturing
circuit design quality.
quality and the circuit design quality.
࡮Facilitates relative comparison that should be
carried out when a process is subject to change.
T04007CE-2 2012.1 2-9
2
Reliability of Semiconductor Devices
Table 2.6 shows the typical reliability problems and failure mechanisms that should be evaluated using
TEGs. The details of failure mechanisms, including these, are described in Chapter 3.
Table 2.6
Problems that should be solved to ensure high reliability
Reliability problems
Hot carrier
Slow trap (NBTI)
Time dependent breakdown of oxide film and
dielectric film
Electromigration
Stress migration (Stress induced void)
Multilayer structure of wire (pinhole, crack)
Soft error
Electrostatic discharge sensitivity
Latch-up
Moisture resistance
Thermal stress
2.2.3
Example of failure mode
Delay in operation speed
Delay in operation speed
Bit failure, leakage, short-circuit of memory
Wire disconnection, short-circuit
Wire disconnection
Wire disconnection, short-circuit
Instantaneous abnormal operation of memory
Destructive failure
Destructive failure, defective property
Wire disconnection, defective property
Package cracking, chip cracking, passivation
film cracking, wire sliding
Reliability test method
a) Concept of reliability test method
Reliability test should be carried out under the same conditions as the practical use as far as possible. In addition,
it is demanded that the reliability test should always be repeatable. The field test carried out at the local site is
the optimal test because the test can be carried out in the same conditions as the practical use. In most cases,
however, time and cost are limited for the reliability test. So it is difficult to obtain enough information by carrying
out a field test. So, we simulate practical use to carry out the reliability test.
For the simulation test, non-destructive stress strength is generally selected. In some cases, however, destructive
stresses are intentionally applied so that the failure can be caused earlier and we can carry out failure analysis earlier.
Regarding the stress application time, there are two types of stress application methods: continuous stress
application and intermittent stress application. We select the optimal stress application method so that the test can
be carried out under the same conditions as the practical use as far as possible.
The reliability test items are normally classified into individual test items to facilitate repeatability, failure
analysis, etc. However, to adopt the practical use conditions as far as possible, pre-treatments are added, and
a series test and composite test are carried out in many cases.
In addition, it is preferable for the reliability test that comparison with the past data and comparison with
the other product types can be performed easily and accurately. For this reason, the reliability test should be
performed under known stress conditions and the test method should be standardized as far as possible. For
the semiconductor devices, the conventional standard test methods are specified in the JEITA standards, IEC
standards, JEDEC standards and MIL standards, and various other test methods are specified in the standards
established by Japanese government offices or industrial organizations in Japan and many other countries.
T04007CE-2 2012.1 2-10
2
Reliability of Semiconductor Devices
The main standards specifying the reliability test methods are shown in Table 2.7. There are slight
differences in these test methods and conditions, but their intended purposes are the same.
Table 2.7
Main standards specifying reliability test methods
IEC standards (IEC: International Electrotechnique Commission)
IEC 60068:
Environmental testing - Electric, electronic
IEC 60747:
Semiconductor devices
IEC 60748:
Integrated circuits
IEC 60749:
Semiconductor devices - Mechanical and climatic test methods
MIL standards (MIL: Military Specifications and Standards, officially titled as United States
Defense Standard)
MIL-STD-202G: Test Method Standard, Electronic and Electrical Component Parts
MIL-STD-750E: Test Method Standard, Test Methods for Semiconductor Devices
MIL-STD-883G: Test method Standard, Microcircuits
JEITA standards (JEITA: Japan Electronics and Information Technology Industries Association)
ED-4701:
Environmental and endurance test methods for semiconductor devices
ED-4702A:
Mechanical stress test methods for semiconductor surface mounting devices
JEDEC standards (JEDEC [Joint Electron Devices Engineering Council] Solid State Technology
Association)
JESD22:
Reliability test methods for semiconductor devices
J-STD-020D.01: Moisture/reflow sensitivity classification for nonhermetic solid state surface
mount devices
JESD78B:
IC latch-up test
b) Reliability test standard specified by Semiconductor Business Group, Industrial Devices
Company, Panasonic Corporation
In accordance with various standards shown in Table 2.7, etc., we have established the “Environment Test
Method and Durability Test Method for Semiconductor Devices” as the practical reliability test standard so
that we can satisfy various customer demands and can solve various problems peculiar to products, chips,
packages, and surface mounting, etc. Table 2.8 shows the main test items specified in this standard, outline
of contents and test conditions, and reference standard numbers to show the JEITA, IEC, and JEDEC
standards to which we referred.
Features of this standard:
1) The criteria specified in this standard are generally stricter than the other standards or as strict as the
other standards.
2) Heating + surface mounting thermal stress application should be performed as pre-treatment before
starting some types of life test or moisture resistance environment test.
3) High-temperature storage or high-temperature high-humidity storage should be performed as pretreatment before starting the solderability test.
4) During soldering heat resistance test of surface mounting devices, the surface mounting thermal stress
should be applied to the entire products.
T04007CE-2 2012.1 2-11
2
Reliability of Semiconductor Devices
Table 2.8
Test item
Standard
name
Outline of our reliability test methods for semiconductors
Our standard
JEITA
JEDEC
IEC 60749
ED-4701
JESD22
Applies electric (voltage, current) and thermal stresses to an
Test
element for a long time to judge whether the element is resistant method
to such stresses.
101
Continuous operation (Standard test conditions)
test
Ambient temperature: Maximum operation temperature (Toprmax)
Voltage: Maximum rated voltage (Vddmax)
Test time: 1,000 h
Part23
A108C
Part6
A103C
High-temperature
storage test
Stores the test piece at a high temperature for a long time to judge Test
whether the test piece is resistant to such a thermal condition.
method
(Standard test conditions)
201
Ambient temperature: Upper limit of rated storage temperature
(Tstgmax)
Test time: 1,000 h
Low-temperature
storage test
Stores the test piece at a low temperature for a long time to judge Test
whether the test piece is resistant to such a thermal condition.
method
(Standard test conditions)
202
Ambient temperature: Lower limit of rated storage temperature
(Tstgmin)
Test time: 1,000 h
A119
㧙
Applies electric stress to a device at a high temperature and high Test
humidity for a long time to judge whether the device is resistant method
102
Temperature humidity to such stress.
(Standard test conditions)
bias test (THB test)
Ambient conditions: 85°C, 85%RH
Voltage: Standard voltage (Voltage that can prevent internal heating)
Test time: 1,000 h
Part5
A101B
Applies electric stress to a device at a high temperature and high Test
humidity for a long time to judge whether the device is resistant method
to such stress.
102
Unsaturated vapor
(Standard test conditions)
compression bias test Ambient conditions: 130°C, 85%RH
(USPCBT)
Voltage: Standard voltage (Voltage that can prevent internal heating)
Test time: Individually specified
Note: Either the THB test or the USPCBT should be carried out.
Part4
A110C
㧙
㧙
Part5
A104C
Thermal humidity
storage test
(TH storage test)
Stores the test piece at a high temperature and high humidity for a Test
long time to judge whether the test piece is resistant to such a
method
storage condition.
103
(Standard test conditions)
Ambient conditions: 85°C, 85%RH
Test time: 1,000 h
Temperature cycle
test (Vapour phase)
Exposes the test piece to temperature change to judge whether the Test
test piece is resistant to temperature change.
method
(Standard test conditions)
105
High temperature side / low temperature side: maximum storage
temperature (Tstgmax) / minimum storage temperature (Tstgmin)
Test cycle: 10 cycles
T04007CE-2 2012.1 2-12
2
Test item
Standard
name
Thermal shock test
(Liquid phase)
Moisture resistance
(Cyclic) test
Reliability of Semiconductor Devices
Our standard
JEITA
JEDEC
IEC 60749
ED-4701
JESD22
Exposes the test piece to rapid temperature change to judge
whether the test piece is resistant to rapid temperature change.
(Standard test conditions)
High temperature side / low temperature side: maximum storage
temperature (Tstgmax) / minimum storage temperature (Tstgmin)
Test cycle: 10 cycles
Test
method
307A
Condition
E
Exposes the test piece to temperature change at a high humidity
to judge whether the test piece is resistant to temperature change
in such a condition.
(Standard test conditions)
Ambient conditions:
Test
method
203
65°C/90㨪96%RH
Part4
A106B
㧙
㧙
J-STD020D.01
‫ ޓ‬25°C/90㨪96%RH
‫ޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓ‬
−10°C
‫ޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓޓ‬
One cycle (24 h)
Test cycle: 10 cycles (240 h)
Test
method
104
301B
302
Part20
Soldering heat
resistance test
Judges whether the test piece is resistant to the heat during
soldering work.
(Standard test conditions)
࡮Pre-treatment of humidification
‫ޓ‬Under the specified humidification conditions
࡮Conditions for infrared radiation or air reflow (for SMD,
Pb-free solder)
‫ޓ‬Peak temperature: °C, tolerance: +5/−0
Volume:
350㨪
Thickness:
2000
mm3 350 2000
mm
260
260
260
<1.6
260
250
245
1.6㨪2.5
250
245
245
2.5
‫ޓ‬Time for peak temperature of −5°C or more (s)
Condition A 10 +6/−0
Condition B 20 +6/−0
Test
method
303A
Part21
B102E
Solderability test
Judges whether the terminal area ensures solderability.
(Standard test conditions)
࡮Aging conditions: 105°C, 100%RH, shelf time:
4 hours (8 hours for test pieces other than SMD)
࡮Soldering bath temperature: 245°C, dipping time:
5 s (Pb-free solder)
Judges whether the terminal area has enough strength and is
Test
resistant enough to the force to be applied by the connected wires method
or the force to be applied during use.
401A
1) Tension test: Applies the specified tension in the pull-out axis
direction, and holds the tension for 30 seconds.
2) Torsion test: Applies the specified torsion using the pull-out
axis as the rotation axis, and holds the torsion for 15 seconds.
Terminal strength test 3) Bending test: Bends the terminal from the pull-out axis to the
specified angle, and then returns the terminal to the initial position.
4)Torque test for threaded terminal: Applies the torque after
fitting the washer and nut.
5) Fatigue test: Hangs the specified weight from the front end of
the terminal.
6) Shear test: Applies a load to the solder ball at the specified
height and speed.
Part14
B105C
(Not
specified
in
JESD22)
T04007CE-2 2012.1 2-13
2
Reliability of Semiconductor Devices
Test item
Standard
name
Our standard
JEITA
JEDEC
IEC 60749
ED-4701
JESD22
Judges whether the test piece is resistant to vibration to be
applied during transportation or use.
(Standard test conditions)
Frequency range: 100 Hz to 2,000 Hz, Acceleration: 200 m/s2
Sweep: 100 Hz - 2,000 Hz - 100 Hz
Approx. 4 min
Vibration direction: X, Y, and Z directions, 4 cycles for each
direction, 48 minutes in total
Test
method
403
Part12
B103B
Vibration (Sinusoidal)
test
(To be applied to
hollow package
semiconductor
devices)
Judges the structural and mechanical resistances.
(Standard test conditions)
Maximum acceleration and pulse width: 15,000 m/s2, 0.5 ms
(Test condition D)
Shock application direction: X1, (X2), Y1, Y2, Z1, (Z2)
The directions shown in parentheses can be omitted in
accordance with the individual standards.
Number of shock application times: 3 times for each direction
Test
method
404
Condition
D
Part10
B104C
Shock test
(To be applied to
hollow package
semiconductor
devices)
Electrostatic
discharge sensitivity
test
(HBM)
Judges whether the test piece is resistant to static electricity to be Test
generated during storage, transportation, or assembly.
method
(Standard test conditions)
304
Test circuit: C = 100 pF, R = 1,500 Ω (Condition for HBM test)
Part26
A114F
Part29
JESD78B
Latch-up test
Judges whether the test piece (CMOS device, mainly) is resistant Test
method
to latch-up.
306
(Standard test conditions)
1) Pulse current input method
2) Overvoltage supply method
Test
method
204
Part13
Salt mist test
Judges whether the test piece is resistant to corrosiveness of the
salt water atmosphere.
(Standard test conditions)
Salt water temperature: 35°C,
Salt water concentration: 5% (Mass ratio), Test time: 72 h
Steady state
acceleration test
(To be applied to
hollow package
semiconductor
devices)
Judges whether the test piece is resistant to constant acceleration. Test
method
(Standard test conditions)
405
Maximum acceleration: 300,000 m/s2
Directions: X1, X2, Y1, Y2, Z1, and Z2 directions
Time: 1 min for each direction
Part36
Sealing test
(To be applied to
airtight package
semiconductor
devices)
Judges whether seals are airtight.
(Standard test conditions)
1) Fine-leakage test using radio isotope
2) Fine-leakage test using helium gas
3) Gross leakage test using bubbles
Ta = 125°C
Part8
T04007CE-2 2012.1 2-14
Test
method
503
(Not
specified in
JESD22)
A107B
㧙
A109A
2
2.2.4
Reliability of Semiconductor Devices
Failure criterion
To carry out the reliability test, it is necessary to define the failures. In other words, it is necessary to clarify
the criteria to judge whether devices should be accepted or rejected. There are various types of failures: major
failures, such as destructive failures (wire breakage, short-circuit); functional failures; and minor failures
(increase in leakage current, increase in wire resistance, operation power variation in the allowable range). In
this way, the seriousness of each failure depends on the degree of deterioration. We, therefore, should
carefully determine the failure range. In other words, we should carefully determine the criteria for judgment
of failures. This is because the result of reliability test greatly depends on the determined criteria.
It is ideal that the parameter values of all the characteristics (electric characteristics, etc.) and performances
not vary from the initial values. Parameter values of some characteristics, however, vary. For the reliability
test, therefore, the failure criteria should be determined as follows:
1) Margins for the circuits and use conditions should be obtained.
2) Limits for reliability control should be determined.
Method 1 determines the criteria from the characteristics required for the machine. Method 2 determines
the criteria depending on the failure mode or the failure mechanism of the device (physical concept of the
failure). Practically, it is preferable that both methods should be used.
These criteria normally do not indicate the limit points where system failures occur in practical use, but are
used as the criteria for strict judgment in quality and reliability evaluations in a comparatively short period.
For method 1, the failure criteria are generally determined from the specified tolerance values. Specifically,
the upper limit values are generally determined as the upper 10% of points of the initially specified upper
limit values, and the lower limit values as the lower 10% of points of the initially specified lower limit values.
For method 2, the change rate of each initial characteristic value is used as the failure criterion. For a detailed
description, refer to the individual specification of the corresponding product.
T04007CE-2 2012.1 2-15
2
Reliability of Semiconductor Devices
2.2.5
Accelerated life test
a) Concept of accelerated life test
The following basic concept for the accelerated test is important: “Occurrence of a failure should be promoted
by setting stricter conditions than the practical use conditions, and then from the obtained life, the life under
the normal use conditions should be obtained considering the correlation between two ...”. This means that the
same failure mechanism and the same failure mode as the practical use should be adopted for the test. In other
words, if the failure mechanism and the failure mode are not the same, the accelerated test will not be
successful. There are some stresses that can be accelerated. They are the environmental stresses (temperature,
humidity, vibration, stress, etc.), electric stresses (voltage, current, etc.), etc. It is important that we know to
what extent we can accelerate these stresses.
b) What is an accelerated test?
An accelerated test is defined as a “test that should be carried out under the stricter conditions than the
reference conditions for the purpose of reduction in the test time”. In addition, the life prediction method for
the accelerated test is defined as a “method that promotes the failure mechanism by adopting the stricter
conditions to quickly assume the actual life under the practical use conditions using the correlation between
the two”.
To assume the life and the failure rate for a product, the reliability test will be carried out. For this test,
however, if the failure does not occur, it is difficult to use the data analysis method, such as the Weibull
analysis method and the Arrhenius model. Regarding the statistical assurance of reliability, if it is necessary
to ensure 0.01% for 103 hours, approximately 2,300 samples and 104 hours are needed for the conditions of
“C = 0 and β = 0.1”. In this way, an enormous number of samples and enormous amount of time are needed
for the reliability test (refer to MIL-S-19500C).
To check and ensure the reliability of a product, a reliability test should be carried out, but as described
above, the reliability test needs many samples and much test time. So, we should adopt the accelerated test
to quickly estimate the life and the failure rate by physically and chemically accelerating the practical use
conditions of products (by reducing the number of samples, shortening the test time, and adopting stricter
stresses).
c) Necessity of accelerated test
To break the barriers of the “number of samples, test time, and cost”, it is necessary to check the reliability
from the practically and economically using the accelerated test.
When checking the reliability of semiconductors, we will encounter the following problems:
1) Systems are considerably upgraded and complicated.
2) Techniques are remarkably innovated.
3) Practical use conditions and ambient conditions are getting much stricter and more diversified.
4) High reliability should be ensured.
5) The life (life cycle) of products is being shortened.
6) Long life is demanded for industrial use.
T04007CE-2 2012.1 2-16
2
Reliability of Semiconductor Devices
To solve these problems and to ensure reliability of semiconductors, it is necessary to take the following actions:
1) Quick evaluation
2) Evaluation for important reliability items by predicting possible problems
3) Evaluation considering the use conditions and the environmental conditions
4) Accumulation of basic data that can be used for general purposes in the future
To obtain satisfactory results from reliability check, it is necessary to carry out the accelerated test. We can
expect the following effects from the accelerated test:
(a) The reliability can be predicted.
It is important to assume the reliability from the accelerated test result. Since techniques are remarkably
innovated in the semiconductor field, assumption of the reliability is indispensable.
(b)The ability of the product can be clarified.
If the reliability test is ramblingly carried out only using the test methods specified in the conventional
test standards or specifications, it may result in a waste of time and cost. Carrying out the reliability test
in such a way only eases our minds. It is, therefore, important that we should push the limits of using the
accelerated test to clarify the ability of the product and the margin in practical use. After carrying out the
accelerated test, we should check the correlations between the quality shown in the accelerated test result
and the actual market quality, and there should not be any differences between them. It is, therefore, important
that we should collect field data and analyze the failure modes to follow up the correlations between the
quality obtained by predicting the reliability and the actual market quality.
d) Application of failure physics to accelerated test
1) Arrhenius model
When microscopically observed, destruction of a substance is caused by a change at the atomic or molecular
level. For example, electric stress, thermal stress, or mechanical stress applied to a substance will cause change
(chemical change, composition change, crystal structure change, binding power change, etc.) in the balanced
condition inside the substance to finally cause a failure.
The generally used reaction model theory is that since the semiconductor products are devices to which the
physical and chemical changes on the surfaces of substances are applied, if physical or chemical reaction
harmful to a semiconductor is promoted to the limit point, a failure of the semiconductor may occur. There
are various electric, thermal and mechanical stresses. Among them, semiconductor products are the most
sensitive to the temperature stress. Arrhenius found that occurrence of a failure depends on the reaction rate
caused by the temperature stress (Arrhenius model). The Arrhenius model is exclusively used for semiconductor
products.
T04007CE-2 2012.1 2-17
2
Reliability of Semiconductor Devices
Equation of Arrhenius model:
lnL = A
Activated state
Ea/k T
Where, L: Life, A: Constant
Ea (Activation energy)
Ea: Activation energy
k: Boltzmann constant
Normal state
Deteriorated state
T: Absolute temperature
Figure 2.3
Activation energy
“Ea” in the above equation is referred to as “activation energy”. As shown in Figure 2.3, when the state
changes from the normal state to the deteriorated state, there is a barrier of energy. The energy necessary for
breaking the barrier is supplied from the outside. This energy is referred to as activation energy. Figure 2.4
shows the relation between the temperature and the life using the activation energy of the Arrhenius equation
as the parameter. As the activation energy is increased, the inclination of the line will become steep, and the
life will become more dependent on the temperature.
2) Activation energy and acceleration factor
The acceleration factor between two temperature points can be obtained as follows. Assume that “L1”
represents the life time at the temperature “T1”, and “L2” represents the life time at the temperature “T2”. In
this case, the acceleration factor “K” can be obtained using the following formula:
Where,
Ea: Activation energy
k: Boltzmann constant
T1, T2: Absolute temperature
Figure 2.5 shows the relation between the activation energy and the acceleration factor.
T04007CE-2 2012.1 2-18
2
Ea
=0
.3e
V
Acceleration factor K
E
a=
0.
105
0°C
/3
0°C
10
V
150
°C
104
6e
Ea
=1.
2eV
Ea
=1.
0eV
Ea
=0
.8e
V
106
/ 30
°C
105
107
Life (h)
Reliability of Semiconductor Devices
103
0°C
C
70°
/3
102
50°C
104
/ 30°
C
10
1000
T
( K −1)
2.5
3.5
150
50
1
25
0
0.5
Temperature (°C)
Figure 2.4
1.5
1.0
Activation energy Ea (eV)
Relation between
Figure 2.5
temperature and life
Relation between activation
energy and acceleration factor
The height of the energy barrier depends on the mechanism of the failure to be promoted. Table 2.9 shows
the typical failure modes, failure mechanisms and values of the activation energies of the semiconductor
products.
Table 2.9
Failure mode, failure mechanism and activation energy
Failure mode
Failure mechanism
Activation energy (eV)
VT shift
Ionicity (Drift of Na ions in SiO2)
0.7 ∼ 1.8
VT shift
Ionicity (Slow trap of Si-SiO2 interface)
0.8 ∼ 1.2
0.8 ∼ 1.0
Increase in leakage current Generation of inversion layer (MOS)
Increase in leakage current Channel effect (Diode)
0.5
Reduction in hFE
Acceleration of ionic migration by water content
Wire disconnection
Al corrosion
0.7 ∼ 0.9
Wire disconnection
Electromigration of Al
0.5 ∼ 0.7
Short-circuit
Breakdown of oxide film
0.3 ∼ 1.1
0.8
These activation energy values are obtained from the past reliability evaluation results. Contrary to this way,
we can also assume the failure mechanism from an activation energy value, and can use this technique for
improvement. This means that from the accelerated reliability test result, we can clarify the design quality at
the early stages, can assume the market quality, and can predict possible failures.
T04007CE-2 2012.1 2-19
2
Reliability of Semiconductor Devices
We can also use the Eyring model. For this model, the Arrhenius model has been developed and generalized
considering the influences of mechanical stresses, humidity, voltage, etc. Using the Eyring model, we can also
obtain the life “L” in the same way as the Arrhenius model. The following formula should be used for calculation:
lnL = A + B / T + n × lnS
Where, “S” represents the function of any stress excluding the temperature stress.
e) Acceleration by humidification
1) Various types of humidity accelerated test
Applications of the resin-sealed semiconductor products are being increasingly diversified because the
material costs are low. In addition, the resin-sealed semiconductor products are suitable for mechanization and
labor saving, and resistant to vibration. However, the great disadvantage of the resin-sealed semiconductor
products is that they are not resistant enough to humidity (moisture). If the base of the semiconductor is
plastic, such as epoxy, it is difficult to protect the semiconductor from humidification to some extent. The
humidified semiconductor products are unreliable because they have two great problems. These are:
(a) Disconnection of Al wire due to corrosion
Phosphorus in protective film, impurity ions in sealing resin, water entered through moisture-permeable
interface or lead-frame interface
(b) Property deterioration
Water and impurity ions entered
To evaluate the moisture resistance in the early stages, there are many types of moisture resistance evaluation
tests. Table 2.10 shows typical accelerated tests for evaluation of moisture resistance. The optimal test should
be used depending on the semiconductor product type and the cause of the failure. The test methods can be
roughly classified into two types. One type of test method is to leave the semiconductor products in a
humidified atmosphere. The other type of test method is to apply the bias to semiconductor products while
humidifying the products or after adequately humidifying the products. Finally, the most important point is
that correlation with the market quality should be ensured. In addition, three elements should be ensured: the
failure modes and the failure mechanisms should be the same, enough acceleration should be ensured, and
repeatability should be ensured.
T04007CE-2 2012.1 2-20
2
Table 2.10
Reliability of Semiconductor Devices
Typical accelerated tests for evaluation of
moisture resistance of semiconductor devices
No.
Test item
Description
Typical temperature and humidity
Exposes the test piece to an atmosphere where a
Thermal humidity storage
certain temperature and relative humidity (less
test
than 100%RH) are kept.
60°C࡮90%RH
2
Thermal humidity bias test Same as above + application of bias
Same as above
3
Boiling test
4
Saturated pressure cooker Exposes the test piece to saturated steam of
test
1.013 × 105 Pa or more.
121°C࡮100%RH
5
Unsaturated pressure
cooker test
Exposes the test piece to unsaturated steam of
1.013 × 105 Pa or more.
121°C࡮85%RH
6
Unsaturated pressure
cooker bias test
Same as above + application of bias
7
Pressure cooker test
Carries out the pressure cooker test as
+
pre-treatment of the thermal humidity bias test.
thermal humidity bias test
8
Temperature cycle test
+
pressure cooker test
Carries out the temperature cycle test as
pre-treatment of the pressure cooker test.
9
Series test
Series test or composite test where the above
moisture resistance tests are combined with
mechanical tests or thermal resistance tests
(Ex. No. 7 or 8)
1
Dips the test piece into boiled water.
85°C࡮85%RH
Into deionized water of 100°C
Same as above
121͠࡮100%RH࡮8 h
+85°C࡮85%RH
125°C to −55°C, 5 times
+121°C࡮100%RH
The moisture resistance test should be carefully carried out because there are many factors (impurities,
materials, processing method, etc.) that may affect the failures.
In addition, if the relative humidity is 100%, dew condensation may be caused, and the correlation with the
market failures and repeatability may not be ensured. If the test is extremely accelerated, a failure mode that
cannot occur in practical use may occur during the test, and repeatability of the test may not be ensured. So,
the test should be carried out carefully.
2) Acceleration models for failures that are caused by humidity
Some acceleration models are reported, and these models can predict the reliability of resin-sealed semiconductor
products in practical use using the results of the moisture resistance test. These models are:
(a) By F.N. Sinnadurai (BPO)2.4), Maeda (Matsushita Electronics)2.5)
Until the accumulated failures are increased to 10%, the relation between the time “t” and the vapor
pressure “Vp” can be expressed as follows:
t ∝ Vp-n
Where, n = 4.1 (F.N. Sinnadurai), 2.0 (Maeda)
T04007CE-2 2012.1 2-21
2
Reliability of Semiconductor Devices
(b)By N. Lycoudes (Motorola)2.6)
t50 = Aexp(Ea/kT) × exp(B/RH) × V-1
Where, (V: Applied voltage, RH: Relative humidity)
(c) By Suzuki (Nippon Telegraph and Telephone Public Co.)2.7)
To assume the practical use condition, Arrhenius model (1/T) can be used. Using this model, the
temperature term can be obtained from the parallel straight line “f(RH)” of each humidity. The following
empirical formula can be used:
tMED = C exp(Ea/kT) f(RH)
Panasonic has carried out various moisture resistance accelerated tests2.5). As an example, Figure 2.6 shows
the temperature dependency of bipolar IC failures and MOSLSI failures at relative humidity of 85%RH.
Failures occurred at the same rate at any temperature. The bipolar IC caused Al wire corrosion, and the MOS
LSI caused property failures. From the test results obtained from several tens of test types, we obtained the
moisture resistant life using the following general acceleration formula:
L = Aexp(Ea/kT) f(RH) g(V)
Relative humidity:
85%RH
Mean times to failure (h)
Where, f(RH) = A’ exp(B/RH)
g(V) = A” V-n
L: Mean life
Ea: Activation energy
RH: Relative humidity
V: Applied voltage
Bipolar IC
104
CMOSLSI
103
1.0eV
0.8eV
102
A A’ A” B n: Constant
130°C
140°C 121°C
k: Boltzmann constant
85°C
1
10
25
Junction temperature
Figure 2.6
30
1000 −1
K
Tj
Temperature dependency of time to failure
Regarding the above general acceleration formula, the voltage cannot be greatly increased considering the
integrated circuit function conditions. In addition, considering the practical use conditions, the relative humidity
value cannot be greatly increased, either. So we cannot expect a great acceleration by increasing the voltage or
humidity. Consequently, it can be said that raising the absolute humidity by raising the temperature is the most
effective. However, considering the characteristic limit value of the resin material, we assume that approximately
140°C is the upper limit acceleration value.
From the results of various tests carried out in our company, we have determined the acceleration factor
(acceleration rate against practical use [worst] conditions) for the products manufactured from the standard
material in the standard process as shown in Table 2.11.
T04007CE-2 2012.1 2-22
2
Table 2.11
Reliability of Semiconductor Devices
Acceleration factor for moisture resistance of general products
(property change, Al corrosion)
Relative humidity: 85%RH, Ea = 0.88 eV
Applied voltage: Voltage of standard circuit
Tj (°C)
30
40
65
85
121
130
140
2.2.6
Factor
1
3
20
160
2,240
4,000
7,360
Reliability test by sampling
a) Sampling inspection for reliability
Most of the reliability tests are accelerated tests, and generally these tests have destructive testing elements.
Regarding the testing cost and test equipment, it is difficult to perform a 100% inspection. So, just like the
inspection for quality control, sampling is adopted for the reliability test. For this sampling test, products will
be sampled from a population consisting of mass-produced products whose design and manufacturing process
are the same, and the sampled products will be accepted or rejected based on the test result. Compared with
the sampling inspection for quality control, an additional element of “time” is added to the sampling inspection
for reliability. The following are the main differences between the sampling inspection for reliability and the
sampling inspection for quality control:
1) In place of percent defective, the failure rate is used as a measure.
2) When calculating a measure from the test samples, it will take too much time to wait until failure occurs
on all the samples. So, the test should be ended in the middle as follows:
When the number of failures has increased to the specified number, the test should be ended.
Fixed
number test plan
When the test time has increased to the specified time, the test should be ended.
Fixed time test
plan
3) For quality control, the normal distribution is the basic distribution. For the reliability test, the exponential
distribution is mainly used.
4) For quality control, it is necessary to examine the manufacturer risks and the consumer risks. For the
reliability test, however, it is necessary to validate the assumption of the life distribution.
5) The test generally requires a lot of time. So, the accelerated test is frequently used.
6) It is necessary to determine the acceleration factor optimum for the corresponding failure mode.
The sampling inspection based on exponential distribution is the best sampling method because the theory
is prepared after enough research. In addition, this theory is standardized. Table 2.12 shows the sampling
inspection method specified in United States Defense Standard MIL-S-19500. This sampling inspection is the
T04007CE-2 2012.1 2-23
2
Reliability of Semiconductor Devices
exponential distribution type and counting once type (α = 5%, β = 10%). How to use the sampling method
is described below:
(a) Determine the maximum failure rate “λ1”.
(b)For “λ1”, determine the allowable number of failures for acceptance “C”.
(c) From “λ1” and “C”, find out the corresponding size “n”.
(d)Carry out random sampling from a lot so that the number of samples can be “n”, and carry out the test
for the specified time. At the completion of the test, if the total number of failures does not exceed the
value “C” (allowable number of failures for acceptance), accept the lot.
If the lot is accepted, it can be said that “the failure rate of the lot is lower than “λ1” when the reliability level
is 90%”. From Table 2.12, we can obtain the sample size “n” and the allowable number of failures for acceptance
“C” to ensure allowable failure rate of “λ1” when the consumer risk is 0.1 (β = 0.1).
For example, when we want to ensure λ1 = 5% by the 1,000-hours test, and if the allowable number of samples
for acceptance is “0” (C = 0), the sample size should be “45”, according to the table.
If the sample size is doubled, in other words, if the sample size is set to “90”, the following calculation
should be carried out due to the characteristic of exponential distribution:
λ = r/T = r/(n T)
Total testing time: T (sample size “n”× testing time), number of failures: r
Since judgment of acceptance or rejection is possible, the testing time can be shortened to 1/2 (500 hours). If
the accelerated test is adopted and the acceleration factor can be doubled, the sample size or the testing time
can be shortened to 1/2.
T04007CE-2 2012.1 2-24
8
(0.64)
13
(2.7)
18
(4.5)
22
(6.2)
27
(7.3)
31
(8.4)
35
(9.4)
39
(10.2)
43
(10.9)
47
(11.5)
51
(12.1)
54
(12.8)
59
(13.0)
63
(13.4)
67
(13.8)
71
(14.1)
74
(14.6)
79
(14.7)
83
(15.0)
86
(15.4)
90
(15.6)
109
(16.1)
30
11
(0.46)
18
(2.0)
25
(3.4)
32
(4.4)
38
(5.3)
45
(6.0)
51
(6.6)
57
(7.2)
63
(7.7)
69
(8.1)
75
(8.4)
83
(8.3)
89
(8.6)
95
(8.9)
101
(9.2)
107
(9.4)
112
(9.7)
118
(9.86)
124
(10.0)
130
(10.2)
135
(10.4)
163
(10.8)
20
10
7
5
3
2
1.5
1
0.7
0.5
0.3
15
(0.34)
25
(1.4)
34
(2.24)
43
(3.2)
52
(3.9)
60
(4.4)
68
(4.9)
77
(5.3)
85
(5.6)
93
(6.0)
100
(6.3)
111
(6.2)
119
(6.5)
126
(6.7)
134
(6.9)
142
(7.1)
150
(7.2)
158
(7.36)
165
(7.54)
173
(7.76)
180
(7.82)
217
(8.08)
22
(0.23)
38
(0.94)
52
(1.6)
65
(2.1)
78
(2.6)
91
(2.9)
104
(3.2)
116
(3.5)
128
(3.7)
140
(3.9)
152
(4.1)
166
(4.2)
178
(4.3)
190
(4.5)
201
(4.6)
213
(4.7)
225
(4.8)
236
(4.93)
248
(5.02)
259
(5.12)
271
(5.19)
326
(5.38)
32
(0.16)
55
(0.65)
75
(1.1)
94
(1.5)
113
(1.8)
131
(2.0)
149
(2.2)
166
(2.4)
184
(2.6)
201
(2.7)
218
(2.9)
238
(2.9)
254
(3.0)
271
(3.1)
288
(3.2)
305
(3.3)
321
(3.37)
338
(3.44)
354
(3.51)
370
(3.58)
386
(3.65)
466
(3.76)
45
(0.11)
77
(0.46)
105
(0.78)
132
(1.0)
158
(1.3)
184
(1.4)
209
(1.6)
234
(1.7)
258
(1.8)
282
(1.9)
306
(2.0)
332
(2.1)
356
(2.2)
379
(2.26)
403
(2.3)
426
(2.36)
450
(2.41)
473
(2.46)
496
(2.51)
518
(2.56)
541
(2.60)
652
(2.69)
76
(0.07)
129
(0.28)
176
(0.47)
221
(0.62)
265
(0.75)
308
(0.85)
349
(0.94)
390
(1.0)
431
(1.1)
471
(1.2)
511
(1.2)
555
(1.2)
594
(1.3)
632
(1.3)
672
(1.4)
711
(1.41)
750
(1.44)
788
(1.48)
826
(1.51)
864
(1.53)
902
(1.56)
1086
(1.61)
116
(0.04)
196
(0.18)
266
(0.31)
333
(0.41)
398
(0.51)
462
(0.57)
528
(0.62)
589
(0.67)
648
(0.72)
709
(0.77)
770
(0.80)
832
(0.83)
890
(0.86)
948
(0.89)
1007
(0.92)
1066
(0.94)
1124
(0.96)
1182
(0.98)
1239
(1.0)
1296
(1.02)
1353
(1.04)
1629
(1.08)
153
(0.03)
258
(0.14)
354
(0.23)
444
(0.32)
531
(0.37)
617
(0.42)
700
(0.47)
783
(0.51)
864
(0.54)
945
(0.58)
1025
(0.60)
1109
(0.62)
1187
(0.65)
1264
(0.67)
1343
(0.69)
1422
(0.71)
1499
(0.72)
1576
(0.74)
1652
(0.75)
1728
(0.77)
1803
(0.78)
2173
(0.807)
231
(0.02)
390
(0.09)
533
(0.15)
668
(0.20)
798
(0.25)
927
(0.28)
1054
(0.31)
1178
(0.34)
1300
(0.36)
1421
(0.38)
1541
(0.40)
1664
(0.42)
1781
(0.43)
1896
(0.44)
2015
(0.46)
2133
(0.47)
2249
(0.48)
2364
(0.49)
2478
(0.50)
2591
(0.52)
2705
(0.52)
3259
(0.538)
328
(0.02)
555
(0.06)
759
(0.11)
953
(0.14)
1140
(0.17)
1323
(0.20)
1503
(0.22)
1680
(0.24)
1854
(0.25)
2027
(0.27)
2199
(0.28)
2378
(0.29)
2544
(0.3)
2709
(0.31)
2878
(0.32)
3046
(0.33)
3212
(0.337)
3377
(0.344)
3540
(0.351)
3702
(0.358)
3864
(0.364)
4656
(0.376)
461
(0.01)
778
(0.045)
1065
(0.08)
1337
(0.1)
1599
(0.12)
1855
(0.14)
2107
(0.155)
2355
(0.17)
2599
(0.18)
2842
(0.19)
3082
(0.20)
3323
(0.21)
3562
(0.22)
3793
(0.22)
4029
(0.23)
4265
(0.235)
4497
(0.241)
4728
(0.246)
4956
(0.251)
5183
(0.256)
5410
(0.260)
6518
(0.269)
767
(0.007)
1296
(0.027)
1773
(0.045)
2226
(0.062)
2663
(0.074)
3090
(0.085)
3509
(0.093)
3922
(0.101)
4329
(0.108)
4733
(0.114)
5133
(0.12)
5546
(0.12)
5936
(0.13)
6321
(0.134)
6716
(0.138)
7108
(0.141)
7496
(0.144)
7880
(0.148)
8260
(0.151)
8638
(0.153)
9017
(0.156)
10863
(0.161)
Minimum number of samples (number of elements needed for life test × 1,000 for time)
15
1152
(0.005)
1946
(0.018)
2662
(0.031)
3341
(0.041)
3997
(0.049)
4638
(0.056)
5267
(0.052)
5886
(0.067)
6498
(0.072)
7103
(0.077)
7704
(0.080)
3319
(0.083)
8904
(0.086)
9482
(0.089)
10073
(0.092)
10662
(0.094)
11244
(0.096)
11819
(0.098)
12390
(0.100)
12957
(0.102)
13526
(0.104)
16295
(0.108)
0.2
1534
(0.003)
2592
(0.013)
3547
(0.022)
4452
(0.031)
5327
(0.037)
6181
(0.042)
7019
(0.047)
7845
(0.051)
8660
(0.054)
9468
(0.057)
10268
(0.060)
11092
(0.062)
11872
(0.065)
12643
(0.067)
13431
(0.069)
14216
(0.070)
14992
(0.072)
15759
(0.074)
16520
(0.075)
17276
(0.077)
18034
(0.078)
21726
(0.081)
0.15
0.1
2303
(0.002)
3891
(0.009)
5323
(0.015)
6681
(0.018)
7994
(0.025)
9275
(0.028)
10533
(0.031)
11771
(0.034)
12995
(0.036)
14206
(0.038)
15407
(0.040)
16638
(0.042)
17808
(0.043)
18964
(0.045)
20146
(0.046)
21324
(0.047)
22487
(0.048)
23639
(0.049)
24780
(0.050)
25914
(0.051)
27051
(0.052)
32589
(0.054)
Note 1: The number of samples is determined based on the limit of Poission’s binomial distribution exponent.
Note 2: The values shown in parentheses are reference values (approximate AQL values) for assurance of minimum quality, and these values can ensure
acceptance of 19 out of 20 lots (on the average).
25
20
19
18
17
16
15
14
13
12
11
10
9
5
(1.03)
8
(4.4)
11
(7.4)
13
(10.5)
16
(12.3)
19
(13.8)
21
(15.6)
24
(16.6)
26
(18.1)
28
(19.4)
31
(19.9)
33
(21.0)
36
(21.4)
38
(22.3)
40
(23.1)
43
(23.3)
45
(24.1)
47
(24.7)
50
(24.9)
52
(25.5)
54
(26.1)
65
(27.0)
50
Table 2.12
8
7
6
5
4
3
2
1
0
Allowable number: C
(r = c + 1)
Maximum percent
defective (LTPD) or λ
Minimum number of samples needed for test to ensure that any lot having the same percent defective
as the specified LTPD will not be accepted at the reliability rate of 90% (single sampling)
2
Reliability of Semiconductor Devices
LTPD sampling method
Source: MIL-S-19500E
T04007CE-2 2012.1 2-25
2
Reliability of Semiconductor Devices
b) How to obtain the failure rate reliability limit
When carrying out the life test of a semiconductor product, we use the failure rate (λ) or the mean time to
failure (MTTF) to evaluate the test result. The relation between λ and MTTF can be expressed as follows:
λ = 1/MTTF
The lifetime data can be always obtained from the samples having a short life, and it is difficult to check the
lives of all the samples. So, we have to end the life test in the middle of the test (refer to Sec. 2.2.5-a)).
When it is assumed that the failure distribution is the exponential distribution, the upper limit value of the
failure rate reliability is frequently used for the life test. This method is specified in JIS C 5003 “General Test
Procedure of Failure Rate for Electronic Components”. Assume that the total testing time is “T” and the
number of failures is “r”. In this case, the failure rate “λ” can be expressed as follows:
λ = r/T
Since the value “λ” is obtained from a limited number of samples, this value may fluctuate in a certain interval.
So, we cannot say that this value is always true. It is, therefore, necessary to say that the true value is in the
fluctuating interval. The probability of existence of the true value in this interval is referred to as the confidence
level. For semiconductors, the confidence level is normally set to “90%” or “60%”.
The former “λ” is referred to as a point estimation, and the latter is referred to as an interval estimation. To
obtain the latter “λ” value, we should obtain the point estimation “λ” value first, and should then multiply the
obtained “λ” value by the factor corresponding to the confidence level and the number of failures. To obtain
this factor, we should use the χ2-distribution. Table 2.13 shows the factors to be used for obtaining the result
(failure rate upper limit value λ0 (one side)).
If the number of failures is “0” (r = 0), the λ0 value can be obtained using the same formula as above:
λ0 = a/T
In this case, if the confidence level is 90%, the value “a” will be 2.30, and if the confidence level is 60%, the
value “a” will be 0.917.
Table 2.13
Interval estimation factors for confidence levels 90% and 60%
(for failure rate upper limit value λ0 (one side))
Number of failures
r
1
2
3
4
5
6
7
8
9
10
T04007CE-2 2012.1 2-26
Confidence level
60%
90%
2.02
3.89
1.55
2.66
1.39
2.23
1.31
2.00
1.85
1.26
1.22
1.76
1.20
1.68
1.18
1.62
1.16
1.58
1.54
1.15
2
Reliability of Semiconductor Devices
Example: Assume that the life test is carried out for 1 year (8,743 hours) using 1,000 semiconductor products,
and 8 failures occur during the test. Also assume that the acceleration factor is “100”, and the upper
limit confidence level is 60%. In this case, the failure rate can be obtained as follows:
T = 1000 × 8743 = 8.743 × 106(h)
r=8
Acceleration factor = 100
Factor of confidence level = 1.18
Consequently, the failure rate “λ” can be obtained as follows:
λ = (1.18 × 8)/(8.743 × 106 × 100) = 1.08 × 10−8(h−1)
2.2.7
Screening
a) Concept of screening
The reliability of electronic parts is frequently expressed by the failure rate. The dependency of the failure
rate on the time can be indicated by the bath-tub curve as shown in Figure 2.7. Failures can be classified as
the early failures, random failures, and wear-out failures. If a failure occurs relatively early after starting use,
the failure will be regarded as an early failure. If a failure occurs randomly during the relatively long period after
the early stages of use, the failure will be regarded as a random failure. If a failure occurs frequently by fatigue
or deterioration of the product or a part after long use of the product, the failure will be regarded as a wearout failure.
As shown in Figure 2.7, semiconductor products rarely cause wear-out failures, except in special cases.
We, therefore, should consider the early and random failures.
Failure rate λ (t)
General electronic device
or electronic part
Semiconductor device
Early failure
period
Random failure period
Assumed
Wear-out failure
period
Time t
Figure 2.7
Transition of failure rate
T04007CE-2 2012.1 2-27
2
Reliability of Semiconductor Devices
The main purpose of screening is to obtain high reliability by eliminating the early failures because these
failures occur at a high rate. This means that we should screen to eliminate the latent defects that may cause
deterioration very easily when a thermal stress or an electric stress is applied to the semiconductor product
as shown in Figure 2.8. However, we should carefully determine the stress application conditions so that
products having no latent defects can cause characteristic change by the applied stresses. During the random
failure period, application of thermal and electric stresses for a long time will cause gradual change in the
distribution curve as shown in the Figure. After entering the wear-out failure period, the distribution curve will
change abruptly and the failure rate will be increased rapidly. For ideal screening, therefore, it is very important
to determine the screening method after analyzing the failures. For example, failures should be analyzed to
check what types of failures occur during the early failure period and what stresses can easily cause failures.
Figure 2.9 shows the example of screening procedure.
Specified width
Initial property distribution
Distribution after applying
thermal and electric stresses
Early failure
1
Stress application time
ೋ
2
’
2‫ޓ‬
”
2‫ޓ‬
3
Figure 2.8
Change in property distribution caused by stress application
T04007CE-2 2012.1 2-28
2
Latent defect
Reliability of Semiconductor Devices
Manufacturer’s technical problem
Cause deterioration by applying stress.
Find out the cause.
Clarify the failure mechanism.
Examine the screening method.
Determine the screening method.
Check the effect.
Collect the market reliability data.
Figure 2.9
Failure analysis
Carry out screening.
Example of screening procedure
When a product is in use, its reliability depends on the reliability of the product and the reliability of the
product use conditions. This means that user factors, such as stress application by mounting, conditions for
use of the product, and environmental conditions (conditions of the place where the product is used), will
greatly affect the reliability. Regarding the screening procedure shown in Figure 2.9, therefore, the stress
application method and the screening method should be determined carefully considering these user factors.
In addition, to protect the product from unexpected stresses, such as surge, it is necessary to take stress
preventive measures very carefully.
b) Failure model and screening
Considering a semiconductor memory, for example, the semiconductor memory manufacturing process is
very complicated and delicate. So, we can find various failure factors at various stages of the semiconductor
memory manufacturing process. Examples of such factors are designing problems, manufacturing problems and
inspection problems. In addition, after delivering the products to the users, there are problems of users’
inappropriate use conditions, such as inappropriate circuits and environmental conditions. In the manufacturing
process, various stages, such as the silicon boards, dispersion, passivation, wiring, electrode, frame, package,
die bonding, wire bonding, and sealing stages, have their own factors that may cause failures. The main failure
modes that may be caused by these factors are:
Surface defect (ion contamination)
Oxide film defect (pinhole)
Metal wire defect
Diffusion layer defect
Input/output circuit defect
T04007CE-2 2012.1 2-29
2
Reliability of Semiconductor Devices
For these failure modes, the screening methods shown in Table 2.14 can be used.
Table 2.14
Failure modes and screening methods
Screening method
Failure mode
Surface defect (contamination, etc.)
Static burn-in
Oxide film defect
Dynamic burn-in, high voltage, cell stress
Input circuit deterioration
Static burn-in
Diffusion layer defect
Dynamic burn-in
Micro-crack
Temperature cycle
Contact defect
Dynamic burn-in
Electromigration
Dynamic burn-in
Corrosion (plastic)
Thermal-humidity low-loss bias
Corrosion (hermetic)
Low-temperature low-loss bias
Hot electron injection
Low-temperature operation
Among the above screening methods, the most effective method is “burn-in”. This method carries out
screening at around 125°C. In addition to the temperature and the time, the drive circuit is important for burnin. Use of static burn-in can eliminate surface defects, such as increase in leakage current, deterioration of
operation speed, and fluctuation of threshold voltage. On the other hand, use of dynamic burn-in can eliminate
memory cell defects caused by weak oxide films, contact defects, dispersion defect, etc. Table 2.15 shows
the main screening methods and their effects.
T04007CE-2 2012.1 2-30
2
Table 2.15
Mechanical stress
Thermal stress
Method
Cost
Application
Good
Very
economical
Effective method
Effective in stabilization. However, there
are cases in which the other method is
used for recovering from the failure mode.
Detection item
Good
Very
economical
Effective method
Effective in screening of problems in the
connected area.
Good
Economical
This method has an effect similar to that
of the temperature cycle method. The
stress level is high.
Shape of internal lead
Die bonding, wire bonding
Silicon (Crack)
Good
Medium
Variable frequency
vibration
(Without monitoring)
Package
Die bonding, wire bonding
Silicon (Crack)
Rather good
Expensive
Random vibration
(Without monitoring)
Foreign material
Internal lead (Shape)
Internal lead (Partial disconnection)
Good
Expensive
Variable frequency
vibration
(With monitoring)
Foreign material
Internal lead (Shape)
Internal lead (Partial disconnection)
Good
The effect on foreign materials depends
Very expensive on the foreign material type.
Random vibration
(With monitoring)
Foreign material
Internal lead (Shape)
Internal lead (Partial disconnection)
Good
Very expensive
Foreign material
Rather good
Expensive
Foreign material
Internal lead (Shape)
Rather bad
Medium
Intermittent operation
Metallization
Oxide film
Contamination
Inversion channel
Drift
Good
Expensive
AC operation
Metallization
Oxide film
Contamination
Inversion channel
Drift
Very good
Expensive
DC operation
Metallization
Oxide film
Contamination
Inversion channel
Drift
Good
Expensive
High-temperature
AC operation
Metallization
Oxide film
Contamination
Inversion channel
Drift
High-temperature
reversed bias
Inversion channel
High-temperature
storage
Temperature cycle
Airtightness of package
Wire bonding, die bonding
Silicon (Crack)
Thermal defect of connected area
Thermal shock
Airtightness of package
Die bonding, wire bonding
Silicon (Crack)
Thermal defect of connected area
Constant acceleration
Shock
Electric stress
Comparison of screening methods
Electric stability
Metallization
Silicon
Corrosion
Vibration noise
Fine leakage
Others
Reliability of Semiconductor Devices
Airtightness of package
Effect
Effective for high-density mounting.
Suitable for electrical equipment and
aviation fields.
Suitable for the parts of space equipment.
Most expensive method
This method has high costs, but is not so
effective.
This method is worse than the constant
acceleration method.
Since temperature can promote failure
modes, raising the temperature will be
Extremely good Very expensive more effective.
Rather bad
Expensive
Good
Medium
Gross leakage
Airtightness of package
Good
Economical
X-ray fluoroscopy
Die bonding
Lead shape
Airtightness of package
Foreign material
Contamination
Good
Medium
1.013 × 10
−5
Pa ml/s
−1
1.013 × 10 ml/s
Effective on resin molded products.
T04007CE-2 2012.1 2-31
2
Reliability of Semiconductor Devices
c) Practical use of screening
We carry out screening as described before. However, we should determine the quality that justifies the cost,
considering the features of the product, package, and process, before practically carrying out screening. So,
the screening method depends on the product type. Table 2.16 shows an example of the screening processes
practically adopted for plastic packages and ceramic packages.
Table 2.16
Examples of screening processes
Plastic package
Ceramic package
Optical visual inspection of the inside
‫↓ޓޓ‬
Die bonding, wire bonding
‫↓ޓޓ‬
Visual inspection of the inside before sealing
‫↓ޓޓ‬
Sealing, lead frame cutting, bending
‫↓ޓޓ‬
Surge application test
‫↓ޓޓ‬
Electric test
‫↓ޓޓ‬
High-temperature dynamic burn-in
‫↓ޓޓ‬
High-voltage stress test
‫↓ޓޓ‬
High-temperature final test
‫↓ޓޓ‬
Quality assurance inspection
Dicing
‫↓ޓޓ‬
Pre-forming
‫↓ޓޓ‬
Alloy mounting
‫↓ޓޓ‬
Ultrasonic or thermocompression bonding
‫↓ޓޓ‬
Pre-sealing inspection
‫↓ޓޓ‬
Sealing
‫↓ޓޓ‬
Temperature cycle (5 cycles, −65°C to 150°C)
‫↓ޓޓ‬
5
2
Centrifugal acceleration (1.96 × 10 m/s , Y1 direction)
‫↓ޓޓ‬
Sn plating
‫↓ޓޓ‬
Fine-leakage (1.013 × 10−2 Pa ml/s)
‫↓ޓޓ‬
Gross leakage (C2 modified)
‫↓ޓޓ‬
Lead frame cutting
‫↓ޓޓ‬
High-temperature high-voltage dynamic burn-in
‫↓ޓޓ‬
High-temperature final test
‫↓ޓޓ‬
Quality assurance inspection
d) Cautions for screening
Before starting screening, be sure to observe the following cautions:
1) Since the purpose of screening is to detect latent failures quickly, testing should be performed under
considerably strict conditions. Therefore, if the test conditions are not appropriate, conforming devices
may be damaged, or applied stresses may remain in conforming devices. As a result, reliability may be
deteriorated.
T04007CE-2 2012.1 2-32
2
Reliability of Semiconductor Devices
For example,
(a) A high pulse voltage should be applied to carry out electrostatic destruction screening. If this voltage
exceeds 70% of the withstand voltage of the device, the stress may remain in the device.
(b)If a plastic package product is exposed to a high temperature of 150°C or more, the product may be
deteriorated.
If the junction temperature is too high, the product may be deteriorated.
It is very important that the test conditions should be determined after thorough discussion with the
manufacturer.
2) The failure rate, temperature acceleration factor, and percent defective may fluctuate depending on the
electric power consumption.
3) The screening method should be carefully selected for each package type.
In addition, when adopting the screening test or determining the screening conditions, we should always
remember that screening is not an infallible method.
This means that the screening test is convenient because it can be started easily and immediately.
However, it is recommended that the screening test should be adopted as a temporary measure, for the
following reasons:
(a) It is important to investigate the causes of failures to improve the reliability. Screening, however, cannot
improve the reliability.
(b)Screening the finished products will result in higher cost because such screening requires both the
screening cost and the defective product cost.
(c) If a stress is applied by screening, the applied stress may deteriorate the conforming products. If the
failure occurrence frequency shows a completely separated two-peak distribution as shown in Figure
2.10-a), the conforming products may not be deteriorated. However, if the failure occurrence frequency
shows a one-peak distribution or an incompletely separated two-peak distribution, as shown in Figure
2.10-b) and Figure 2.10-c), the conforming products may be deteriorated.
a) Completely separated
b) One-peak distribution
c) Incompletely separated
Stress strength
Screening level
Failure occurrence
frequency
Screening level
two-peak distribution
Failure occurrence
frequency
Screening level
Failure occurrence
frequency
two-peak distribution
Stress strength
Figure 2.10
Stress strength
Failure distribution and screening level
T04007CE-2 2012.1 2-33
2
Reliability of Semiconductor Devices
Reference documents:
2.1) Ajiki, “Reliability Engineering for Semiconductor Devices”, Union of Japanese Scientists and Engineers,
pp. 44-46.
2.2) Ajiki, “Reliability Engineering for Semiconductor Devices”, Union of Japanese Scientists and Engineers,
pp. 23-26.
2.3) Wada, “Improvement of design reliability for miniaturization process”, National Technical Report, Vol.
36, No. 4, pp. 493-500 (1990).
2.4) F. N. Sinnadurai, “The accelerated aging of plastic encapsulated semiconductor devices in environments
containing a high vapour pressure of water”, Microelectronics and Reliability, Vol. 13, p. 23 (1974).
2.5) Maeda et al., “Property change in moisture resistance test”, 16th JUSE Symposium on Reliability and
Maintainability, p. 217 (1986).
2.6) N. Lycoudes, “The reliability of plastic microcircuit in moist environments”, Solid State Technology, p.
53, (October 1978).
2.7) Suzuki et al., “Acceleration of resin mold IC in pressure cooker test”, Technical Research Report of
Institute of Electronics, Information and Communication Engineers, R79-57, p. 83 (1980).
T04007CE-2 2012.1 2-34
Download
Related flashcards
Create Flashcards