Classic
EPLD Family
®
May 1999, ver. 5
Features
Data Sheet
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■
■
■
■
■
■
■
■
■
Complete device family with logic densities of 300 to 900 usable gates
(see Table 1)
Device erasure and reprogramming with non-volatile EPROM
configuration elements
Fast pin-to-pin logic delays as low as 10 ns and counter frequencies
as high as 100 MHz
24 to 68 pins available in dual in-line package (DIP), plastic J-lead
chip carrier (PLCC), pin-grid array (PGA), and small-outline
integrated circuit (SOIC) packages
Programmable security bit for protection of proprietary designs
100% generically tested to provide 100% programming yield
Programmable registers providing D, T, JK, and SR flipflops with
individual clear and clock controls
Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, IBM RISC System/6000
workstations, and third-party development systems
Programming support with Altera’s Master Programming Unit
(MPU); programming hardware from Data I/O, BP Microsystems,
and other third-party programming vendors
Additional design entry and simulation support provided by EDIF,
library of parameterized modules (LPM), Verilog HDL, VHDL, and
other interfaces to popular EDA tools from manufacturers such as
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,
Synplicity, and VeriBest
Table 1. Classic Device Features
Feature
Altera Corporation
A-DS-CLASSIC-05
EP610
EP610I
EP910
EP910I
EP1810
Usable gates
300
450
900
Macrocells
16
24
48
Maximum user I/O pins
22
38
64
t PD (ns)
10
12
20
f CNT (MHz)
100
76.9
50
745
Classic EPLD Family Data Sheet
General
Description
The Altera ClassicTM device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology,
Classic devices also have a Turbo-only version, which is described in this
data sheet.
Classic devices support 100% TTL emulation and can easily integrate
multiple PAL- and GAL-type devices with densities ranging from 300 to
900 usable gates. The Classic family provides pin-to-pin logic delays as
low as 10 ns and counter frequencies as high as 100 MHz. Classic devices
are available in a wide range of packages, including ceramic dual in-line
package (CerDIP), plastic dual in-line package (PDIP), plastic J-lead chip
carrier (PLCC), ceramic J-lead chip carrier (JLCC), pin-grid array (PGA),
and small-outline integrated circuit (SOIC) packages.
EPROM-based Classic devices can reduce active power consumption
without sacrificing performance. This reduced power consumption
makes the Classic family well suited for a wide range of low-power
applications.
Classic devices are 100% generically tested devices in windowed
packages and can be erased with ultra-violet (UV) light, allowing design
changes to be implemented quickly.
Classic devices use sum-of-products logic and a programmable register.
The sum-of-products logic provides a programmable-AND/fixed-OR
structure that can implement logic with up to eight product terms. The
programmable register can be individually programmed for D, T, SR, or
JK flipflop operation or can be bypassed for combinatorial operation. In
addition, macrocell registers can be individually clocked either by a global
clock or by any input or feedback path to the AND array. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to implement a variety of logic functions simultaneously.
Classic devices are supported by Altera’s MAX+PLUS II development
system, a single, integrated package that offers schematic, text—including
VHDL, Verilog HDL, and the Altera Hardware Description Language
(AHDL)—and waveform design entry, compilation and logic synthesis,
simulation and timing analysis, and device programming. The
MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL,
Verilog HDL, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and workstationbased EDA tools. The MAX+PLUS II software runs on Windows-based
PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations. These devices also contain on-board logic test
circuitry to allow verification of function and AC specifications during
standard production flow.
746
Altera Corporation
Classic EPLD Family Data Sheet
f
Functional
Description
For more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet.
The Classic architecture includes the following elements:
■
■
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■
Macrocells
Programmable registers
Output enable/clock select
Feedback select
Macrocells
Classic macrocells, shown in Figure 1, can be individually configured for
both sequential and combinatorial logic operation. Eight product terms
form a programmable-AND array that feeds an OR gate for combinatorial
logic implementation. An additional product term is used for
asynchronous clear control of the internal register; another product term
implements either an output enable or a logic-array-generated clock.
Inputs to the programmable-AND array come from both the true and
complement signals of the dedicated inputs, feedbacks from I/O pins that
are configured as inputs, and feedbacks from macrocell outputs. Signals
from dedicated inputs are globally routed and can feed the inputs of all
device macrocells. The feedback multiplexer controls the routing of
feedback signals from macrocells and from I/O pins. For additional
information on feedback select configurations, see Figure 3 on page 749.
Figure 1. Classic Device Macrocell
Logic Array
Global
Clock
VCC
Output Enable/Clock Select
OE
CLK
Q
CLR
Programmable
Register
Input, I/O, and
Macrocell
Feedbacks
Altera Corporation
To Logic Array
Feedback
Select
Asynchronous Clear
747
Classic EPLD Family Data Sheet
The eight product terms of the programmable-AND array feed the 8-input
OR gate, which then feeds one input to an XOR gate. The other input to the
XOR gate is connected to a programmable bit that allows the array output
to be inverted. Altera’s MAX+PLUS II software uses the XOR gate to
implement either active-high or active-low logic, or De Morgan’s
inversion to reduce the number of product terms needed to implement a
function.
Programmable Registers
To implement registered functions, each macrocell register can be
individually programmed for D, T, JK, or SR operation. If necessary, the
register can be bypassed for combinatorial operation. During design
compilation, the MAX+PLUS II software selects the most efficient register
operation for each registered function to minimize the logic resources
needed by the design. Registers have an individual asynchronous clear
function that is controlled by a dedicated product term. These registers
are cleared automatically during power-up.
In addition, macrocell registers can be individually clocked by either a
global clock or any input or feedback path to the AND array. Altera’s
proprietary programmable I/O architecture allows the designer to
program output and feedback paths for combinatorial or registered
operation in both active-high and active-low modes. These features make
it possible to simultaneously implement a variety of logic functions.
Output Enable/Clock Select
Figure 2 shows the two operating modes (Modes 0 and 1) provided by the
output enable/clock (OE/CLK) select. The OE/CLK select, which is
controlled by a single programmable bit, can be individually configured
for each macrocell. In Mode 0, the tri-state output buffer is controlled by
a single product term. If the output enable is high, the output buffer is
enabled. If the output enable is low, the output has a high-impedance
value. In Mode 0, the macrocell flipflop is clocked by its global clock input
signal.
In Mode 1, the output enable buffer is always enabled, and the macrocell
register can be triggered by an array clock signal generated by a product
term. This mode allows registers to be individually clocked by any signal
on the AND array. With both true and complement signals in the AND array,
the register can be configured to trigger on a rising or falling edge. This
product-term-controlled clock configuration also supports gated clock
structures.
748
Altera Corporation
Classic EPLD Family Data Sheet
Figure 2. Classic Output Enable/Clock Select
Mode 0
Global
Clock
In Mode 0, the register
is clocked by the global
clock signal. The
output is enabled by
the logic from the
product term.
Output Enable/Clock
Select
VCC
OE
AND
Array
CLK
Data
Q
OE = Product Term
CLK = Global
Macrocell
Output Buffer
CLR
Mode 1
Global
Clock
In Mode 1, the output
AND
is permanently enabled
Array
and the register is
clocked by the product
term, which allows
gated clocks to be
generated.
OE = Enabled
Output Enable/Clock
Select
VCC
OE
CLK
Data
CLK = Product Term
Q
CLR
Macrocell
Output Buffer
Feedback Select
Each macrocell in a Classic device provides feedback selection that is
controlled by the feedback multiplexer. This feedback selection allows the
designer to feed either the macrocell output or the I/O pin input
associated with the macrocell back into the AND array. The macrocell
output can be either the Q output of the programmable register or the
combinatorial output of the macrocell. Different devices have different
feedback multiplexer configurations. See Figure 3.
Figure 3. Classic Feedback Multiplexer Configurations
Global Feedback Multiplexer
Q
Global
I/O
EP610
EP610I
EP910
EP910I
Altera Corporation
Quadrant Feedback Multiplexer
Q
Quadrant
I/O
EP1810
Dual Feedback Multiplexer
Quadrant
Q
Global
I/O
EP1810
749
Classic EPLD Family Data Sheet
EP610, EP610I, EP910, and EP910I devices have a global feedback
configuration; either the macrocell output (Q) or the I/O pin input (I/O)
can feed back to the AND array so that it is accessible to all other
macrocells.
EP1810 macrocells can have either of two feedback configurations:
quadrant or dual. Most macrocells in EP1810 devices have a quadrant
feedback configuration; either the macrocell output or I/O pin input can
feed back to other macrocells in the same quadrant. Selected macrocells in
EP1810 devices have a dual feedback configuration: the output of the
macrocell feeds back to other macrocells in the same quadrant, and the
I/O pin input feeds back to all macrocells in the device. If the associated
I/O pin is not used, the macrocell output can optionally feed all
macrocells in the device. In this case, the output of the macrocell passes
through the tri-state buffer and uses the feedback path between the buffer
and the I/O pin.
Design Security
Classic devices contain a programmable security bit that controls access to
the data programmed into the device. When this bit is programmed, a
proprietary design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security because
data within configuration elements is invisible. The security bit that
controls this function and other program data is reset only when the
device is erased.
Timing Model
Device timing can be analyzed with the MAX+PLUS II software, with a
variety of popular industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 4. Devices have fixed
internal delays that allow the user to determine the worst-case timing for
any design. The MAX+PLUS II software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for systemlevel performance evaluation.
Figure 4. Classic Timing Model
Global Clock
Delay
tICS
Input
Delay
tIN
Array Clock
Delay
tIC
Register
tSU
tH
Logic Array
Delay
tLAD
tCLR
I/O
Delay
tIO
750
Output
Delay
tOD
tXZ
tZX
Feedback
Delay
tFD
Altera Corporation
Classic EPLD Family Data Sheet
Timing information can be derived from the timing model and
parameters for a particular device. External timing parameters represent
pin-to-pin timing delays, and can be calculated from the sum of internal
parameters. Figure 5 shows the internal timing relationship for internal
and external delay parameters.
f
Altera Corporation
For more information on device timing, refer to Application Note 78
(Understanding MAX 5000 & Classic Timing) in this data book.
751
Classic EPLD Family Data Sheet
Figure 5. Classic Switching Waveforms
t R and t F < 3 ns.
Inputs are driven at 3 V
for a logic high and
0 V for a logic low.
All timing characteristics
are measured at 1.5 V.
Input Mode
tPD1 = tIN + tLAD + tOD
tPD2 = tIO + tIN + tLAD + tOD
tIO
I/O Pin
tIN
Input Pin
tLAD
Logic Array Input
tCLR
Logic Array Output
tOD
Output Pin
Global Clock Mode
tCH
tR
tCL
tF
Global Clock Pin
tIN
tICS
tSU
tH
Global Clock at Register
Data from Logic Array
Array Clock Mode
tR
tACH
tACL
tF
Clock Pin
tIN
Clock into Logic Array
tIC
Clock from Logic Array
tASU
tAH
Data from Logic Array
tFD
Register Output to Logic Array
Output Mode
Clock from Logic Array
tOD
Data from Logic Array
tXZ
tZX
Output Pin
High-Impedance
Tri-State
752
Altera Corporation
Classic EPLD Family Data Sheet
Turbo Bit
Option
Many Classic devices contain a programmable Turbo BitTM option to
control the automatic power-down feature that enables the low-standbypower mode. When the Turbo Bit option is turned on, the low-standbypower mode is disabled. All AC values are tested with the Turbo Bit
option turned on. When the device is operating with the Turbo Bit option
turned off (non-Turbo mode), a non-Turbo adder must be added to the
appropriate AC parameter to determine worst-case timing. The nonTurbo adder is specified in the “AC Operating Conditions” tables for each
Classic device that supports the Turbo mode.
Generic Testing
Classic devices are fully functionally tested. Complete testing of each
programmable EPROM configuration element and all internal logic
elements before and after packaging ensures 100% programming yield.
See Figure 6 for AC test measurement conditions. These devices also
contain on-board logic test circuitry to allow verification of function and
AC specifications during standard production flow.
Figure 6. AC Test Conditions
Power-supply transients can affect AC
measurements. Simultaneous transitions of
R1
multiple outputs should be avoided for
885 Ω
accurate measurement. Threshold tests
Device
must not be performed under AC
conditions. Large-amplitude, fast ground- Output
current transients normally occur as the
device outputs discharge the load
R2
capacitances. When these transients flow
340 Ω
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in observable
noise immunity can result.
Device
Programming
VCC
To Test
System
C1 (includes
JIG capacitance)
Classic devices can be programmed on 486- and Pentium-based PCs with
the MAX+PLUS II Programmer, an Altera Logic Programmer card, the
MPU, and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
Data I/O, BP Microsystems, and other programming hardware
manufacturers also offer programming support for Altera devices. See
Programming Hardware Manufacturers for more information.
Altera Corporation
753
Notes:
EP610 EPLD
Features
■
■
■
■
■
■
High-performance, 16-macrocell Classic EPLD
– Combinatorial speeds with tPD as fast as 10 ns
–
Counter frequencies of up to 100 MHz
–
Pipelined data rates of up to 125 MHz
Programmable I/O architecture with up to 20 inputs or 16 outputs
and 2 clock pins
EP610 and EP610I devices are pin-, function-, and programming
file-compatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see Figure 7):
– 24-pin small-outline integrated circuit (plastic SOIC only)
– 24-pin ceramic and plastic dual in-line package (CerDIP and
PDIP)
– 28-pin plastic J-lead chip carrier (PLCC)
Figure 7. EP610 Package Pin-Out Diagrams
19
7
8
9
18
17
16
10
15
11
14
12
13
INPUT
1
21
I/O
I/O
5
26
25
I/O
I/O
5
20
I/O
I/O
6
24
I/O
I/O
6
19
I/O
I/O
7
23
I/O
I/O
8
22
I/O
9
21
I/O
I/O
I/O
7
8
18
17
I/O
I/O
28
27
EP610
I/O
9
16
I/O
I/O
I/O
10
15
I/O
I/O
10
20
I/O
INPUT
11
14
INPUT
NC
11
19
NC
GND
12
13
CLK2
12
13
14
15
16
17
18
24-Pin SOIC
24-Pin DIP
28-Pin PLCC
EP610
EP610
EP610I
EP610
EP610I
Altera Corporation
I/O
4
VCC
I/O
I/O
I/O
6
2
22
INPUT
20
VCC
5
3
3
CLK2
21
CLK1
4
4
INPUT
I/O
GND
22
INPUT
3
VCC
23
GND
23
24
2
I/O
2
VCC
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
CLK2
1
INPUT
24
CLK1
INPUT
EP610
1
EP610
CLK1
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
GND
I/O
Package outlines not drawn to scale. Windows in ceramic packages only.
755
Classic EPLD Family Data Sheet
General
Description
EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins,
and 2 global clock pins (see Figure 8). Each macrocell can access signals
from the global bus, which consists of the true and complement forms of
the dedicated inputs and the true and complement forms of either the
output of the macrocell or the I/O input. The CLK1 signal is a dedicated
global clock input for the registers in macrocells 9 through 16. The CLK2
signal is a dedicated global clock input for registers in macrocells 1
through 8.
Figure 8. EP610 Block Diagram
Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages.
2 (3)
INPUT
1 (2)
CLK1
11 (13)
3
(4)
4
(5)
5
(6)
6
(7)
7
(8)
8
(9)
9
(10)
10
(12)
INPUT (27) 23
CLK2
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Global
Bus
(16) 13
(26)
22
(25)
21
(24)
20
(23)
19
(22)
18
(21)
17
(20)
16
(18)
15
INPUT (17) 14
INPUT
Figure 9 shows the typical supply current (ICC) versus frequency of EP610
devices.
Figure 9. ICC vs. Frequency of EP610 Devices
100
Turbo
10
Typical ICC
Active (mA)
1.0
VCC = 5.0 V
TA = 25° C
Non-Turbo
0.1
1 kHz
10 kHz 100 kHz 1 MHz 10 MHz 80 MHz
Frequency
756
Altera Corporation
Classic EPLD Family Data Sheet
Figure 10 shows the typical output drive characteristics of EP610 devices.
Figure 10. Output Drive Characteristics of EP610 Devices
Drive characteristics may exceed shown curves.
EP610-15 & EP610-20 EPLDs
EP610-25, EP610-30 & EP610-35 EPLDs
200
80
Typical ICC
Output
Current (mA)
IOL
IOL
150
60
Typical ICC
Output
Current (mA)
VCC = 5.0 V
TA = 25° C
100
VCC = 5.0 V
TA = 25° C
40
IOH
50
20
IOH
0.45
1
2
3
4
5
VO Output Voltage (V)
0.45 1
2
3
4
5
VO Output Voltage (V)
EP610I EPLDs
100
80
IOL
Typical ICC
Output
Current (mA)
60
VCC = 5.0 V
TA = 25° C
40
IOH
20
1
2
3
4
5
VO Output Voltage (V)
Altera Corporation
757
Classic EPLD Family Data Sheet
Operating
Conditions
Tables 2 through 7 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP610 and EP610I devices.
Table 2. EP610 & EP610I Device Absolute Maximum Ratings
Symbol
Parameter
VCC
Supply voltage
Notes (1), (2)
Conditions
EP610
With respect to ground (3)
EP610I
Unit
Min
Max
Min
Max
–2.0
7.0
–2.0
7.0
–0.5
VCC + 0.5
VI
DC input voltage
–2.0
7.0
IMAX
DC VCC or ground current
–175
175
V
V
mA
IOUT
DC output current, per pin
–25
25
TSTG
Storage temperature
No bias
–65
150
–65
150
TAMB
Ambient temperature
Under bias
–65
135
–65
135
°C
TJ
Junction temperature
Ceramic packages, under
bias
150
150
°C
Plastic packages, under bias
135
135
°C
Table 3. EP610 & EP610I Device Recommended Operating Conditions
Symbol
Parameter
Conditions
Supply voltage
VI
Input voltage
(4)
°C
Note (2)
EP610
Min
VCC
mA
EP610I
Max
4.75 (4.5) 5.25 (5.5)
Min
Unit
Max
4.75
5.25
V
–0.3
VCC + 0.3
–0.3
V CC + 0.3
V
0
VCC
0
V CC
V
0
70
0
70
°C
85
–40
VO
Output voltage
TA
Operating temperature
For commercial use
85
°C
tR
Input rise time
(5)
100 (50)
500
ns
tF
Input fall time
(5)
100 (50)
500
ns
Unit
For industrial use
–40
Table 4. EP610 & EP610I Device DC Operating Conditions
Symbol
Parameter
Note (6)
Min
Max
VIH
High-level input voltage
Conditions
2.0
VCC + 0.3
V
VIL
Low-level input voltage
–0.3
0.8
V
High-level TTL output voltage
IOH = –4 mA DC (7)
2.4
High-level CMOS output voltage
IOH = –0.6 mA DC (7), (8)
3.84
VOL
Low-level output voltage
IOL = 4 mA DC (7)
II
I/O pin leakage current of dedicated input VI = VCC or ground
pins
IOZ
Tri-state output leakage current
VOH
758
VO = VCC or ground
V
V
0.45
V
–10
10
µA
–10
10
µA
Altera Corporation
Classic EPLD Family Data Sheet
Table 5. EP610 & EP610I Device Capacitance
Symbol
Parameter
Note (9)
Conditions
EP610-15
EP610-20
EP610-25
EP610-30
EP610-35
Min
Min
Max
Max
EP610I
Min
Unit
Max
CIN
Input pin capacitance
VIN = 0 V, f = 1.0 MHz
10
20
8
pF
CI/O
I/O pin capacitance
VOUT = 0 V, f = 1.0 MHz
12
20
8
pF
CCLK1
CLK1 pin capacitance
VIN = 0 V, f = 1.0 MHz
20
20
10
pF
CCLK2
CLK2 pin capacitance
VIN = 0 V, f = 1.0 MHz
20
50
12
pF
Table 6. EP610 Device ICC Supply Current
Symbol
Parameter
Notes (2), (10)
Conditions
Speed
Grade
EP610
Min
Unit
Typ
Max
ICC1
VCC supply current
(non-Turbo, standby)
VI = VCC or ground, no load
(11), (12)
20
150
µA
ICC2
VCC supply current
(non-Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (11), (12)
5
10 (15)
mA
ICC3
VCC supply current
(Turbo, active)
VI = VCC or ground, no load, -15, -20
f = 1.0 MHz (12)
-25, -30,
-35
60
90 (115)
mA
45
60 (75)
mA
Table 7. EP610I Device ICC Supply Current
Note (10)
Symbol
Conditions
Parameter
EP610I
Min
Unit
Typ
Max
ICC1
VCC supply current
(non-Turbo, standby)
VI = VCC or ground, no load,
(11), (12)
20
150
µA
ICC2
VCC supply current
(non-Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (11), (12)
3
8
mA
ICC3
VCC supply current
(Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (12)
65
105
mA
Altera Corporation
759
Classic EPLD Family Data Sheet
Notes to tables:
(1)
(2)
(3)
See the Operating Requirements for Altera Devices Data Sheet in this data book.
Numbers in parentheses are for industrial-temperature-range devices.
The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP610) or
–0.5 V (EP610I) or overshoot to 7.0 V (EP610) or VCC + 0.5 V (EP610I) for input currents less than 100 mA and periods
less than 20 ns.
(4) For EP610 devices, maximum VCC rise time is 50 ms. For EP610I devices, maximum VCC rise time is unlimited with
monotonic rise.
(5) For EP610-15 and EP610-20 devices: tR and tF = 40 ns.
For EP610-15 and EP610-20 clocks: tR and tF = 20 ns.
(6) These values are specified in Table 3 on page 758.
(7) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(8) This parameter does not apply to EP610I devices.
(9) The device capacitance is measured at 25° C and is sample-tested only.
(10) Typical values are for TA = 25° C and VCC = 5 V.
(11) When the Turbo Bit option is not set (non-Turbo mode), EP610 devices enter standby mode if no logic transitions
occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP610I devices enter standby mode if
no logic transitions occur for 75 ns after the last transition.
(12) Measured with a device programmed as a 16-bit counter.
760
Altera Corporation
Classic EPLD Family Data Sheet
Tables 8 and 9 show the timing parameters for EP610-15 and EP610-20
devices.
Table 8. EP610-15 & EP610-20 External Timing Parameters
Symbol
Parameter
Conditions
Notes (1), (2)
EP610-15
EP610-20
Min Max Min Max
Non-Turbo
Adder
Unit
(3)
tPD1
Input to non-registered output
C1 = 35 pF
15.0
20.0
20.0
ns
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
17.0
22.0
20.0
tPZX
Input to output enable
C1 = 35 pF
15.0
20.0
20.0
ns
tPXZ
Input to output disable
C1 = 5 pF (4)
15.0
20.0
20.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
20.0
fMAX
Maximum clock frequency
(5)
tSU
tH
20.0
ns
83.3
15.0
62.5
0.0
MHz
Global clock input setup time
9.0
11.0
20.0
ns
Global clock input hold time
0.0
0.0
0.0
ns
tCH
Global clock high time
6.0
8.0
0.0
ns
tCL
Global clock low time
6.0
8.0
0.0
ns
tCO1
Global clock to output delay
13.0
0.0
ns
tCNT
Global clock minimum period
16.0
fCNT
Maximum internal global clock
frequency
tASU
Array clock input setup time
tAH
Array clock input hold time
tACH
Array clock high time
tACL
Array clock low time
tODH
Output data hold time after clock
11.0
12.0
(6)
0.0
ns
62.5
0.0
MHz
6.0
8.0
20.0
ns
6.0
8.0
0.0
ns
7.0
9.0
0.0
ns
7.0
9.0
0.0
ns
1.0
1.0
1.0
ns
83.3
C1 = 35 pF (7)
tACO1
Array clock to output delay
15.0
20.0
20.0
ns
tACNT
Array clock minimum period
14.0
18.0
0.0
ns
fACNT
Array clock internal maximum
frequency
0.0
MHz
(6)
71.4
55.6
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 1 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20
Unit
Min Max Min Max
tIN
Input pad and buffer delay
4.0
4.0
tIO
I/O input pad and buffer delay
2.0
2.0
ns
tLAD
Logic array delay
6.0
11.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
5.0
5.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
5.0
5.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
5.0
5.0
ns
Altera Corporation
ns
761
Classic EPLD Family Data Sheet
Table 9. EP610-15 & EP610-20 Internal Timing Parameters (Part 2 of 2)
Symbol
Parameter
Conditions
EP610-15 EP610-20
Unit
Min Max Min Max
tSU
Register setup time
5.0
4.0
ns
tH
Register hold time
4.0
7.0
ns
tIC
Array clock delay
6.0
11.0
ns
tICS
Global clock delay
2.0
4.0
ns
tFD
Feedback delay
1.0
1.0
ns
tCLR
Register clear time
6.0
11.0
ns
Tables 10 and 11 show the timing parameters for EP610-25, EP610-30 and
EP610-35 devices.
Table 10. EP610-25, EP610-30 & EP610-35 External Timing Parameters
Symbol
Parameter
Conditions
EP610-25
EP610-30
Notes (1), (2)
EP610-35 Non-Turbo Unit
Adder
Min Max Min Max Min Max
C1 = 35 pF
(3)
tPD1
Input to non-registered output
25.0
30.0
35.0
30.0
tPD2
I/O input to non-registered output
27.0
32.0
37.0
30.0
ns
tPZX
Input to output enable
25.0
30.0
35.0
30.0
ns
tPXZ
Input to output disable
25.0
30.0
35.0
30.0
ns
37.0
C1 = 5 pF (4)
tCLR
Asynchronous output clear time
C1 = 35 pF
fMAX
Maximum frequency
(5)
27.0
32.0
ns
30.0
ns
47.6
41.7
37.0
0.0
MHz
ns
tSU
Global clock input setup time
21.0
24.0
27.0
30.0
tH
Global clock input hold time
0.0
0.0
0.0
0.0
ns
tCH
Global clock high time
10.0
11.0
12.0
0.0
ns
tCL
Global clock low time
10.0
tCO1
Global clock to output delay
11.0
15.0
12.0
17.0
tCNT
Global clock minimum period
fCNT
Maximum internal global clock
frequency
tASU
Array clock input setup time
8.0
tAH
Array clock input hold time
12.0
tACH
Array clock high time
10.0
tACL
Array clock low time
10.0
tODH
Output data hold time after clock
1.0
tACO1
Array clock to output delay
27.0
32.0
tACNT
Array clock minimum period
25.0
30.0
fACNT
Maximum internal global clock
frequency
762
25.0
(6)
C1 = 35 pF (7)
(6)
40.0
40.0
30.0
0.0
ns
20.0
0.0
ns
35.0
0.0
ns
28.6
0.0
MHz
8.0
8.0
30.0
ns
12.0
12.0
0.0
ns
11.0
12.0
0.0
ns
11.0
12.0
0.0
ns
1.0
1.0
37.0
30.0
ns
35.0
0.0
ns
0.0
MHz
33.3
33.3
28.6
ns
Altera Corporation
Classic EPLD Family Data Sheet
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
Symbol
Parameter
Condition
EP610-25
Min
Max
EP610-30
Min
Max
EP610-35
Min
Unit
Max
tIN
Input pad and buffer delay
8.0
9.0
11.0
ns
tIO
I/O input pad and buffer delay
2.0
2.0
2.0
ns
tLAD
Logic array delay
11.0
14.0
15.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
6.0
7.0
9.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
6.0
7.0
9.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
6.0
7.0
9.0
ns
tSU
Register setup time
11.0
11.0
12.0
tH
Register hold time
10.0
10.0
10.0
tIC
Array clock delay
13.0
16.0
17.0
ns
tICS
Global clock delay
1.0
1.0
0.0
ns
tFD
Feedback delay
tCLR
Register clear time
ns
ns
3.0
5.0
8.0
ns
13.0
16.0
17.0
ns
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
These values are specified in Table 3 on page 758.
See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Sample-tested only for an output change of 500 mV.
The fMAX values represent the highest frequency for pipelined data.
Measured with a device programmed as a 16-bit counter.
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Altera Corporation
763
Classic EPLD Family Data Sheet
Tables 12 and 13 show the timing parameters for EP610I devices.
Table 12. EP610I External Timing Parameters
Symbol
Parameter
Notes (1), (2)
Conditions EP610I-10 EP610I-12 EP610I-15
Min Max Min Max Min Max
C1 = 35 pF
Input to non-registered output
tPD2
I/O input to non-registered output
10.0
12.0
15.0
25.0
ns
tPZX
Input to output enable
15.0
15.0
18.0
25.0
ns
tPXZ
Input to output disable
C1 = 5 pF (4)
13.0
15.0
18.0
25.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
13.0
15.0
18.0
25.0
ns
fMAX
Maximum frequency
(5)
0.0
MHz
tSU
Global clock input setup time
tH
Global clock input hold time
tCH
Global clock high time
tCL
Global clock low time
tCO1
Global clock to output delay
6.5
8.0
8.0
0.0
ns
tCNT
Global clock minimum period
10.0
12.0
15.0
25.0
ns
fCNT
Maximum internal global clock
frequency
125.0
12.0
15.0
(3)
tPD1
(6)
10.0
Non-Turbo Unit
Adder
25.0
ns
100.
0
83.3
7.0
9.0
12.0
25
ns
0.0
0.0
0.0
0.0
ns
5.0
5.0
5.0
0.0
ns
5.0
5.0
5.0
0.0
ns
100.0
83.3
66.0
0.0
MHz
tASU
Array clock input setup time
1.5
3.0
4.0
25.0
ns
tAH
Array clock input hold time
5.5
6.0
6.0
0.0
ns
tACH
Array clock high time
5.0
5.0
6.0
0.0
ns
tACL
Array clock low time
5.0
5.0
6.0
0.0
tODH
Output data hold time after clock
1.0
1.0
1.0
C1 = 35 pF
(7)
ns
ns
tACO1
Array clock to output delay
12.0
14.0
16.0
25.0
ns
tACNT
Array clock minimum period
10.0
12.0
15.0
25.0
ns
fACNT
Maximum internal array clock
frequency
0.0
MHz
764
(6)
100.0
83.3
66.0
Altera Corporation
Classic EPLD Family Data Sheet
Table 13. EP610 Internal Timing Parameters
Symbol
Parameter
Conditions
EP610I-10
EP610I-12
EP610I-15
Min
Min
Min
Max
Max
Unit
Max
tIN
Input pad and buffer delay
1.5
4.0
4.0
tIO
I/O input pad and buffer delay
0.0
0.0
0.0
ns
tLAD
Logic array delay
5.5
6.0
9.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
3.0
2.0
2.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
8.0
5.0
6.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
6.0
5.0
6.0
ns
tSU
Register setup time
3.5
5.0
5.0
tH
Register hold time
3.5
4.0
7.0
tIC
Array clock delay
7.5
8.0
10.0
ns
tICS
Global clock delay
2.0
2.0
2.0
ns
tFD
Feedback delay
1.0
1.0
1.0
ns
tCLR
Register clear time
8.5
9.0
12.0
ns
ns
ns
ns
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
These values are specified in Table 3 on page 758.
See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic
timing parameters.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Sample-tested only for an output change of 500 mV.
The fMAX values represent the highest frequency for pipelined data.
Measured with a device programmed as a 16-bit counter.
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Altera Corporation
765
Notes:
EP910 EPLD
Features
■
■
■
■
■
■
High-performance, 24-macrocell Classic EPLD
– Combinatorial speeds with tPD as fast as 12 ns
–
Counter frequencies of up to 76.9 MHz
–
Pipelined data rates of up to 125 MHz
Programmable I/O architecture with up to 36 inputs or 24 outputs
EP910 and EP910I devices are pin-, function-, and programming filecompatible
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see Figure 11)
– 44-pin plastic J-lead chip carrier (PLCC)
– 40-pin ceramic and plastic dual in-line packages (CerDIP and
PDIP)
Figure 11. EP910 Package Pin-Out Diagrams
I/O
INPUT
INPUT
INPUT
CLK1
VCC
VCC
INPUT
INPUT
INPUT
I/O
Package outlines are not drawn to scale. Windows in ceramic packages only.
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
5
4
3
2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VCC
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK2
I/O
INPUT
INPUT
INPUT
GND
GND
CLK2
INPUT
INPUT
INPUT
I/O
18 19 20 21 22 23 24 25 26 27 28
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLK1
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
GND
Altera Corporation
44-Pin PLCC
40-Pin DIP
EP910
EP910I
EP910
EP910I
767
Classic EPLD Family Data Sheet
General
Description
Altera EP910 devices can implement up to 450 usable gates of SSI and MSI
logic functions. EP910 devices have 24 macrocells, 12 dedicated input
pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell
can access signals from the global bus, which consists of the true and
complement forms of the dedicated inputs and the true and complement
forms of either the output of the macrocell or the I/O input. The CLK1 and
CLK2 signals are the dedicated clock inputs for the registers in macrocells
13 through 24 and 1 through 12, respectively.
Figure 12. EP910 Block Diagram
Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages.
768
2
(3) INPUT
INPUT
(43) 39
3
(4) INPUT
INPUT
(42) 38
4
(5) INPUT
INPUT
(41) 37
1
(2)
CLK1
CLK2
(24) 21
5
6
7
8
9
10
11
12
13
14
15
16
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(18)
(40)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
36
35
34
33
32
31
30
29
28
27
26
25
17 (19) INPUT
INPUT
(27) 24
18 (20) INPUT
INPUT
(26) 23
19 (21) INPUT
INPUT
(25) 22
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
Global
Bus
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Altera Corporation
Classic EPLD Family Data Sheet
Figure 13 shows the typical supply current (ICC) versus frequency of
EP910 devices.
Figure 13. I CC vs. Frequency of EP910 Devices
100
Turbo
10
Typical ICC
Active (mA)
VCC = 5.0 V
TA = 25° C
1.0
Non-Turbo
0.1
1 kHz
10 kHz 100 kHz 1 MHz 10 MHz 40 MHz
Frequency
Figure 14 shows the typical output drive characteristics of EP910 devices.
Figure 14. Output Drive Characteristics of EP910 Devices
Drive characteristics may exceed shown curves.
EP910I EPLDs
EP910 EPLDs
120
60
100
50
IOL
80
40
Typical IO
Output
Current (mA)
VCC = 5.0 V
TA = 25° C
30
Typical IO
Output
Current (mA)
IOL
60
VCC = 5.0 V
TA = 25° C
40
20
IOH
IOH
20
10
0
0.45
1
2
3
4
VO Output Voltage (V)
Altera Corporation
5
0.45
1
2
3
4
5
VO Output Voltage (V)
769
Classic EPLD Family Data Sheet
Operating
Conditions
Tables 14 through 18 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP910 and EP910I devices.
Table 14. EP910 & EP910I Device Absolute Maximum Ratings
Symbol
Parameter
Notes (1), (2)
Conditions
EP910
EP910I
Unit
Min
Max
Min
–2.0
7.0
–2.0
7.0
V
DC input voltage
–2.0
7.0
–0.5
VCC + 0.5
V
IMAX
DC VCC or ground current
–250
250
IOUT
DC output current, per pin
–25
25
TSTG
Storage temperature
No bias
–65
150
–65
150
°C
TAMB
Ambient temperature
Under bias
–65
135
–65
135
°C
TJ
Junction temperature
Ceramic packages, under
bias
150
150
°C
Plastic packages, under
bias
135
135
°C
VCC
Supply voltage
VI
With respect to ground (3)
Table 15. EP910 & EP910I Device Recommended Operating Conditions
Symbol
Parameter
Conditions
mA
mA
Note (2)
EP910
Min
(4)
Max
EP910I
Max
4.75 (4.5) 5.25 (5.5)
Min
Unit
Max
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
TA
Operating temperature
For commercial use
tR
Input rise time
(5)
100 (50)
500
ns
tF
Input fall time
(5)
100 (50)
500
ns
Min
Max
Unit
For industrial use
Parameter
5.25
V
VCC + 0.3
–0.3
VCC + 0.3
V
0
VCC
0
VCC
V
0
70
0
70
°C
–40
Table 16. EP910 & EP910I Device DC Operating Conditions
Symbol
4.75
–0.3
85
°C
Notes (6), (7)
Conditions
VIH
High-level input voltage
2.0
VCC + 0.3
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level TTL output voltage
IOH = –4 mA DC (8)
2.4
V
High-level CMOS output voltage
IOH = –0.6 mA DC (8), (9)
3.84
V
VOL
Low-level output voltage
IOL = 4 mA DC (8)
II
I/O leakage current of dedicated input pins VI = VCC or ground
IOZ
Tri-state output leakage current
770
VO = VCC or ground
0.45
V
–10
10
µA
–10
10
µA
Altera Corporation
Classic EPLD Family Data Sheet
Table 17. EP910 & EP910I Device Capacitance
Symbol
Parameter
Note (6)
Conditions
EP910
Min
EP910I
Max
Min
Unit
Max
CIN
Input pin capacitance
VIN = 0 V, f = 1.0 MHz
20
8
CI/O
I/O pin capacitance
VOUT = 0 V, f = 1.0 MHz
20
8
pF
CCLK1
CLK1 pin capacitance
VIN = 0 V, f = 1.0 MHz
20
10
pF
CCLK2
CLK2 pin capacitance
VIN = 0 V, f = 1.0 MHz
60
12
pF
Table 18. EP910 & EP910I Device ICC Supply Current
Symbol
Parameter
pF
Notes (2), (6), (7)
Conditions
EP910
Min
EP910I
Typ
Max
Min
Unit
Typ
Max
ICC1
VCC supply current
(non-Turbo, standby)
VI = VCC or ground, no load
(10), (11)
20
150
60
150
µA
ICC2
VCC supply current
(non-Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (10), (11)
6
20
4
12
mA
ICC3
VCC supply current
(Turbo, active)
VI = VCC or ground, no load,
f = 1.0 MHz (11)
45
80
(100)
120
150
mA
Notes to tables:
(1)
(2)
(3)
See the Operating Requirements for Altera Devices Data Sheet in this data book.
Numbers in parentheses are for industrial-temperature-range devices.
The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V (EP910) or
–0.5 V (EP910I) or overshoot to 7.0 V (EP910) or VCC + 0.5 V (EP910I) for input currents less than 100 mA and periods
less than 20 ns.
(4) Maximum VCC rise time for EP910 devices = 50 ms; for EP910I devices, maximum VCC rise time is unlimited with
monotonic rise.
(5) For all clocks: tR and tF = 100 ns (50 ns for the industrial-temperature-range version).
(6) These values are specified in Table 15 on page 770.
(7) The device capacitance is measured at 25° C and is sample-tested only.
(8) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(9) This parameter does not apply to EP910I devices.
(10) When the Turbo Bit option is not set (non-Turbo mode), an EP910 device will enter standby mode if no logic
transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic
transitions occur for 75 ns after the last transition.
(11) Measured with a device programmed as a 24-bit counter.
Altera Corporation
771
Classic EPLD Family Data Sheet
Tables 19 and 20 show the timing parameters for EP910 devices.
Table 19. EP910 External Timing Parameters
Symbol
Parameter
Notes (1), (2)
Conditions
EP910-30
EP910-35
EP910-40
NonUnit
Turbo
Min Max Min Max Min Max
Adder (3)
tPD1
Input to non-registered output
C1 = 35 pF
30.0
35.0
40.0
30.0
tPD2
I/O input to non-registered output
C1 = 35 pF
33.0
38.0
43.0
30.0
ns
ns
tPZX
Input to output enable
C1 = 35 pF
30.0
35.0
40.0
30.0
ns
tPXZ
Input to output disable
C1 = 5 pF (4)
30.0
35.0
40.0
30.0
ns
tCLR
Asynchronous output clear time
C1 = 35 pF
33.0
38.0
43.0
30.0
ns
(5)
MHz
fMAX
Maximum frequency
41.7
37.0
32.3
0.0
tSU
Global clock input setup time
24.0
27.0
31.0
30.0
ns
tH
Global clock input hold time
0.0
0.0
0.0
0.0
ns
tCH
Global clock high time
12.0
13.0
15.0
0.0
ns
tCL
Global clock low time
12.0
13.0
15.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
tCNT
Global clock minimum clock period
(6)
fCNT
Maximum internal global clock
frequency
(6)
tASU
Array clock input setup time
10.0
tAH
Array clock input hold time
15.0
tACH
Array clock high time
15.0
tACL
Array clock low time
tODH
Output data hold time after clock
C1 = 35 pF (7)
tACO1
Array clock to output delay
C1 = 35 pF
tACNT
Array clock minimum clock period
fACNT
Maximum internal array clock
frequency
772
(6)
18
21.0
24.0
0.0
ns
30.0
35.0
40.0
0.0
ns
25.0
0.0
MHz
10.0
10.0
30.0
ns
15.0
15.0
0.0
ns
16.0
17.0
0.0
ns
15.0
16.0
17.0
0.0
1.0
1.0
1.0
33.3
33.3
28.6
ns
ns
33.0
38.0
43.0
30.0
ns
30.0
35.0
40.0
0.0
ns
0.0
MHz
28.6
25.0
Altera Corporation
Classic EPLD Family Data Sheet
Table 20. EP910 Internal Timing Parameters
Symbol
Parameter
Condition
EP910-30
EP910-35
EP910-40
Min
Min
Min
Max
Max
Unit
Max
tIN
Input pad and buffer delay
9.0
10.0
13.0
tIO
I/O input pad and buffer delay
3.0
3.0
3.0
ns
tLAD
Logic array delay
14.0
16.0
17.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
7.0
9.0
10.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
7.0
9.0
10.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
7.0
9.0
10.0
ns
tSU
Register setup time
12.0
13.0
15.0
ns
tH
Register hold time
12.0
12.0
12.0
ns
tIC
Array clock delay
17.0
19.0
20.0
ns
tICS
Global clock delay
2.0
2.0
1.0
ns
tFD
Feedback delay
tCLR
Register clear time
ns
4.0
6.0
8.0
ns
17.0
19.0
20.0
ns
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
These values are specified in Table 15 on page 770.
See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for more information on Classic
timing parameters.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Sample-tested only for an output change of 500 mV.
The fMAX values represent the highest frequency for pipelined data.
Measured with a device programmed as a 24-bit counter.
Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Altera Corporation
773
Classic EPLD Family Data Sheet
Tables 21 and 22 show the timing parameters for EP910I devices.
Table 21. EP910I External Timing Parameters
Symbol
Parameter
Notes (1), (2)
Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Unit
Adder
Min Max Min Max Min Max
C1 = 35 pF
Input to non-registered output
tPD2
I/O input to non-registered output
C1 = 35 pF
12.0
15.0
25.0
40.0
ns
tPZX
Input to output enable
C1 = 35 pF
15.0
18.0
28.0
40.0
ns
tPXZ
Input to output disable
C1 = 35 pF
(4)
15.0
18.0
28.0
40.0
ns
28.0
tCLR
Asynchronous output clear time
C1 = 35 pF
fMAX
Global clock maximum frequency
(5)
tSU
tH
12.0
15.0
15.0
25.0
(3)
tPD1
18.0
40.0
ns
40.0
ns
125.0
100.0
62.5
0.0
MHz
Global clock input setup time
8.0
11.0
16.0
40.0
ns
Global clock input hold time
0.0
0.0
0.0
0.0
ns
ns
tCH
Global clock high time
5.0
6.0
10.0
0.0
tCL
Global clock low time
5.0
6.0
10.0
0.0
ns
tCO1
Global clock to output delay
14.0
0.0
ns
tCNT
Global clock minimum clock period
C1 = 35 pF
25.0
fCNT
Maximum internal global clock
frequency
(6)
8.0
9.0
40.0
ns
76.9
13.0
66.6
15.0
40.0
0.0
MHz
40.0
ns
tASU
Array clock input setup time
3.0
4.0
8.0
tAH
Array clock input hold time
6.0
7.0
8.0
ns
tACH
Array clock high time
6.0
7.5
12.5
ns
6.0
7.5
12.5
ns
1.0
1.0
1.0
ns
tACL
Array clock low time
tODH
Output data hold time after clock
C1 = 35 pF
(7)
C1 = 35 pF
tACO1
Array clock to output delay
tACNT
Array clock minimum clock period
fACNT
Maximum internal array clock
frequency
774
(6)
76.9
16.0
18.0
22.0
40.0
ns
13.0
15.0
25.0
40.0
ns
66.6
40.0
MHz
Altera Corporation
Classic EPLD Family Data Sheet
Table 22. EP910I Internal Timing Parameters
Symbol
Parameter
Condition
EP910I-12
EP910I-15
EP910I-25
Min
Min
Min
Max
Max
Unit
Max
tIN
Input pad and buffer delay
2.0
3.0
2.0
tIO
I/O input pad and buffer delay
0.0
0.0
0.0
ns
tLAD
Logic array delay
8.0
9.0
17.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
2.0
3.0
6.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
5.0
6.0
9.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
5.0
6.0
9.0
ns
tSU
Register setup time
4.0
5.0
5.0
tH
Register hold time
4.0
6.0
11.0
tIC
Array clock delay
12.0
12.0
14.0
ns
tICS
Global clock delay
4.0
3.0
6.0
ns
tFD
Feedback delay
tCLR
Register clear time
ns
ns
ns
1.0
1.0
3.0
ns
11.0
12.0
20.0
ns
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
These values are specified in Table 15 on page 770.
See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Sample-tested only for an output change of 500 mV.
The fMAX values represent the highest frequency for pipelined data.
Measured with the device programmed as a 24-bit counter.
Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both
global and array clocking.
Altera Corporation
775
Notes:
EP1810 EPLD
Features
High-performance, 48-macrocell Classic EPLD
– Combinatorial speeds with tPD as fast as 20 ns
–
Counter frequencies of up to 50 MHz
–
Pipelined data rates of up to 62.5 MHz
Programmable I/O architecture with up to 64 inputs or 48 outputs
Programmable clock option for independent clocking of all registers
Macrocells individually programmable as D, T, JK, or SR flipflops, or
for combinatorial operation
Available in the following packages (see Figure 15)
– 68-pin ceramic pin-grid array (PGA)
– 68-pin plastic J-lead chip carrier (PLCC)
■
■
■
■
■
Figure 15. EP1810 Package Pin-Out Diagrams
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Package outlines not drawn to scale. See Table 32 on page 785 of this data sheet for PGA package pin-out information.
Windows in ceramic packages only.
L
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK1/INPUT
VCC
CLK2/INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
I/O
K
J
H
G
Bottom
View
F
E
D
C
B
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
CLK4/INPUT
VCC
CLK3/INPUT
INPUT
INPUT
INPUT
I/O
I/O
I/O
I/O
1
2
3
Altera Corporation
4
5
6
7
8
9
10 11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
68-Pin PGA
68-Pin PLCC
EP1810
EP1810
777
Classic EPLD Family Data Sheet
General
Description
Altera EP1810 devices offer LSI density, TTL-equivalent speed, and lowpower consumption. EP1810 devices have 48 macrocells, 16 dedicated
input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided
into four quadrants, each containing 12 macrocells. Of the 12 macrocells
in each quadrant, 8 have quadrant feedback and are “local” macrocells
(see “Feedback Select” on page 749 of this data sheet for more
information). The remaining 4 macrocells in the quadrant are “global”
macrocells. Both local and global macrocells can access signals from the
global bus, which consists of the true and complement forms of the
dedicated inputs and the true and complement forms of the feedbacks
from the global macrocells.
EP1810 devices also have four dedicated inputs (one in each quadrant)
that can be used as quadrant clock inputs. If the dedicated input is used
as a clock pin, the input feeds the clock input of all registers in that
particular quadrant.
778
Altera Corporation
Classic EPLD Family Data Sheet
Figure 16. EP1810 Block Diagram
Pin numbers are for J-lead packages. Pin numbers in parentheses are for PGA packages.
Quadrant A
Quadrant D
Local Bus—Quadrant D
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Local Bus—Quadrant A
2 (F1)
3 (G2)
4 (G1)
5 (H2)
6 (H1)
7 (J2)
8 (J1)
9 (K1)
10 (K2)
11 (L2)
12 (K3)
13 (L3)
(E1) 68
(E2) 67
(D1) 66
(D2) 65
(C1) 64
(C2) 63
(B1) 62
(B2) 61
(A2) 60
(A3) 59
(B3) 58
(A4) 57
Macrocell 48
Macrocell 47
Macrocell 46
Macrocell 45
Macrocell 44
Macrocell 43
Macrocell 42
Macrocell 41
Macrocell 40
Macrocell 39
Macrocell 38
Macrocell 37
14 (K4)
INPUT
INPUT
15 (L4)
INPUT
INPUT
(A5) 55
16 (K5)
INPUT
INPUT
(B5) 54
17 (L5)
INPUT/CLK1
19 (L6)
INPUT/CLK2
20 (K7)
Global
Bus
(B4) 56
INPUT/CLK4
(A6) 53
INPUT/CLK3
(A7) 51
INPUT
INPUT
(B7) 50
21 (L7)
INPUT
INPUT
(A8) 49
22 (K8)
INPUT
INPUT
(B8) 48
Quadrant C
Local Bus—Quadrant C
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
Macrocell 17
Macrocell 18
Macrocell 19
Macrocell 20
Macrocell 21
Macrocell 22
Macrocell 23
Macrocell 24
Local Bus—Quadrant B
Quadrant B
23 (L8)
24 (K9)
25 (L9)
26 (L10)
27 (K10)
28 (K11)
29 (J10)
30 (J11)
31(H10)
1)
32 (H1
33(G10)
1)
34 (G1
Macrocell 36
Macrocell 35
Macrocell 34
Macrocell 33
Macrocell 32
Macrocell 31
Macrocell 30
Macrocell 29
Macrocell 28
Macrocell 27
Macrocell 26
Macrocell 25
(A9) 47
(B9) 46
(A10) 45
(B10) 44
(B11) 43
(C11) 42
(C10) 41
(D11) 40
(D10) 39
(E11) 38
(E10) 37
(F11) 36
Global Macrocells
Local Macrocells
Altera Corporation
779
Classic EPLD Family Data Sheet
Figure 17 shows the typical supply current (ICC) versus frequency for
EP1810 EPLDs.
Figure 17. I CC vs. Frequency of EP1810 Devices
EP1810
100
Typical ICC
Active (mA)
10
VCC = 5.0 V
TA = 25° C
1.0
0.1
10 kHz
100 kHz
1 MHz
10 MHz
60 MHz
Frequency
Figure 18 shows the output drive characteristics of EP1810 devices.
Figure 18. Output Drive Characteristics of EP1810 Devices
Drive characteristics may exceed shown curves.
EP1810-35 & EP1810-45 EPLDs
EP1810-20 & EP1810-25 EPLDs
200
80
IOL
IOL
150
Typical I O
Output
Current (mA)
60
VCC = 5.0 V
TA = 25° C
100
50
2
3
4
VO Output Voltage (V)
780
VCC = 5.0 V
TA = 25° C
40
IOH
20
IOH
1
Typical IO
Output
Current (mA)
5
1
2
3
4
5
VO Output Voltage (V)
Altera Corporation
Classic EPLD Family Data Sheet
Operating
Conditions
Tables 23 through 27 provide information on absolute maximum ratings,
recommended operating conditions, operating conditions, and
capacitance for EP1810 devices.
Table 23. EP1810 Device Absolute Maximum Ratings
Symbol
Parameter
Notes (1), (2)
Conditions
Min
Max
Unit
V
VCC
Supply voltage
With respect to ground (3)
–2.0 (–0.5)
7.0
VI
DC input voltage
With respect to ground (3)
–2.0 (–0.5)
7.0
V
IMAX
DC V CC or ground current
–300 (–400)
300 (400)
mA
IOUT
DC output current, per pin
TSTG
Storage temperature
–25
25
mA
No bias
–65
150
°C
TAMB
TJ
Ambient temperature
Under bias
–65
135
°C
Junction temperature
Ceramic packages, under bias
150
°C
Plastic packages, under bias
135
°C
Max
Unit
Table 24. EP1810 Device Recommended Operating Conditions
Symbol
Parameter
Note (2)
Conditions
(4)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
TA
Operating temperature
For commercial use
tR
Input rise time
(5)
tF
Input fall time
(5)
For industrial use
Table 25. EP1810 Device DC Operating Conditions
Symbol
Parameter
Min
4.75 (4.5)
5.25 (5.5)
V
–0.3
VCC + 0.3
V
0
VCC
V
0
70
°C
–40
85
°C
50
ns
50
ns
Min
Max
Unit
2.0
VCC + 0.3
V
–0.3
0.8
Notes (6), (7)
Conditions
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level TTL output voltage
IOH = –4 mA DC (8)
2.4
3.84
High-level CMOS output voltage
IOH = –0.6 mA DC (8)
VOL
Low-level output voltage
IOL = 4 mA DC (8)
II
I/O pin leakage current of dedicated VI = VCC or ground
input pins
IOZ
Tri-state output leakage current
Altera Corporation
VO = VCC or ground
V
V
V
0.45
V
–10
10
µA
–10
10
µA
781
Classic EPLD Family Data Sheet
Table 26. EP1810 Device Capacitance
Symbol
Note (9)
Parameter
Conditions
Min
Max
Unit
CIN
Input pin capacitance
VIN = 0 V, f = 1.0 MHz
20
pF
CIO
I/O pin capacitance
VOUT = 0 V, f = 1.0 MHz
20
pF
CCLK1
CCLK1 pin capacitance
VIN = 0 V, f = 1.0 MHz
25
pF
CCLK2
CCLK2 pin capacitance
VIN = 0 V, f = 1.0 MHz
160
pF
Typ
Max
Unit
VI = VCC or ground, no load, -20, -25
(10)
-35, -45
50
150
µA
35
150
µA
VI = VCC or ground, no load, -20, -25
f = 1.0 MHz (10)
-35, -45
20
40
mA
10
30 (40)
mA
VI = VCC or ground, no load
f = 1.0 MHz (10)
-20, -25
180
225 (250)
mA
-35, -45
100
180 (240)
mA
Table 27. EP1810 Device ICC Supply Current
Symbol
ICC1
Parameter
VCC supply current
(non-Turbo, standby)
ICC2
VCC supply current
ICC3
VCC supply current (Turbo, active)
(non-Turbo, active)
Notes (2), (6), (7)
Conditions
Speed
Grade
Min
Notes to tables:
(1)
(2)
(3)
See the Operating Requirements for Altera Devices Data Sheet in this data book.
Numbers in parentheses are for industrial-temperature-range devices.
The minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
input currents less than 100 mA and periods less than 20 ns.
(4) Maximum VCC rise time is 50 ms.
(5) For EP1810 clocks: tR and tF = 100 ns (50 ns for industrial-temperature-range versions).
(6) Typical values are for TA = 25° C and VCC = 5 V.
(7) These values are specified in Table 24 on page 781.
(8) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL
output current.
(9) The device capacitance is measured at 25° C and is sample-tested only.
(10) Measured with a device programmed as four 12-bit counters.
782
Altera Corporation
Classic EPLD Family Data Sheet
Tables 28 through 31 show the timing parameters for EP1810-20,
EP1810-25, EP1810-35, and EP1810-45 devices.
Table 28. EP1810-20 & EP1810-25 External Timing Parameters
Symbol
Parameter
Conditions
Note (1)
EP1810-20 EP1810-25 Non-Turbo
Adder
Min Max Min Max
Unit
(2)
tPD1
Input to non-registered output
C1 = 35 pF
20.0
25.0
25.0
ns
tPD2
I/O input to non-registered output
C1 = 35 pF
22.0
28.0
25.0
ns
tSU
Global clock setup time
13.0
17.0
25.0
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tCH
Global clock high time
8.0
10.0
0.0
ns
tCL
Global clock low time
8.0
10.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
15.0
18.0
0.0
ns
tCNT
Minimum global clock period
(3)
20.0
25.0
0.0
ns
fCNT
Maximum internal frequency
(3)
40.0
0.0
MHz
50.0
tASU
Array clock setup time
8.0
10.0
25.0
ns
tAH
Array clock hold time
8.0
10.0
0.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
tODH
Output data hold time after clock
C1 = 35 pF (4)
20.0
1.0
25.0
1.0
25.0
ns
0.0
ns
tACNT
Array clock maximum clock period
(3)
0.0
ns
fACNT
Maximum internal array clock
frequency
(3)
50.0
40.0
0.0
ns
fMAX
Maximum clock frequency
(5)
62.5
50.0
0.0
MHz
20.0
25.0
Table 29. EP1810-20 and EP1810-25 Internal Timing Parameters
Symbol
Parameter
Conditions
EP1810-20 EP1810-25 Non-Turbo
Adder
Min Max Min Max
Unit
(2)
tIN
Input pad and buffer delay
5.0
7.0
0.0
tIO
I/O input pad and buffer delay
2.0
3.0
0.0
ns
tLAD
Logic array delay
9.0
12.0
25.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
6.0
6.0
0.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
6.0
6.0
0.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF (6)
6.0
6.0
0.0
ns
tSU
Register setup time
8.0
10.0
0.0
ns
tH
Register hold time
5.0
10.0
0.0
ns
tIC
Array clock delay
9.0
12.0
25.0
ns
tICS
Global clock delay
4.0
5.0
0.0
ns
tFD
Feedback delay
3.0
3.0
–25.0
ns
tCLR
Register clear time
9.0
12.0
25.0
ns
Altera Corporation
ns
783
Classic EPLD Family Data Sheet
Table 30. EP1810-35 & EP1810-45 External Timing Parameters
Symbol
Parameter
Conditions
Note (1)
EP1810-35 EP1810-45 Non-Turbo
Adder
Min Max Min Max
Unit
(2)
tPD1
Input to non-registered output
C1 = 35 pF
35.0
45.0
30.0
tPD2
I/O input to non-registered output
C1 = 35 pF
40.0
50.0
30.0
ns
tSU
Global clock setup time
30.0
ns
tH
Global clock hold time
0.0
0.0
0.0
ns
tCH
Global clock high time
12.0
15.0
0.0
ns
tCL
Global clock low time
12.0
15.0
0.0
ns
tCO1
Global clock to output delay
C1 = 35 pF
20.0
25.0
0.0
ns
tCNT
Minimum global clock period
(3)
35.0
45.0
0.0
ns
fCNT
Maximum internal frequency
(3)
28.6
22.2
0.0
MHz
tASU
Array clock setup time
10.0
11.0
30.0
ns
tAH
Array clock hold time
15.0
18.0
0.0
ns
tACO1
Array clock to output delay
C1 = 35 pF
30.0
ns
tODH
Output data hold time after clock
C1 = 35 pF (4)
25.0
30.0
35.0
1.0
45.0
1.0
ns
ns
tACNT
Array clock maximum clock period
(3)
0.0
ns
fACNT
Maximum internal array clock
frequency
(3)
28.6
22.2
0.0
ns
fMAX
Maximum clock frequency
(5)
40
33.3
0.0
MHz
35.0
45.0
Table 31. EP1810-35 & EP1810-45 Internal Timing Parameters
Symbol
Parameter
Conditions
EP1810-35 EP1810-45 Non-Turbo
Adder
Min Max Min Max
Unit
(2)
tIN
Input pad and buffer delay
7.0
6.0
0.0
tIO
I/O input pad and buffer delay
5.0
5.0
0.0
ns
tLAD
Logic array delay
19.0
28.0
30.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
9.0
11.0
0.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
9.0
11.0
0.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF (6)
11.0
0.0
ns
tSU
Register setup time
10.0
10.0
0.0
ns
tH
Register hold time
15.0
18.0
0.0
ns
tIC
Array clock delay
19.0
28.0
30.0
ns
tICS
Global clock delay
4.0
8.0
0.0
ns
tFD
Feedback delay
6.0
7.0
–30.0
ns
tCLR
Register clear time
24.0
32.0
30.0
ns
784
9.0
ns
Altera Corporation
Classic EPLD Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
These values are specified in Table 24 on page 781.
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
Measured with a device programmed as four 12-bit counters.
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
The fMAX values represent the highest frequency for pipelined data.
Sample-tested only for an output change of 500 mV.
Pin-Out
Information
Table 32 provides pin-out information for EP1810 devices in 68-pin PGA
packages.
Table 32. EP1810 PGA Pin-Outs
Pin
Altera Corporation
Function
Pin
Function
Pin
Function
Pin
Function
A2
I/O
B9
I/O
F10
GND
K4
INPUT
A3
I/O
B10
I/O
F11
I/O
K5
INPUT
A4
I/O
B11
I/O
G1
I/O
K6
VCC
A5
INPUT
C1
I/O
G2
I/O
K7
INPUT
A6
CLK4/INPUT
C2
I/O
G10
I/O
K8
INPUT
A7
CLK3/INPUT C10
I/O
G11
I/O
K9
I/O
A8
INPUT
C11
I/O
H1
I/O
K10 I/O
K11 I/O
A9
I/O
D1
I/O
H2
I/O
A10
I/O
D2
I/O
H10
I/O
L2
I/O
B1
I/O
D10
I/O
H11
I/O
L3
I/O
B2
I/O
D11
I/O
J1
I/O
L4
INPUT
B3
I/O
E1
I/O
J2
I/O
L5
CLK1/INPUT
B4
INPUT
E2
I/O
J10
I/O
L6
CLK2/INPUT
B5
INPUT
E10
I/O
J11
I/O
L7
INPUT
B6
VCC
E11
I/O
K1
I/O
L8
I/O
B7
INPUT
F1
I/O
K2
I/O
L9
I/O
B8
INPUT
F2
GND
K3
I/O
L10
I/O
785
Notes: