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DESIGN AND ANALYSIS OF HIGH PERFORMANCE LOW NOISE
OSCILLATORS AND PHASE LOCK LOOPS
By
Li Ke
A thesis submitted for the degree of Doctor of Philosophy
School of Electronics and Computer Science,
University of Southampton,
United Kingdom.
Sep, 2010
UNIVERSITY OF SOUTHAMPTON
ABSTRACT
FACULTY OF ENGINEERING
SCHOOL OF ELECTRONICS AND COMPUTER SCIENCE
Doctor of Philosophy
DESIGN AND ANALYSIS OF HIGH PERFORMANCE LOW NOISE
OSCILLATORS AND PHASE LOCK LOOPS
by Li Ke
The design and implementation of high purity, high speed and power efficient
clock generation Integrated Circuits continue to be one the greatest challenges facing
IC designers today. In order to address this challenge, this thesis considers the
modeling and design of two fundamental clock generation circuits – the VCO and PLL.
An improved ring oscillator topology is proposed which has the advantage of an
ultra wide tuning range. A novel noise aware ring oscillator model is also proposed
which links the noise performance of the oscillator to its transistor dimensions giving
insight to the design procedure. The use of this VCO model in a noise-aware PLL
model allows the trade-off between noise performance and the loop bandwidth to be
quantified accurately. From further analysis of the proposed PLL model, a novel PLL
structure has been designed which is extremely successful at reference spur suppression.
Simulation results based on the proposed model and foundry BSIM3v3 models
are provided for all the VCO and PLL designs. To validate the proposed VCO topology
and VCO model, two prototype chips have been fabricated and measured results show
close agreement with theoretical analysis and simulation.
.
Contents
Chapter 1
Introduction ......................................................................................... 1
1.1
Design trends in modern clock generation circuits ........................................ 1
1.2
Design challenges faced by the PLL designer ............................................... 4
1.2.1
Negative effects introduced by process scaling ................................. 4
1.2.2
Difficulty of modelling noise in PLL designs.................................... 9
1.3
Project motivation ........................................................................................ 10
1.4
Project contribution...................................................................................... 11
1.5
Thesis outline ............................................................................................... 12
1.6
Publications .................................................................................................. 14
Chapter 2
2.1
Fundamentals of oscillators and phase locked loops ..................... 15
Voltage controlled oscillator ........................................................................ 15
2.1.1
Small signal model ........................................................................... 17
2.1.2
RC based oscillator .......................................................................... 18
2.1.3
Large signal model ........................................................................... 21
2.1.4
Design parameters of a VCO ........................................................... 22
Tuning Range ........................................................................................... 24
Tuning Linearity ....................................................................................... 25
Output Amplitude ..................................................................................... 25
Power Dissipation..................................................................................... 26
Output Signal Purity ................................................................................. 26
2.1.5
2.2
2.3
Phase Locked Loop ...................................................................................... 32
2.2.1
Type I PLL ....................................................................................... 34
2.2.2
Type II PLL ..................................................................................... 40
Summary ...................................................................................................... 45
Chapter 3
3.1
LC based oscillator .......................................................................... 29
PLL literature review, noise theory and analysis .......................... 47
Literature review of charge pump PLL ........................................................ 47
3.1.1
Dead zone cancellation of phase frequency detector ....................... 49
3.1.2
Performance enhancement ............................................................... 52
3.1.3
Adaptive bandwidth and PVT tolerant designs ............................... 56
3.1.4
Noise modelling approaches ............................................................ 62
3.1.5
3.2
Noise reduction methods.................................................................. 67
Literature review of RC based VCO noise models...................................... 71
3.2.1
Noise model for single transistor ..................................................... 71
3.2.2
Impulse sensitivity function model .................................................. 74
3.2.3
Transistor sizing to phase noise ....................................................... 79
White noise induced phase noise.............................................................. 82
Flicker noise induced phase noise ............................................................ 84
Flicker noise in control module ................................................................ 87
3.2.4
Performance enhancement ............................................................... 89
Coupled oscillators ................................................................................... 90
Multiple feedback ..................................................................................... 91
3.2.5
3.3
Comparison of existing designs ....................................................... 96
Summary ...................................................................................................... 98
Chapter 4
Ultra wide tuning range ring oscillator........................................... 99
4.1
Improved delay cell structure....................................................................... 99
4.2
Phase noise model oriented transistor width sizing ................................... 102
4.3
Design methodology .................................................................................. 103
4.4
Design example 1&2 and simulation results ............................................. 104
4.4.1
Design example 1: 32M—5.1GHz ................................................ 104
Transistor sizing ..................................................................................... 104
Layout of delay cell in design example1 ................................................ 105
4.4.2
Design example 2: 4M—800 MHz ................................................ 107
4.5
Realization and testing of prototype chip 1 ............................................... 108
4.6
Summary .................................................................................................... 111
Chapter 5
A novel noise-aware oscillator model ............................................ 113
5.1
Modelling of frequency tuning behaviour. ................................................ 114
5.2
Modelling of VCO noise ............................................................................ 120
5.2.1
Generation of time domain based flicker noise ............................. 121
5.2.2
Integration of noise generator into the VCO model....................... 125
5.2.3
Verifications with simulation examples......................................... 131
5.2.4
Advanced flicker noise modelling in control module .................... 136
5.3
Realization of prototype chip 2 .................................................................. 140
5.4
Measurement of prototype chip 2 .............................................................. 142
5.4.1
PCB design .................................................................................... 142
5.4.2
Time domain measurement results ................................................ 143
Tuning range........................................................................................... 143
Jitter ........................................................................................................ 145
5.4.3
Frequency domain measurement results ........................................ 146
Frequency spectrum to phase noise ........................................................ 146
Phase Noise over tuning range ............................................................... 147
5.4.4
5.5
Discussion of probe pads based measurement results ................... 148
Summary .................................................................................................... 151
Chapter 6
A novel noise aware PLL model and low-noise PLL ................... 153
6.1
Two PLL (type II) design examples .......................................................... 153
6.2
Realization of the proposed new PLL model ............................................. 158
6.2.1
Model of PFD ................................................................................ 158
6.2.2
Model of frequency divider ........................................................... 159
6.2.3
Model of charge-pump................................................................... 160
6.2.4
Comprehensive PLL model. .......................................................... 161
6.3
A new PLL structure .................................................................................. 168
6.4
Advanced verification of the proposed new PLL structure. ...................... 181
6.5
Summary .................................................................................................... 186
Chapter 7
Conclusions and further work ....................................................... 187
7.1
Conclusions ................................................................................................ 187
7.2
Future work ................................................................................................ 188
Appendix A
Fundamental building blocks ....................................................... 191
A.1 DC signal generation.................................................................................... 191
A.1.1 Current mirror .................................................................................. 193
A.1.2 Biasing circuit and cascode current mirror ...................................... 194
Beta-multiplier........................................................................................ 194
Cascode current mirror ........................................................................... 198
A.1.2 Bandgap reference (BGR) ................................................................ 200
A.2 Operational amplifier ................................................................................... 207
A.2.1 Single ended amplifier ..................................................................... 208
A.2.2 Differential amplifier ....................................................................... 217
A.2.3 Operational amplifier ....................................................................... 220
Appendix B
Relation between jitter and phase noise....................................... 225
Appendix C
Measurement results of prototype chip 2 .................................... 229
Appendix D
Matlab code for VCO model ......................................................... 233
References
237
List of Figures
Figure 1-1 Linear model of Phase Locked Loop ............................................................. 2
Figure 1-2 Fast-lock, low-skew clock generation system design for ―Nehalem‖ [5] ...... 2
Figure 1-3 Conventional direct up-conversion transmitter .............................................. 3
Figure 1-4 Distribution of drain current at different corners. (a) 130 process, (b) 90nm
process ..................................................................................................................... 7
Figure 1-5 Variation of drain current due to mismatch effect ......................................... 8
Figure 1-6 Thesis outline ............................................................................................... 13
Figure 2-1 Step response of op-amp in Figure A -28 (a) with Miller capacitance, (b)
without Miller capacitance ..................................................................................... 16
Figure 2-2 Feedback system .......................................................................................... 17
Figure 2-3 Schematic of three stage ring oscillator formed by current source load
inverter and its output waveform ........................................................................... 19
Figure 2-4 Frequency response of single delay stage in Figure 2-3 .............................. 20
Figure 2-5 (a) Push pull inverter based oscillator (b) current starved VCO .................. 23
Figure 2-6 Tuning range characteristic of current starved oscillator ............................. 24
Figure 2-7 Output waveform at different frequencies. (a) current source load inverter,
(b) current starved inverter..................................................................................... 25
Figure 2-8 Output power spectrum of oscillator. (a) ideal. (b) practical ....................... 26
Figure 2-9 Schematic level phase noise simulation of current starved VCO. ............... 28
Figure 2-10 Schematic of LC-VCO (a) theoretical model (b) realization with st12
process ................................................................................................................... 29
Figure 2-11 Schematic level phase noise simulation of LC-VCO ................................. 30
Figure 2-12 Tuning range characteristic of LC-VCO .................................................... 30
Figure 2-13 Layout view of example LC-VCO reported in [61] ................................... 31
Figure 2-14 Tuning characteristic of current starved oscillator upon different
temperatures ........................................................................................................... 32
Figure 2-15 Linear model of Phase Locked Loop ......................................................... 33
Figure 2-16 Circuit diagram of XOR gate ..................................................................... 34
Figure 2-17 Simulation results of XOR gate ................................................................. 34
Figure 2-18 Block diagram of a typical type I PLL ....................................................... 35
Figure 2-19 Transient simulation results for type I PLL, (a) reference signal (b)
feedback signal after 5 stage frequency divider ..................................................... 37
Figure 2-20 Transient simulation results of type I PLL (control node voltage of VCO).
............................................................................................................................... 37
Figure 2-21 Control node voltage of VCO (VinVCO) with loop filter‘s cut-off frequency
sweep ..................................................................................................................... 38
Figure 2-22 TSPC frequency divider and its simulation results .................................... 39
Figure 2-23 Block diagram of D flip-flop ..................................................................... 40
Figure 2-24 Block diagram of a typical charge pump PLL ........................................... 41
Figure 2-25 Implementation of PFD .............................................................................. 42
Figure 2-26 Simulation results of typical PFD. (a) same frequency with a constant
phase difference, (b) different frequency ............................................................... 43
Figure 2-27 Schematic of an example charge pump ...................................................... 44
Figure 2-28 Control node voltage of VCO (VinVCO) within type II PLL example ........ 45
Figure 3-1 Bode plot of open loop transfer function of charge pump PLL in chapter 2 48
Figure 3-2 Illustration of ―dead zone‖ in PFD ............................................................... 49
Figure 3-3 Improved PFD for ―dead zone‖ cancellation ............................................... 50
Figure 3-4 PFD realized for high speed operation ......................................................... 50
Figure 3-5 Layout of PFD shown in Figure 3-4 ............................................................ 51
Figure 3-6 Post layout simulation results of PFD shown in Figure 3-4 ........................ 51
Figure 3-7 Control node voltage of VCO (VinVCO) after new PFD incorporated .......... 52
Figure 3-8 Practical implementation of the charge pump: (a) without mismatch
cancellation, (b) with mismatch cancellation......................................................... 53
Figure 3-9 Control node voltage of VCO (VinVCO) after mismatch cancellation function
incorporated. .......................................................................................................... 54
Figure 3-10 Charge pump and loop filter with adaptive bandwidth biasing ................. 59
Figure 3-11 Simulation results of charge pump current (Ipump) and effective resistance
(R) with adaptive control ....................................................................................... 60
Figure 3-12 Transient simulation results of an adaptive bandwidth PLL. ..................... 61
Figure 3-13 PLL linear phase noise model. ................................................................... 62
Figure 3-14 Bode plot of phase noise transfer functions in Table 3-2........................... 64
Figure 3-15 Phase noise analysis of PLL. (a) transfer function of ratio between VCO
phase noise and PLL phase noise; (b) phase noise plot of VCO and its contribution
to PLL .................................................................................................................... 64
Figure 3-16 Example circuit of Charge Pump and sample-reset loop filter [70]........... 69
Figure 3-17 Example circuit diagram of a digitally controlled PLL [90] ...................... 69
Figure 3-18 Common source amplifier including noise sources ................................... 72
Figure 3-19 Output noise spectrum of single transistor ................................................. 73
Figure 3-20 Phase impulse response model ................................................................... 74
Figure 3-21 Five stage ring oscillator ............................................................................ 80
Figure 3-22 Illustration of terms: To, td, Δ td, vn............................................................. 80
Figure 3-23 Flicker noise source induced phase noise modelling ................................. 87
Figure 3-24 Flicker noise correlated modulation mechanism in control modules......... 88
Figure 3-25 Signal spectrum of coupled oscillator ........................................................ 90
Figure 3-26 Phase noise spectrum of 1/2/4/8/16 coupled oscillators ............................ 91
Figure 3-27 (a) Five stage ring oscillator with single feedback loop. (b) Five stage ring
oscillator with double feedback loop ..................................................................... 92
Figure 3-28 (a) Output waveform with single feedback loop. (b) output waveform with
double feedback loop ............................................................................................. 93
Figure 3-29 Four stage differential ring oscillator (a) single feedback loops (b) double
feedback loops (c) triple feedback loops ............................................................... 94
Figure 3-30 (a) Double inputs source-coupled delay cell. (b) triple inputs sourcecoupled delay cell. (c) double inputs cross-coupled delay cell. (d) dual inverter
delay cell. ............................................................................................................... 95
Figure 3-31 Dual inverter delay cell based four stage ring oscillator. (a) negative
feedback. (b) positive feedback ............................................................................. 95
Figure 4-1 Existing double feedback dual inverter delay cell [40]. ............................. 100
Figure 4-2 Improved double feedback dual inverter delay cell. .................................. 101
Figure 4-3 DC analysis for existing and improved delay cells. ................................... 101
Figure 4-4 Theoretical model for proposed delay cell ................................................. 102
Figure 4-5 Design dimensions of example 1 ............................................................... 105
Figure 4-6 Stack sizing for each FET .......................................................................... 105
Figure 4-7 Illustration of layout structure for left half delay cell ................................ 106
Figure 4-8 Layout for the left half of the delay cell..................................................... 106
Figure 4-9 All layer view of chip 1 evaluation PCB ................................................... 108
Figure 4-10 Output signal at 108.08MHz (864.6MHz) of design example 2 .............. 109
Figure 4-11 Jitter performance output signal at 108.08MHz (864.6MHz) of design
example 2 ............................................................................................................. 109
Figure 4-12 Performance comparison between simulation and measurement results of
design example 2.................................................................................................. 111
Figure 5-1 Modelling of effective RC delay for the proposed new delay cell ............ 115
Figure 5-2 Simulink model of the variable resistor (Rctn). ......................................... 117
Figure 5-3 Simulink model of the propagation delay (push-delay) ............................. 118
Figure 5-4 Preliminary Simulink model of VCO frequency tuning behaviour. .......... 118
Figure 5-5 Design examples‘ oscillation frequency simulated using Simulink .......... 119
Figure 5-6 Design examples‘ oscillation frequency when PVT variation is included 120
Figure 5-7 Block definition of the random number generator ..................................... 122
Figure 5-8 Simulink model of 1/f noise shaping filter ................................................. 123
Figure 5-9 Testing platform of the flicker noise generator illustrated in Figure 5-8. .. 124
Figure 5-10 Comparison between Simulink modelling results and Spectre simulation
results (NMOS: W/L=10μm/0.4μm, biasing at VGS=0.9V) .................................. 125
Figure 5-11 Simulink model of jitter generator (push). ............................................... 128
Figure 5-12 Proposed Simulink model of VCO, which includes jitter generator ........ 128
Figure 5-13 Simulink model based oscillation frequency plot, which includes flicker
noise ..................................................................................................................... 129
Figure 5-14 Calculation flow chart: from instantaneous frequency and phase to phase
noise. .................................................................................................................... 130
Figure 5-15 Flicker noise induced phase noise plot for design example 2, comparison
between the proposed Simulink model and Spectre based results ....................... 130
Figure 5-16 Thermal noise induced phase noise plot for design example 2, comparison
between the proposed Simulink model and Spectre based results ....................... 131
Figure 5-17 Flicker noise induced phase noise plot for VCO design example 2,
comparison between the proposed Simulink model and Spectre based results with
tuning voltage 0.4V~1.0V .................................................................................... 132
Figure 5-18 Flicker noise induced phase noise plot for VCO design example 1,
comparison between the proposed Simulink model and Spectre based results with
tuning voltage 0.4V~1.2V .................................................................................... 133
Figure 5-19 Schematic of delay cell for VCO design example 3 ................................ 134
Figure 5-20 Layout of VCO design example 3............................................................ 134
Figure 5-21 Voltage frequency tuning behaviour of design example 3 (Simulink
modelling results and RCc extraction mode based post layout simulation result.)
............................................................................................................................. 135
Figure 5-22 Flicker noise induced phase noise plot for design example 3, comparison
between the proposed Simulink model and Spectre based results with tuning
voltage 0.4V~1.2V ............................................................................................... 136
Figure 5-23 Dual inverter based VCO together with the voltage control module. ...... 137
Figure 5-24 Proposed Simulink model of VCO including voltage control module
included ................................................................................................................ 138
Figure 5-25 Flicker noise induced phase noise plot for VCO design example 2, with
different transistor dimensions in the voltage control modules ........................... 139
Figure 5-26 Top level structure of chip 2 .................................................................... 140
Figure 5-27 Schematic of the output buffer ................................................................. 141
Figure 5-28 Entire chip layout ..................................................................................... 141
Figure 5-29 All layer view of chip 2 evaluation PCB ................................................. 142
Figure 5-30 Tuning range of design example 2. .......................................................... 143
Figure 5-31 Output signal at 748.3MHz ...................................................................... 144
Figure 5-32 Output signal at 197KHz .......................................................................... 144
Figure 5-33 Measured rms jitter (left) and as a percentage of oscillation period (right).
............................................................................................................................. 145
Figure 5-34 Measured p-p jitter (left) and as a percentage of oscillation period (right).
............................................................................................................................. 145
Figure 5-35 Measured jitter histogram at 748MHz ...................................................... 146
Figure 5-36 Measured signal spectrum at 746MHz with 100MHz/2MHz span using PCB
based appraoch ..................................................................................................... 147
Figure 5-37 Measured phase noise at 744MHz using PCB based approach. ............... 147
Figure 5-38 RF probe pads based measuring platform ................................................ 149
Figure 5-39 Die photo of the chip being measureing .................................................. 149
Figure 5-40 Measured signal spectrum at 752MHz using RF probe pads based approach
............................................................................................................................. 150
Figure 5-41 Measured signal spectrum at 752MHz using RF probe pads based approach
............................................................................................................................. 151
Figure 6-1 Block diagram of a typical charge pump PLL ........................................... 154
Figure 6-2 Bode plot of open loop transfer function of PLL design example 1 .......... 155
Figure 6-3 Bode plot of open loop transfer function of PLL design example 2. ......... 156
Figure 6-4 Transistor level simulation results (Spectre) of PLL design example 1 .... 157
Figure 6-5 Transistor level simulation results (Spectre) of PLL design example 2 .... 157
Figure 6-6 Modelling of the digital gate with propagation delay (NAND4) ............... 159
Figure 6-7 Modelling of the PFD ................................................................................ 159
Figure 6-8 Modelling of the frequency divider............................................................ 160
Figure 6-9 Modelling of the charge-pump with mismatch control .............................. 160
Figure 6-10 Model of the comprehensive PLL ............................................................ 161
Figure 6-11 Settling behaviour (vco_control) of PLL design example 1, obtained within
Simulink model (excluding in-band noise and without charge pump mismatch) 162
Figure 6-12 Phase noise curve of the PLL design example 1 obtained from Simulink
(excluding in-band noise and without charge pump mismatch) .......................... 163
Figure 6-13 Settling behavioural (vco_control) of PLL design example 1, obtained
within Simulink Model (including loop filter noise and charge pump mismatch)
............................................................................................................................. 164
Figure 6-14 Phase noise curve of the PLL design example 1 obtained from Simulink
(including loop filter noise and charge pump mismatch) .................................... 165
Figure 6-15 Settling behaviour (vco_control) of PLL design example 2, obtained within
Simulink Model (including loop filter noise and charge pump mismatch) ......... 166
Figure 6-16 Phase noise curve of the PLL design example 2, obtained from Simulink
(including loop filter noise and charge pump mismatch) .................................... 167
Figure6-17 Proposed Simulink model of VCO including voltage control module ..... 168
Figure 6-18 Applying the all-pass filter within the proposed VCO model.................. 169
Figure 6-19 Phase noise curve of PLL design example 3, obtained from Simulink
(including loop filter noise and charge pump mismatch) .................................... 170
Figure 6-20 Modified VCO topology by incorporating three stage all-pass filters ..... 171
Figure 6-21 Transistor level simulation results (Spectre) of PLL design example 3, with
4 control signals applied to the VCO. .................................................................. 172
Figure 6-22 Transistor level simulation results (Spectre) of PLL design example 3,
average of 4 control signals that are applied to the VCO. ................................... 173
Figure 6-23 Block diagram of PLL design example 3 ................................................. 174
Figure 6-24 Block diagram of the proposed novel PLL .............................................. 174
Figure 6-25 Improved VCO topology by incorporating three stage all-pass filters, the
PVT variation is considered ................................................................................. 176
Figure 6-26 Comprehensive PLL model of the proposed novel PLL .......................... 177
Figure 6-27 Phase noise curve of PLL design example 4, obtained from Simulink
(including loop filter noise and charge pump mismatch) .................................... 178
Figure 6-28 Spectrum of the PLL‘s output signal, obtained from Simulink model (PLL
design example 1 and 4) ...................................................................................... 179
Figure 6-29 Bode plot of open loop transfer function of PLL design example 3 ........ 180
Figure 6-30 Bode plot of open loop transfer function of PLL design example 4 ........ 181
Figure 6-31 Layout of VCO design example 3, modified with quadrature control to
each delay cell ...................................................................................................... 182
Figure 6-32 Post layout simulation results (Spectre) of PLL design example 5 ......... 183
Figure 6-33 Post layout simulation results (Spectre) of PLL design example 6, with
four control signals applied to the VCO .............................................................. 183
Figure 6-34 Post layout simulation results (Spectre) of PLL design example 6, average
of four control signals that are applied to the VCO. ............................................ 184
Figure 6-35 Schematic of the optimized output buffer ................................................ 185
Figure 6-36 Layout of the optimized output buffer ..................................................... 185
Figure 6-37 Post layout simulation results of the improved output buffer .................. 186
Figure 7-1 Corner frequency tuning of the all-pass filter ............................................ 189
Figure A-1 Current-voltage characteristics for st12 NMOS (W/L=150nm/130nm) .... 192
Figure A-2 Conceptual model of current mirror .......................................................... 193
Figure A-3 Beta-multiplier for constant biasing generation ........................................ 195
Figure A-4 Dependence of reference current (Iref) on supply voltage (VDD). ............ 196
Figure A-5 Layout of beta-multiplier .......................................................................... 197
Figure A-6 How the finite output resistance of the MOSEFT affects the output current
............................................................................................................................. 198
Figure A-7 Biasing and reference current generation circuit....................................... 199
Figure A-8 Temperature behaviour of bias voltage Vbiasn and drain current of M1 .... 200
Figure A-9 Layout of pseudo PNP bipolar transistor .................................................. 201
Figure A-10 Voltage, current and temperature characteristics of the diode shown in
Figure A-9 ............................................................................................................ 202
Figure A-11 Diode-reference, self-biasing circuit. ...................................................... 203
Figure A-12 Schematic of total bandgap reference circuit .......................................... 204
Figure A-13 Temperature behaviour of BGR reference voltage at 600mV ................ 205
Figure A-14 Temperature behaviour comparison between BGR and basic biasing
approach ............................................................................................................... 206
Figure A-15 Layout of BGR ........................................................................................ 207
Figure A-16 Common source amplifier with current source load. .............................. 209
Figure A-17 Frequency response of CS amplifier in Figure A-16 .............................. 210
Figure A-18 Common source amplifier with current source load and source impedance
............................................................................................................................. 211
Figure A-19 Modelling of Miller capacitance ............................................................. 213
Figure A-20 Frequency response of CS amplifier with source resistance ................... 213
Figure A-21 (a) Two stage single-ended amplifier, (b) its small signal model ........... 214
Figure A-22 Two stage amplifier with Miller capacitance compensation ................... 215
Figure A-23 Two stages amplifier with Miller capacitance compensation and zero
cancellation .......................................................................................................... 216
Figure A-24 Bock diagram of two stage op-amp with output buffer .......................... 217
Figure A-25 Analytical model of differential amplifier .............................................. 218
Figure A-26 Differential amplifier with cascode tail current ...................................... 219
Figure A-27 DC biasing circuit for op-amp ................................................................. 220
Figure A-28 Schematic of a folded cascode op-amp with input common range
extension and a gain enhancement module .......................................................... 222
Figure A-29 Layout of op-amp in Figure A -28 .......................................................... 223
Figure A-30 Frequency response of op-amp in Figure A-28 (Post layout level
simulation results) ................................................................................................ 224
Figure B-1 Illustration of Jitter .................................................................................... 226
Figure D-1 MATLAB control code for the propose Simulink VCO model (part A) .. 234
Figure D-2 MATLAB control code for the propose Simulink VCO model (part B) .. 235
List of Tables
Table 1-1 Specifications for frequently adopted RF communication standards .............. 3
Table 1-2 Typical parameters for long/short channel MOSFETS [10] ........................... 5
Table 1-3 Process parameters from ST microelectronics. [14]‒[16]. .............................. 6
Table 3-1 Specifications of charge pump PLL in Chapter 2 ......................................... 48
Table 3-2 PLL phase noise transfer function for each block ......................................... 63
Table 3-3 Performance comparison between single feedback loop and double feedback
loop ........................................................................................................................ 93
Table 3-4 Comparison of existing design ...................................................................... 97
Table 4-1 Design example specifications .................................................................... 104
Table 4-2 Simulation results of design example 1 ....................................................... 107
Table 4-3 Design example two dimensions ................................................................. 107
Table 4-4 Simulation results of design example 2 ....................................................... 108
Table 4-5 Measurement results of chip 1..................................................................... 110
Table 5-1 Transistor dimensions of analytical design cases, which are created for
voltage control module‘s noise analysis. ............................................................. 138
Table 5-2 Measured phase noise over full tuning range .............................................. 148
Table 6-1 Specifications of PLL design example 1 & 2 .............................................. 155
Table 6-2 Specifications of PLL design example 5 & 6 .............................................. 182
Table A-1 Component values and transistor dimensions for Beta-multiplier in Figure
A-3 ....................................................................................................................... 196
Table A-2 Component values and transistor dimensions for BGR in Figure A-12 ..... 205
DECLARATION OF AUTHORSHIP
I, Li Ke, declare that the thesis entitled ―DESIGN AND ANALYSIS OF HIGH
PERFORMANCE LOW NOISE OSCILLATORS AND PHASE LOCK LOOPS‖ and
the work presented in the thesis are both my own, and have been generated by me as
the result of my own original research. I confirm that:

this work was done wholly or mainly while in candidature for a research
degree at this University;

where any part of this thesis has previously been submitted for a degree or
any other qualification at this University or any other institution, this has
been clearly stated;

where I have consulted the published work of others, this is always clearly
attributed;

where I have quoted from the work of others, the source is always given.
With the exception of such quotations, this thesis is entirely my own
work;

I have acknowledged all main sources of help;

where the thesis is based on work done by myself jointly with others, I
have made clear exactly what was done by others and what I have
contributed myself;parts of this work have been published as [95][97].
Signed: ………………………………………………………………………..
Date:…………………………………………………………………………….
Acknowledgements
This thesis records the journey this project has taken over the past four years,
which not only includes background review, innovation, theoretical modeling, and
practical realization, but also depicts the learning curve within each step of the project.
Despite starting from a very fundamental level and encountering many challenges
along the way, a comprehensive model of the Phase Locked Loop (PLL) has been
created and from this a new, entirely unique, PLL structure has been designed, which is
extremely successful at reference spur suppression. It is hoped that the final fruits of
this project can contribute to a revolutionary change in PLL IC design. However, it is
accepted that innovation and improvement on the work here will never stop, because
the quest for design perfection is endless.
I want to take this opportunity to say thanks to Dr. Reuben Wilcock for the
training in circuit design, IC layout, PCB design, and paper writing. Without his help, I
would not have arrived at the finish line of my PhD. Furthermore, special thanks go to
my Supervisor Dr. Peter Wilson for the encouragement and help he gave me from day
1 of my PhD project.
I want give a special thanks to Dr. Dominique Coué, Bruno Johnson and
Wolfgang Bruchner, who are members of Cascoda Semiconductor Design Ltd. At the
final stage of this PhD project, I undertook a half year internship project with Cascoda.
Due to a confidentiality agreement, none of the technical work undertaken whilst at
Cascoda can be presented in this project; however, this industrial experience greatly
enhanced my skills and understanding of analogue IC design.
Besides this, special thanks go to Dr. Sawal Ali and Dr. Ren Xianqiang for
discussions about circuit design. Special thanks also go to Dr. Kanad Mallik and Dr
Matthew Swabey for their help with chip testing and the Cadence tools. Special thanks
also go to all my friends who have helped me, encouraged me and shared the happiness
with me in past five years.
Finally, I want to acknowledge my parents, who gave me the financial support for
this PhD project. I will always owe them for this support, which cannot be counted and
redeemed.
Definitions and Abbreviations Used
BGR
Band Gap Reference
CMOS Complementary Metal–Oxide–Semiconductor
CMRR Common Mode Rejection Ratio
CTAT
Complementary To Absolute Temperature
DCS
Digital personal Communication System
DSM
Deep Sub-Micron
FOM
Figure Of Merit
GSM
Global System for Mobile communications
GPS
Global Position System
IC
Integrated Circuit
LO
Local Oscillator
PD
Phase Detector
PFD
Phase Frequency Detector
PLL
Phase Lock Loop
PM
Phase Margin
PTAT
Proportional To Absolute Temperature
PSD
Power Spectral Density
PVT
Process Voltage Temperature
RF
Radio Frequency
RMS
Root Mean Square
TSPC
True-Single Phase Clock
VCO
Voltage Controlled Oscillators
Introduction
1
Chapter 1 Introduction
A ubiquitous requirement in today‘s world of consumer electronics is to generate
high performance, high frequency, reference clock signals. These signals are required
for both digital and analogue systems with clock generation and communication
standards being the most common applications. In the case of a digital system, the
frequency of a clock signal may drift from its designed value in the presence of
temperature and process variations, making a frequency compensation mechanism
essential. For analogue systems, especially for wireless communication carrier signals,
smarter and more accurate frequency adjustment approaches are required than for their
digital counterparts.
Fundamentally, no matter whether designed for digital or analogues applications,
a clock generation circuit must ensure the devices are working at their designed
operational speed. Furthermore, besides the clock generation mechanism, many of
these devices require their clock signal to be tuneable over a range of frequency bands.
This requires the use of a Voltage Controlled Oscillator (VCO) and the controllability
requirement demands the utilization of the Phase-Locked Loop (PLL). In this chapter,
the basic operation of the phase locked loop is introduced together with some of the
challenges associated with its design. The chapter ends with a summary of the thesis
structure and the peer-reviewed contributions made to date.
1.1 Design trends in modern clock generation circuits
The general concept of the Phase-Locked Loop, shown in Figure 1-1, was
invented in the 1920s-1930s, where the initial descriptions of the key concepts can be
found in papers by Appleton [1] in 1923 and de Bellescize [2] in 1932. With the rapid
Introduction
2
development of Integrated Circuits (IC‘s) in the 1970‘s, the PLL became widely used
in modern electronics and communication systems, however, the fact is that the basic
PLL structure has remained basically the same since its invention [3][4].
Phase/Frequency
Detector
Voltage-Controlled
Oscillator
Loop Filter
θe
fref
PFD
fvco
Vct
LF
Phase
error
Tuning
voltage
fdiv
÷N
Frequency Divider
Figure 1-1 Block diagram of Phase Locked Loop
Particularly for digital applications, the PLL serves the important task of clock
generation for microprocessor and peripheral I/O channels. A representative example is
the ―Nehalem‖ clocking system, which is designed to promote stability, modularity,
scalability and power-efficiency for Intel®core™ micro-architecture processors [5]. As
shown inFigure 1-2, this clock generation system is implemented by cascading two
specially designed PLLs and linking them with some associated components. Among
these, the ―local adaptive PLL‖ receives the most important design consideration. It
was reported in [5] that this local adaptive PLL was purposely designed with the
feature of adaptive fast locking (adaptive wide bandwidth). It shows a significant
improvement of the performance of locking time and peak-to-peak jitter. More
specifically, the following measurement results were highlighted due to their
outstanding nature, obtained from a 45nm process test chip:
 At 2.67GHz PLL output clock frequency, a locking time of 1µs.
 At3.2GHz clock frequency, RMS jitter at 0.27% of clock period, and
peak-to-peak jitter is 2.4% of the clock period.
analog digital
supply supply
fb ck
feedback
divider
Central
filter PLL
ref ck
1X
2X
4X
local
adaptive
PLL
core
feedback
divider
duty cycle
adjust
global clock
Dist.
local clocking
DCS duty cycle
sentinel
Figure 1-2 Fast-lock, low-skew clock generation system design for ―Nehalem‖ [5]
Introduction
3
At the risk of stating the obvious, the above example demonstrates that high
spectrum purity and high frequency are the most important design requirements for
PLLs embedded in high performance digital applications.
Single-Sideband
Modulator
I
D
LPF
A
PA
Digital
Baseband
(DSP)
0
90
Q
D
LPF
A
LO
Figure 1-3 Conventional direct up-conversion transmitter
On the other hand, for modern analogue/RF communication systems, the PLL
finds its utilization under severe constraints, defined by tough communication standards
(shown in Table 1-1). Consider the conventional direct up-conversion transmitter
shown in Figure 1-3 [6], in which an RF frequency synthesizer is employed as Local
Oscillator (LO) in the transmitter to perform frequency translation from the baseband to
the RF band. Previous work [6] and [7] note that a great majority of RF wireless
synthesizers for mobile applications are based on a charge pump PLL structure.
Table 1-1 Specifications for frequently adopted RF communication standards
Phase Noise
Standards
Frequency (MHz)
Settling time (µs)
GSM
880-960
<200
-131@1.6
DCS
1710-1880
<200
-131@1.6
GPS
1565-1585
X
-105@1.0
Bluetooth
2400-2485
<155
-119@1.5
802.11b
2400-2483
<150
-120@1.5
802.11a
5150-5825
X
-120@1.5
(dBc/Hz)@(MHz) offset
Consequently, the performance of PLLs realized for these RF frequency
synthesizer applications must meet the specifications that are defined by the
communication standards as listed in Table 1-1.We can see that, similar to digital
Introduction
4
applications, high purity and high frequency are the essential requirements. It appears
that the constraints on locking time for RF applications are slightly relaxed than for
digital applications. However, as discussed in Chapter 3 and Chapter 6, based on the
state of art monolithic CMOS (Complementary Metal–Oxide–Semiconductor) process,
to satisfy the specifications on signal purity and speed, the locking time, which is
essentially the PLL loop bandwidth, has to be chosen with certain degree of trade-off.
Furthermore, a ubiquitous requirement in today‘s world of consumer electronics
is power efficiency, especially if a battery is the primary source of power in portable
electronic devices. However, this is contradictory to the goal of high purity and high
speed, since existing theory [8] and designs [9] have proved that the most straight
forward method to lower the phase noise by 3dB is to double the power consumption of
the VCO. Therefore, the design and implementation of high purity, high speed and
power efficient clock generation circuits continuously poses a challenge for many IC
designers.
1.2 Design challenges faced by the PLL designer
More specifically, the following two areas receive the closest attention among the
myriad of difficulties faced by PLL designers. The first is the schematic level
implementation, during which the designer has to overcome non-ideal effects
introduced by modern CMOS process scaling; while the second is the noise modelling
and simulation for a specified PLL structure.
1.2.1
Negative effects introduced by process scaling
The advantages introduced by CMOS process scaling in previous decades are
considerable [11], and include transistor speed, number of transistors per area, circuit
complexity, cost per chip/PC and the data rate of networks. The rate of this progressive
evolution is widely known as ―Moore‘s Law‖ and many other rules of thumb have been
proposed [13]. However, for analog IC design, CMOS technology evolution has
introduced several problems, among which, decreasing supply voltage (lower voltage
headroom) and the reduction of transistor gain have become the most fundamental
problems that need to be addressed [12].
Introduction
5
In order to illustrate the negative effects introduced by process scaling, the
primary transistor parameters [10] for long channel MOSFET, and short channel
MOSEFT, are listed in Table 1-2, respectively.
Table 1-2 Typical parameters for long/short channel MOSFETS [10]
Long channel MOSEFT (Lmin=1µm)
Short channel MOSEFT (Lmin=50nm)
Process parameter extracted from
Process parameter extracted from
W/L=100µm/2µm NMOS
W/L=2.5µm/0.1µm NMOS
Power supply VDD
5V
Power supply VDD
1V
Threshold voltage Vthn
800mV
Threshold voltage Vthn
280mV
Transconductance gm
150µA/V
Transconductance gm
150µA/V
Output resistance ro
5MΩ
Output resistance ro
167kΩ
Transition frequency fT
900MHz
Transition frequency fT
6000MHz
Transistor gain gm·
ro
750V/V
Transistor gain gm·
ro
25V/V
FOM fT·
g m·
ro
675 GHz
FOM fT·
g m·
ro
150 GHz
It can be observed that the nominal supply voltage for short channel NMOS is
only one fifth of the long channel NMOS‘s, whereas the threshold voltage is decreased
from 800mV to 280mV (one third of the long channel). This leads to an incompatible
decrease of the voltage headroom (VDD-Vthn) that means the allowable signal swing
(normalized to VDD) is much smaller for short channel MOSEFTs. On the other hand,
with the same level of transconductance, the reduction of the output resistance is
tremendous, which contributes to a significant decrease of the transistor gain.
Furthermore, it needs to be noted that the process parameters listed in Table 1-2
are exemplified for educational purposes by the author of the text book [10], however
in practice, the IC designer may have to face a considerably different, often worse, set
of process characteristics. Take for example, in Table 1-3, the process adopted in this
project (ST12 CMOS, hcmos9gp), and the main features of two advanced process from
same foundry are listed. Compared with the parameters given in the Table 1-2, all these
processes have a significant higher transition frequency, with the price paid being the
reduction of transistor gain.
Introduction
6
Table 1-3 Process parameters from ST microelectronics. [14]‒[16].
ST Microelectronics
ST Microelectronics
ST Microelectronics
130nm CMOS
90nm CMOS
65nm CMOS
(st12)
(st090)
(st065)
NMOS:2.474nm
NMOS:1.777nm
PMOS:2.411nm
PMOS:1.804nm
NMOS:249.9cm2/V
NMOS:275.6cm2/V
PMOS:70.43cm2/V
PMOS:77.92cm2/V
Nominal supply voltage VDD
1.2V
1.0V
1.0V
Example transistor dimension W/L
10µm/0.13µm
1µm/0.1µm
1µm/0.06µm
Threshold voltage Vthn
0.318V(27% VDD)
0.247V(25% VDD)
0.296V(30% VDD)
Transconductance gm
6270µA/V
476µA/V
475µA/V
NMOS:5.25fF
NMOS:0.35fF
NMOS:0.34fF
PMOS: 4.48fF
PMOS:0.315fF
PMOS:0.32fF
Output resistance ro
2.17KΩ
17.99KΩ
14.84KΩ
Transition frequency fT
89.1GHz
174GHz
265GHz
Transistor gain gm·
ro
13.7V/V
8.56V/V
7.05V/V
FOM fT·
g m·
ro
1220GHz
1489GHz
1868GHz
Process Parameter
(NMOS at Typical Corner)
Gate-oxide thickness tox
Surface mobility µn,p
Gate-drain overlap capacitanceCgd
-
-
In general, a FOM (Figure of Merit) can be used to evaluate the performance of
process and this can be written as the product of transistor gain with its transition
frequency [10].
FoM  gm ro fT
(1.1)
The FOMs of each process are calculated as shown in Table 1-2 and Table 1-3. It
may be concluded that technology evolution leads to higher performance CMOS
process, since the FOM does increase from generation to generation, but it needs to be
noted that the dominant factor is the increase in transition frequency. As has been
pointed out in [12], digital circuits do benefit from this technology evolution, whereas
the analog circuit designer has to cope with the reduction of the transistor gain from
generation to generation. Therefore, as one of the preliminary goals of this project, it is
hoped to find certain solutions to effectively utilize this benefit within the design of
PLL circuits.
In addition to the above discussion, variability in process parameters is a far
greater problem in Deep sub-Micron (DSM) nodes especially as device models are
reaching their limits of predictability [17]. Due to the non-disclosure agreement
regarding this process, the details characteristics (models) of the process (st12 and
Introduction
7
st090) used for IC design in this project cannot be published in this thesis, however, the
following two simulation examples may demonstrate the influence introduced by
process variation and device mismatch.
Firstly, simply consider a diode connected NMOS device as shown in Figure 1-4,
the transistor is set to the minimum allowable dimensions which are defined by the
process model profile [14][15]. In order to find the variation introduced by process
variations, the ―simulation corner‖ is set to ―statistic‖ mode. After 2000 runs of Monte
Carlo simulation around different process corners, the drain current of this NMOS
shows a Gaussian distribution for both the st12 and st090 process. It can be observed
that the standard deviation (σ) of the drain current is about 7.5%~9% of the mean value,
which is considerable for high performance analog circuits.
Transistor dimensions(Width/Length)
ID St12: 0.15μm/0.13μm
St 090: 0.12μm/0.10μm
VDD
GND
Distribution of drain current for st12
Distribution of drain current for st 090
250
250
mean-σ
mean-σ
mean+σ
mean+σ
68.8%
68.4%
200
200
150
100
150
100
50
50
0
mean = 80.2μA
σ = 6.90μA
Number of samples
Number of samples
mean = 101μA
σ = 7.49μA
0
60
80
100
120
Drain current (μA)
(a)
140
60
80
100
Drain current (μA)
120
(b)
Figure 1-4 Distribution of drain current at different corners. (a) 130 process, (b) 90nm process
Secondly, device mismatch is another important issue that needs to be considered
during circuit design. Again, consider the diode connected NMOS circuit shown
Introduction
8
previously, where in this case, the influence of device mismatch on the variation of
drain current are of interest. Consequently, as shown in Figure 1-5, we choose the st12
process and use the ―typical‖ process corner, dimensions of three example transistors
are purposely sized at ×1, ×3, ×12 of the minimum allowable. Both the absolute value
of drain current and its variation (normalized to mean value) are plotted in Figure 1-5,
from which we can conclude that increased transistor dimensions can significantly
attenuate the uncertainty of drain current. However, the price paid for this is the
incremental at chip area.
M1
0.15 m
0.13 m
0.45 m
0.39 m
M2
VDD
VDD
M3
VDD
GND
GND
1.80 m
1.56 m
GND
180
ID-M3
Current amplitude (μA)
160
ID-M2
140
120
ID-M1
100
80
0
500
1000
1500
2000
Samples
50
Number of samples
40
σ(IDM1)/mean(IDM1)=0.041
30
σ(IDM2)/mean(IDM2)=0.019
σ(IDM3)/mean(IDM3)=0.006
20
10
0
-0.2
-0.15 -0.1
-0.05
0
0.05
0.1
0.15
0.2
Variation of drain current(Normalized to mean value)
Figure 1-5 Variation of drain current due to mismatch effect
The internal reasons leading to these variations are complex and are beyond the
specific research area of this thesis. However, the key aspect to be considered is that the
robustness of the design can be significantly degraded by these kinds of uncertainty,
which means that a certain amount of margin has to be maintained within all stages of
Introduction
9
the design. In other words, a certain degree of trade-off among the speed, chip area,
power consumption and reliability has to be carefully considered for different
applications.
Furthermore, as will be demonstrated in later chapters of this thesis, besides the
process variation and device mismatch, the topology of the layout and the uncertainty
of key environmental factors, such as temperature or the measurement platform, can
also significantly influence the design performance.
1.2.2
Difficulty of modelling noise in PLL designs
The simulation methods and modelling approaches applied to PLL design
continually to receive a high level of attention in different design stages. For issues of
loop stability, locking range, settling time, the loop‘s damping factor (ζ), natural
frequency (ωn) and bode plot of open loop transfer function, existing theory and models
have been comprehensively discussed in the literature [4][10][59][60][63]. A brief
description of these parameters is illustrated in section 2.2.
On the other hand, for the issue of signal purity prediction, which can be
characterised in the dimensions of ‗phase noise‘ in frequency domain and ‗jitter‘ in
time domain, a truly efficient and fully-developed modelling approach is still under
investigation by many researchers. For example, as demonstrated later in chapter 3, the
PLL behaves as a low pass filter for the noise that originates from the charge pump and
loop filter. In contrast, for the noise generated from the VCO, the PLL behaves as a
high pass filter. Therefore, to attenuate properly all the noise sources within the system,
the selection of PLL loop bandwidth become a critical issue for the circuit designer.
However, this selection is often compromised, since it is very difficult to efficiently
model all the noise sources, including device internal noise and any external
interference effects within the PLL loop.
Some previous work [63][65] does focus on modelling PLL noise at a
behavioural level, however the problem with this approach is that a simple link
between the modelled noise and the choice of circuit topology and transistor sizes was
not been given. For example, the behavioural model may indicate to the designer that to
satisfy certain design specification, the gain of VCO should less than, say, 1GHz/V, but
the
gap
between
this
numerical
result
to
the
final
transistor
size(e.g.
Width/Length=1000nm/130nm) has to be filled by the designers experience and a
Introduction
10
tremendous amount of transistor level simulation. People may consider that if
extremely long simulation times can be ignored, a transient transistor level simulation
can display all the necessary information to the IC designer. However, the fact is that in
modern commercial simulators (e.g. Spectre), the correct noise characteristics of each
transistor are not included in such transient simulations. Therefore, the transient
simulation results of a circuit function (e.g. VCO) is noiseless, which means transient
simulation results still pose a certain degree of inaccuracy for the issue of noise
performance of a PLL. An exhaustive solution is to incorporate the noise file for each
transistor within the transient simulation, a technique known as transient noise analysis.
However, this method is physically impractical, since it requires several months of
simulation time and a huge amount of resources to finish the simulation for a realistic
circuit design.
1.3 Project motivation
Bearing all these challenges and difficulties in mind, the overall goal of this
project was to make an effective contribution in the area of PLL noise modelling and
transistor-level circuit design. The motivations can be summarised by the following
two questions:
First, based on the standard digital CMOS process (e.g. st12), is it possible to
build an RC based VCO and embeds this into a PLL that still satisfies the requirements
of typical RF applications and advanced digital functions? If the answer is ―yes‖, what
kinds of circuit topology needs to be adopted for this to be viable? If the answer is
―no‖, the subsequent question is whether this goal can be achieved in the future given
the expected evolution in CMOS technology, and how to close is the gap between the
RC based approach and the existing popular LC based approach?
Secondly, in order to satisfy the critical requirements of signal purity, other
design performances may have to be somehow compromised. The question is can the
trade-offs be quantified between a variety of different kinds of design parameters, such
as operation frequency, signal purity, VCO gain, PLL loop bandwidth and reference
signal frequency, through the use of an advanced behaviour model?
Introduction
11
1.4 Project contribution
To address the motivations described in the previous section, the research starts
from an in depth review of existing PLL designs and VCO noise models with a focus
on the use of low cost standard digital processes. The methods and designs, which may
enhance the performance limitation of the RC based VCO, have been analysed and
compared and the main contributions can be summarized as follows:

Based on the analysis of existing designs, an improved ring oscillator
topology is proposed that has a wider frequency tuning range.

Using this new delay cell topology and with knowledge of existing ring
oscillator noise models, a new time domain based modelling approach is
created to understand in detail the noise behaviour of ring oscillators. It is
hoped this new modelling approach can accurately quantify the trade-off
between noise performance and selection of PLL loop bandwidth leading
to insight into the transistor sizing decision.

Using this new VCO model in the PLL design, providing the precondition
that a proper selection can be made of the PLL loop bandwidth; some
experimental work is undertaken on the suppression of charge pump
mismatch. Final simulation results prove that the proposed new approach
could be extraordinarily effective for the suppression of the reference
spur.

Furthermore, the mathematical theories behind this proposed approach are
analysed, from which a novel PLL structure is obtained. Confirmed by
design examples and the necessary simulation results within all design
stages (behavioural, schematic, post-layout), it is believed that this
proposed new PLL structure can contribute to a revolutionary change to
the area of advanced clock generation circuit.

Finally, many different potential research topics and design directions are
illustrated and discussed, from which we may forecast a bright future
when this new PLL is realized within commercial IC products in the
future.
Introduction
12
1.5 Thesis outline
The structure of the thesis is shown graphically in Figure 1-6. Initially, a
thorough review is undertaken into the areas of design. Some fundamental background
knowledge and circuit functions, such as: current mirror, DC biasing, band gap
reference (BGR), amplifier, operational-amplifier (Op-Amp), are reviewed and
introduced in Appendix A. While some of this material is relatively well known, in this
thesis, it is essential to have well defined implementations of these circuit blocks that
will be used throughout the designs later in the thesis. All these functions are
demonstrated with simulation results based on the st12 process.
Chapter 2 focus on fundamental theory of the VCO and PLL.
In chapter 3, a full literature review is presented on the existing designs and
mathematical models of PLL and RC based VCOs. In particular, two of those most
recent VCO noise models are derived. This in itself is a contribution to the knowledge
of how the noise model can be used as a critical design parameter.
In chapter 4, the topology of a proposed new delay cell is presented together with
the simulation and measurement results within a frequency band. Both the positive and
negative aspects of the measurement results are illustrated together with necessary
discussion.
In chapter 5, measurement results of the first fabrication run ―chip 1‖are further
analysed, from which an improved behavioural model of the proposed ring oscillator is
derived. The model is introduced from the modelling of each transistor‘s individual
noise contribution to the total VCO‘s voltage/frequency tuning behaviour. In order to
prove the validity of the proposed model, another chip was fabricated. On this second
run, different measurement approaches were introduced and testing results were
compared.
In chapter 6, the utilization of this new VCO model is discussed by embedding
this new model in a PLL design procedure. The trade-off between PLL loop bandwidth
and noise suppression is demonstrated. Specifically, the focus is on the in-band noise
suppression; some experimental ideas and the consequent results are discussed in a
variety of perspectives. A novel method is proposed that can totally remove the first
reference spur from the final PLL output signal. Schematic level realization of this new
approach also shows an impressive improvement in the signal purity, from which we
Introduction
13
conclude that all existing PLL/frequency synthesizers could benefit from this new noise
suppression technique.
Furthermore, in-depth analysis of this novel model has led to the invention of a
novel PLL structure, for which the improvements of the PLL‘s noise performance is no
longer the primary task, but the elegance of the mathematical mechanism behind this
new structure becomes the key issue. Both behavioural level and post-layout level
simulation results are demonstrated with careful consideration to design robustness.
Review of fundamental building
blocks
(Appendix A)
Introduction of VCO
(section 2.1)
To achieve the frequency controllability and
stability of the VCO, the PLL is introduced
Introduction of PLL
(section 2.2)
To obtain a deep understanding about the PLL
Literature review of PLL and PLL
noise modeling
(section 3.1)
To correctly characterize the PLL noise
performance, the VCO’s noise model need to be
reviewed
Literature review of RC based VCO
(noise modeling and topology)
(section 3.2)
Propose an improved VCO
topology
(Chapter 4)
Based on the knowledge of existing VCO noise
model and proposed new VCO topology
Propose an novel noise aware
VCO model
(Chapter 5)
Embed the proposed noise aware VCO model
within a PLL model
Propose an comprehensive PLL
model
(section 6.1)
Further deep analysis and research by using the
proposed new PLL model
Propose an new PLL structure
(section 6.2)
Figure 1-6 Thesis outline
Introduction
14
Due to the time limitations of this PhD project, many potential ideas and research
tasks based on the proposed new VCO model and PLL structure are proposed for future
work. All of them are illustrated and discussed in chapter 7.
1.6 Publications
During the course of this research, a number of refereed papers have been
published these are listed below:
Li, K., Wilcock, R. and Wilson, P. ―Improved 6.7GHz CMOS VCO Delay
Cell With Up To Seven Octave Tuning Range.‖ In: 2008 IEEE
International Symposium on Circuits and Systems, ISCAS, 2008.
Li, K., Wilcock, R. and Wilson, P. ―Improved Phase Noise Model for
Ultra Wideband VCO.‖ In: 2008 IEEE International Behavioural
Modelling and Simulation Conference.
Md Ali, S., Li, K., Wilcock, R. and Wilson, P. ―Improved Performance
and Variation Modelling for Hierarchical-based optimisation of
Analogue Integrated Circuits‖. In: DATE, 2009.
Fundamentals of oscillators and phase locked loops
15
Chapter 2 Fundamentals of
oscillators and phase locked
loops
In this chapter, a preliminary introduction to the fundamental concepts of the
VCO and PLL are presented. Both the small and large signal models of the VCO are
discussed and illustrated. Furthermore, commonly used design parameters are
explained with transistor level simulation results. The embedding VCOs in PLLs is
discussed and the concepts of the phase locking mechanism are explained with some
preliminary design examples. The most commonly used PLL structures (type I PLL and
type II PLL) are illustrated and compared with a variety of design dimensions.
2.1 Voltage controlled oscillator
It is often said, ―In the high frequency world, amplifiers oscillate and oscillators
don‘t‖ [4]. This begs the obvious question of ―how to make an amplifier oscillate?‖ The
answer is, often undesirable; a badly designed feedback system may lead to oscillation.
Therefore, to make an op-amp (e.g. Figure A-28 in Appendix A) become a ―badly‖
designed op-amp we could purposely remove the Miller capacitances in the amplifier,
and embed it within a negative feedback system as shown in Figure 2-1.
Fundamentals of oscillators and phase locked loops

vin

16
vout
Op_amp in
FigureA-28
500 fF
Vout (V)
1.2
0.8
0.4
0
0
10
20
(a)
30
40
Time (ns)
50
Oscillating
Vout (V)
1.2
0.8
0.4
0
Time (ns)
0
10
20
30
40
50
(b)
Figure 2-1 Step response of op-amp in Figure A-28 (a) with Miller capacitance, (b) without
Miller capacitance
When a square wave is applied at the positive input node of op-amp, ideally, a
replica version of the input should appear at the output node of op-amp, of which we
can observe in the well-designed case (Figure 2-1(a)). However, when the ―Miller
capacitance‖ is removed, from previous analysis (equation (8.41)-(8.50)), we know that
the frequency components at -180° shift are not adequately attenuated. As a result,
oscillations will occur as shown in Figure 2-1(b).
Clearly, in this research, the desire is not only for the amplifier to oscillate, but
also for it to oscillate as stably as possible, therefore, it is necessary to establish the
criteria for oscillation and how to describe the oscillation in detail.
Fundamentals of oscillators and phase locked loops
2.1.1
17
Small signal model
Starting with the ideal step response system shown in Figure 2-1, without looking
into the detailed circuit realization, it can be treated as the feedback system shown in
Figure 2-2 (a), where the following relationship can be derived:
Vout ( s )  (Vin ( s )  Vout ( s ))  H ( s)
(2.1)
Vout
H ( s)
( s) 
Vin
1  H ( s)
vin +
vx
H(s)
vout
H(s)
vin +
-
vx
vout
+
180°
360°
(a)
(b)
Figure 2-2 Feedback system
If the assumption is that for s=jω0, H(jω0)=-1, at any time, when an input signal
(vx(s)) applied on the system, its negative replica version will appear on the output
node, which is then fed back to the subtractor. When this input signal travels through
this loop many times, the amplitude of this signal, described by equation (2.2), goes to
infinity. This is the basic principle of negative feedback, where the system can oscillate
between two extreme values due to the high gain of the system
VX  Vin  H (s) Vin  H (s) Vin  H (s) Vin 
2
3
(2.2)
Generally, to maintain the above regeneration mechanism, the loop gain function
H(s) needs to satisfy two conditions, which are defined as the ―Barkhausen criteria‖.
H ( j0 )  1
(2.3)
H ( j0 )  180
(2.4)
where equation (2.3) ensures the geometric series function (2.2) does not damp and
equation (2.4) denotes the frequency dependent phase shift of 180°as it is highlighted
by the grey arrow in Figure 2-2(a). On the other hand, if the subtractor is replaced by an
adder, which means a positive feedback system is created, the frequency dependent
phase shift of 360°needs to be provided as shown in Figure 2-2(b) to compensate for
this positive feedback.
Fundamentals of oscillators and phase locked loops
18
Some additional explanation is required on the origin of the input signal vin(s). In
practice, environmental noise and internal device noise can contribute to this input
signal. In the simulation environment, we do not have these external stimuli, which can
trigger oscillation, and so it is sometimes necessary to artificially induce oscillation
using step changes or initial conditions.
2.1.2
RC based oscillator
Specifically, if an RC based design where transistors are used to perform the
voltage or current amplification, the circuit architecture need to be properly configured
so as to satisfy the above criteria.
Take for example the common source amplifier (Figure A-16), which we have
exhaustively analysed in section 0. From equation (8.33), it can be concluded that one
pole exists within this circuit, thereby providing maximum frequency dependent phase
shift for 90°, the common source stage itself exhibits a low frequency (dc) phase shift
for 180°, therefore, the maximum phase shift it can produce is 270°, which fails to
satisfy the necessary condition(equation (2.4)).
On the other hand, for the two stage amplifier shown in Figure A-21, the
achievable frequency dependent phase shift can reach 180°, but the two stage
configuration makes the system exhibit positive feedback at a dc level which requires
the frequency dependent phase shift for 360°. Therefore, this configuration is still
unable to meet the necessary conditions for the circuit to oscillate.
Finally, in a three-stage architecture such as is shown in Figure 2-3, a negative
feedback system is created where each pole contributes a 180°/3=60° frequency
dependent phase shift, which is a practical value for each stage to achieve. The transfer
function of each stage is given as -A0/(1+s/ω0), where A0 is the gain of each stage and
ω0 is the 3-dB bandwidth. The total loop transfer function for the three stages amplifier
is therefore defined as:
H ( s)  
A03
s
(1  )3
0
(2.5)
Fundamentals of oscillators and phase locked loops
19
VDD
0.15 m
0.13 m
Vct  0.4V
B
A
C
+
-
0.15 m
0.13 m
Voltage(V)
GND
1.0
0.8
0.6
0.4
0.2
0
Voltage(V)
18.80
1.0
0.8
0.6
0.4
0.2
0
Voltage(V)
18.80
1.0
0.8
0.6
0.4
0.2
0
18.80
Output waveform at node A
75.26ps
18.85
18.85
25.1ps
25.1ps
18.90
18.95
Time(ns)
19.00
Output waveform at node B
18.90
18.95
Output waveform at node C
Time(ns)
19.00
873mV
18.85
18.90
18.95
Time(ns)
19.00
Figure 2-3 Schematic of three stage ring oscillator formed by current source load inverter and
its output waveform
If each stage contributes 60°of frequency dependent phase shift, then the
frequency at which this occurs is given by:
tan 1
osc
 60
0
(2.6)
hence:
osc  30
(2.7)
To satisfy the ―Barkhausen criteria‖ defined by (2.3), the minimum requirement
of the loop gain is given by equation (2.8):
A03

osc 2 
) 
 1 (
0 

3
1
Therefore, subsititute equation (2.7) into (2.8), provided that A0  2 .
(2.8)
Fundamentals of oscillators and phase locked loops
20
Transient simulation demonstrates the above analysis. As shown in Figure 2-3,
the dimensions of all the transistors were set to the minimum allowable dimensions
(W/L=150nm/130nm) defined by the process definitions [14]. When the external
control voltage is set to 0.4V, the oscillation frequency is 13.28GHz, corresponding to
75.26ps for each oscillation period. For the phase shift between neighbouring stages, it
is expected to observe a 240°(-120°)phase shift which comes from the combination of
DC level signal inversion (180°) and frequency dependent phase shift (60°). This is
demonstrated by the simulation results shown in Figure 2-3 as well; delay times of
25.1ps (1/3rd of each oscillation period) can be clearly observed.
On the other hand, because this three stage feedback system can sustain the
oscillation, it is expected that the gain of each stage must in practice be higher than 2.
Actually, this can be proven by the small signal ac analysis results as shown in Figure
2-4, from which it can be found that at the phase shift of 120°, the corresponding ac
signal frequency is 13.2GHz and absolute value of gain is 3, which satisfies the demand
defined by equation (2.8).
210
180
Phase Shift150
(degree) 120
90
60
Gain
6
5
4
3
2
1
0
7
10
8
10
9
10
7
10
8
10
9
10
10
10
10
10
10
10
11
f=13.2GHz
Phase shift =120°
Gain≈3
11
Frequency(Hz)
Figure 2-4 Frequency response of single delay stage in Figure 2-3
In summary, therefore was can say that the ―Barkhausen criteria‖ can be utilized
as a useful design guideline potentially for transistor sizing. In other words, once a
small signal model is successfully built for certain amplifier (delay cell), it may be
expected that oscillation frequency f0 and circuit parameters gm/C can be derived using
this model, from which the transistor size can then be obtained. Some previous work
[22]-[24] have indeed used this method to explain their design. However, the fact is
that the small signal model, from which the ―Barkhausen criteria‖ are derived, is a
Fundamentals of oscillators and phase locked loops
21
linear model that is only valid over voltage and current regions where the large signal
voltage and current can adequately be represented by a straight line [4]. This model
must therefore be extended to the large signal case.
2.1.3
Large signal model
Obviously, the oscillator discussed previously is not operating within the linear
region because its output waveform has an amplitude of 0.873V (Figure 2-3) and the
power supply is 1.2V. More specifically, the lowest value of output waveform has
already dropped below the threshold voltage Vtn, below which the NMOS transistors
are working at a sub-threshold voltage.
However, continuing the linear analysis for the time being, it can be seen that
when the necessary condition for oscillation (equation(2.3)) is satisfied, after many
cycles of oscillation, the amplitude of output waveform that is defined by equation(2.2)
should approach infinity. However, clearly this never happens in the real case. Indeed,
as the output waveform‘s amplitude increases, the stages in the signal path experience
non-linearity and eventually a form of ―saturation‖ takes place, limiting the maximum
amplitude.
Therefore, a large signal model seems to be a good candidate to explain the
oscillation behaviour of those RC oscillators. In other words, for the VCO shown in
Figure 2-3, it is hoped to replace the PMOS with an effective resistor R and model the
gate capacitance of NMOS with capacitor C, Therefore, the time delay td provided by
each delay stage is given by:
td  RC
(2.9)
From the fact that signal must travel through each of N delay stages twice to
provide one period of oscillation, the oscillation frequency may be expressed as
[27][28]:
f 
1
1

T 2 N  td
(2.10)
Some previous researchers have used this model to explain the ring oscillator‘s
behaviour and start from this point to derive an oscillation frequency equation for a
specific delay cell topology. Take, for example, equation (2.11) [27]. This model has
been derived to explain the oscillation frequency of an N stages ring oscillator formed
Fundamentals of oscillators and phase locked loops
22
by common source delay cell. In this model, the R denote the effective resistance of the
PMOS and NMOS respectively. Cgdn and Cgdp are the gate-drain overlap capacitance of
NMOS and PMOS respectively; Cdbn and Cdbp denote the effective capacitance between
the drain and bulk; Cin is the input capacitance of the loading stage.
f 
1
2 N (0.8)  R  (Cgdn  Cdbn  Cgdp  Cdbp  Cin )
(2.11)
It is very difficult, however, to model precisely the effective value of Reff and Ceff
using this approach. For example, for the full voltage swing at a transistor gate implies
that the output drain current varies significantly. Therefore, the effective resistance
R=Vsw/Iss has to be assumed to be a constant value in the above equation which thereby
reduces the robustness of the model given in equation (2.11). In addition, the parasitic
capacitance as a result of the layout topology, process variations and temperature
variations in deep submicron processes degrades the accuracy of the model.
Finally, to conclude the analysis given in the previous two sections, it may be
summarized that neither the small signal model nor the large signal model can
accurately model the oscillation behaviour entirely. However, from the small signal
model, it may be concluded that any structures of a single stage amplifier can evolve
into an oscillator by properly configuring the signal feedback path. On the other hand,
the large signal model has a limitation on its accuracy due to the variation of the R and
C components. Therefore, it is essential that some other design dimensions may need to
be incorporated in the oscillator design process to accurately predict both the small and
large signal performance. Actually, as will be illustrated in Chapter 4 and Chapter 5,
the phase noise can be predicted much more accurately than the oscillation frequency.
2.1.4
Design parameters of a VCO
Besides the oscillation frequency and phase noise, there are some other important
performance parameters for a VCO such as tuning range, tuning linearity, output
amplitude and power consumption. These performance parameters are discussed in the
following subsection and simulation results of single ended current starved ring
oscillators are used to demonstrate how they affect the overall performance of the VCO.
Fundamentals of oscillators and phase locked loops
23
VDD
M9
M13
M15
M3
M5
M7
M4
M6
M8
M14
M16
M18
M17
VDD
Vp
M3
M5
M7
M4
M6
M8
Vct
M10
Vn
GND
GND
(a)
Figure 2-5 (a) Push pull inverter based oscillator (b) current starved VCO
First we consider a three-stage ring oscillator shown in Figure 2-5(a), which is
formed using push pull inverters. All the NMOS transistors are sized at the minimum
allowable size (Wn/Ln=150nm/130nm) defined by the process. In order to achieve a
symmetrical voltage transfer characteristic, all the PMOS transistors were sized to
ensure that pull up and push down paths have equal transconductance parameters,
which hence resulting in the equation:
n  W 
W 
  
 
 L  p  p  L n
(2.12)
According to the mobility parameter listed in Table 1-3 on page 6, which µn is
249.9cm2/V and µp is 70.43cm2/V, the calculated width of PMOS is 531nm. With
further simulation to compensate the difference of threshold voltage between PMOS
and NMOS, the final refined PMOS size is Wp/Lp=500nm/130nm. Furthermore, in
order to make the oscillation frequency adjustable, two cascode transistors (e.g. M13
and M14) are embedded within each push down and pull up paths respectively as
shown in Figure 2-5(b). The oscillation frequency is adjusted by varying the gate
voltage, which results in a change of the effective resistance of the circuit as suggested
by equations (2.10)-(2.11). A pair of complementary transistors with PMOS diode
connected generates those differential control voltages (Vn/Vp). Again, NMOS (M10)
is sized at the minimum allowable dimension whereas PMOS (M9) is sized at
W/L=400nm/130nm, which ensures a correct differential operation (e.g. when
Vn=0.6V, Vp=Vdd-0.6=0.6V).
Fundamentals of oscillators and phase locked loops
24
Tuning Range
From a schematic level simulation when control voltage (Vct=Vn) is at 0.6V, the
oscillation frequency is 4.19GHz. The tuning range property of this design is shown
below in Figure 2-6. The maximum oscillation frequency is 6.86GHz when Vn is at
1.2V whereas the minimum oscillation frequency is 31.93MHz. Please note that
depending on the layout quality and process variation, the realistic oscillation
frequency and tuning range may vary by a factor of up to 3[4].
Oscillation frequency (GHz)
7
6
6.86GHz
5
4
3
2
KVCO
31.93MHz
1
0
0.1
0.2
0.3
0.4
0.5 0.6 0.7 0.8
Control voltage (V)
0.9 1.0
1.1
1.2
Figure 2-6 Tuning range characteristic of current starved oscillator
As pointed out in Chapter 1, a wide bandwidth is favoured by many applications;
however, this feature may affect some other performance aspects of the oscillator. For
example, one of the most important criteria in VCO design is the noise sensitivity on
the control line. For a given noise amplitude, the fluctuation of output frequency is
proportional to the gain (KVCO) of VCO due to the fact that ωout=ω0+KVCO·Vct. If we
take the average gain (KVCO) of this design, for example, in the above case as:
KVCO 
f max  f min 6860  31.93

 6207 MHz / V  6.2MHz / mV
Vmax  Vmin
1.2  0.1
(2.13)
We can see that clearly, when any interference signal with amplitude of 1mV is
applied to the control node (Vct), the oscillation frequency of the VCO may drift 6MHz
from its original designed oscillation frequency. This problem could become more
serious in today‘s advanced processes where the supply voltage decreases even further,
meaning that this susceptibility will become even more of an issue when scaling
designs to increasingly small processes.
Fundamentals of oscillators and phase locked loops
25
Tuning Linearity
It can also be seen that the VCO gain in above example is an averaged value from
the minimum to the maximum oscillation frequency. Actually, as shown in Figure 2-6,
in the middle part of the tuning range, it shows a much higher gain than the two
extremes. This phenomenon is an aspect of non-linearity, which may seriously degrade
the settling behaviour of PLL. It could be suggested that this non-linearity may be
minimized by properly configuring the VCO structure, posing another challenge for
high performance VCO design.
Vct=0.4V
0.8
0.4
0.4
18.6
18.8
19.0
19.2
19.4 18.6
Time(ns)
18.8
19.0
19.2
Vct=0.6V
Vct=0.6V
1.2
0
19.4
Time(ns)
1.2
0.8
0.8
0.4
0.4
0
18.6
18.8
19.0
19.2
19.4 18.6
Time(ns)
18.8
19.2
0
19.4
Time(ns)
Vct=0.4V
Vct=0.8V
1.2
19.0
Voltage(V)
Voltage(V)
1.2
0.8
0
1.2
0.8
0.8
0.4
0.4
Voltage(V)
Voltage(V)
Vct=0.8V
Voltage(V)
Voltage(V)
1.2
0
0
18.6
18.8
19.0
19.2
19.4 18.6
Time(ns)
18.8
(a)
19.0
19.2
19.4
Time(ns)
(b)
Figure 2-7 Output waveform at different frequencies. (a) current source load inverter, (b)
current starved inverter
Output Amplitude
It is desirable to maintain a large output oscillation amplitude over the full
frequency band, thus making the waveform less sensitive to noise and interference.
However, in practice this is not always the case. For example, Figure 2-7 shows the
output waveform for the previous two design examples (Figure 2-3 and Figure 2-5)
with different control voltages and hence different oscillation frequencies. The example
shows how the output waveform (Figure 2-7 (b)) of the current starved ring oscillator
can sustain the same amplitude during the majority of the frequency band whereas the
Fundamentals of oscillators and phase locked loops
26
current source load inverter based design fails to keep a constant output amplitude
when the oscillation frequency is decreased (Figure 2-7 (a)).
Power Dissipation
Power consumption is a critical issue for most modern deep sub-micron IC
designs. For oscillators, power dissipation is a trade-off between the oscillation
frequency required and the phase noise. This is discussed in more detail in section
3.2.4.
Output Signal Purity
Even with a constant, noise-less control voltage and constant clean power supply,
the output waveform of a well-designed oscillator is not periodic. In fact, device noise
sources and external interference can lead to tiny fluctuations in the output phase and
frequency of the oscillator. In the time domain, this fluctuation is quantified as ―jitter‖
whereas in the frequency domain it is more commonly referred to and characterized as
―phase noise‖. To get an insight of these terminologies, it is useful to consider an ideal
sinusoidal noiseless oscillator, normally expressed as shown in equation (2.14)
Vout (t )  A cos(0t   )
(2.14)
The amplitude is given by A and the constant oscillation frequency ω0 and its average
normalized (RMS) power can be obtained as follows:
Pnorm 
1
2T

T
T
A2 cos 2 0tdt 
A2
4T

T
T
(1  cos 20t )dt 
A2
2
(2.15)
This implies that all of the power is concentrated at the carrier frequency ω0 as shown
in Figure 2-8(a):
Practical Oscillator
Ideal Oscillator
Power
Power
1Hz bandwidth
ω0
(a)
ω
ω0
(b)
Δω
ω
Figure 2-8 Output power spectrum of oscillator. (a) ideal. (b) practical
Fundamentals of oscillators and phase locked loops
27
However, when noise sources are incorporated into this ideal model, fluctuations
in amplitude and phase make the power spread into nearby frequencies around ω0
(Figure 2-8(b)). In this scenario, the output waveform may be expressed more
accurately as:
Vout  A(t ) cos[0t   (t )]
(2.16)
Where A(t) and ϕ(t) express the random fluctuations of amplitude and phase,
respectively. It has been shown in [4] that the amplitude limitation mechanism in a ring
oscillator minimizes the amplitude fluctuation and hence equation (2.16) can be
rewritten as:
Vout  A cos[0t   (t )]  A[cos(0t )cos  (t )  sin(0t )sin  (t )]
(2.17)
Normally, for a small phase fluctuation, where |(t)|<<0.01rad, some approximations
are valid, such as: cos((t))≈1 and sin((t))≈(t). Therefore, it is possible to simplify
equation (2.17) to obtain:
Vout  A cos 0t  A (t )sin 0t
(2.18)
As will be demonstrated in section 3.2, (t) may be expressed as a sinusoidal
function:
 (t )   p sin(t )
(2.19)
where Δω is the offset frequency from carrier and p is a function which symbolized all
the necessary circuit coefficients. Substitute equation(2.19) into equation(2.18):
Vout  A cos 0t  A p sin(t )sin(0t )
 A cos 0t  A
p
2
[cos(0   )t  cos(0   )t ]
(2.20)
Equation (2.20) shows that a pair of equal sideband locates at ω0Δω with a
normalized sideband power relate to centre frequency (ω0) at:
Psideband ( )   p2 / 4
(2.21)
To measure the magnitude of this sideband power and quantify the relationship
between this sideband power and the carrier power, the term ―phase noise, L  ‖ is
introduced, which is expressed in the same way as defined in[31]:
(  ,1Hz ) 
P
L   10log  single sideband 0

Pcarrier


(2.22)
Fundamentals of oscillators and phase locked loops
28
Where Psingle sideband (0+Δ, 1Hz) is the single sideband power at a frequency
offset of Δ from the carrier with a measurement bandwidth of 1Hz, and Pcarrier is the
carrier power in full bandwidth.
It is important to note that equation (2.21) and equation (2.22) are fundamentally
different. Equation (2.21) shows the normalized absolute value of sideband power at
Δω frequency as illustrated in Figure 2-8(b), whereas equation (2.22) denotes the ratio
of single sideband power at Δω frequency to the total carrier power across the full
bandwidth. When the offset frequency Δω is large enough, the total carrier power may
be approximately quantified as the grey area in the Figure 2-8(b) .This is an integral
function that is required to calculate the total power from the centre frequency (ω0) to
the offset frequency(ω0+Δω). Plotting equation(2.22), which is termed as phase noise,
it is possible to see further useful information compared to equation (2.21) as depicted
in Figure 2-9. This figure shows a simulation example of current starved oscillator
(Figure 2-5 (b)).
30
Phase Noise (dBc/Hz)
0
-30
-30dB/Decade
-60
2rd Harmonic
-61.98dBc/Hz
-90
-20dB/Decade
-120
-150
Noise Floor
3
10
4
10
5
10
6
10
7
10
Offset frequency from carrier (Hz)
8
10
9
10
10
10
Figure 2-9 Schematic level phase noise simulation of current starved VCO.
In this example, the control voltage (Vct) is set to a value of 0.6V that produces an
oscillation frequency of 4.19GHz. Therefore, as expected, two ripples at offset
frequency 4.2GHz and 8.4GHz are observed that correspond to the second and third
harmonics of the output signal. Furthermore, it is useful to note that when the offset
frequency is less than 10MHz, the roll off factor of the phase noise is -30
dBc/Hz/Decade whereas beyond 10MHz the roll off speed decreases to -20
dBc/Hz/Decade. As will be demonstrated in section 3.2, different types of noise source
may lead to different roll off factors. This can be used as a useful design guideline for
Fundamentals of oscillators and phase locked loops
29
IC designers making it essential to provide an appropriate model for these different
types of device noise.
2.1.5
LC based oscillator
Inductor-capacitor (LC) based VCO topologies are a fundamental VCO type that
must be reviewed in order to compare with the VCOs used in this research (RC). Basic
electronic knowledge tells us that when place an ideal inductor (LP) in parallel with an
ideal capacitor (CP), the resonance happens at the frequency ωp, which is given by:
P 
1
LP CP
(2.23)
Therefore, as shown in Figure 2-10 (a), when we embed this LC tank into a backto-back inverter, those noise components at resonant frequency ωp will be amplified
and the DC gain of inverter will be killed. Consequently, a practical example case
created based on the st12 process as shown in Figure 2-10 (b).
VDD
VDD
120  m
0.8 m
120  m
0.8 m
3nH
Vct
LP
CP
300  m
0.4  m
Coarse
tuning
50 m
0.8 m
Coarse
tuning
50 m
0.8 m
Tail biasing
1000 m
0.8 m
GND
(a)
(b)
Figure 2-10 Schematic of LC-VCO (a) theoretical model (b) realization with st12 process
The voltage-frequency tuning mechanism is realized by two PMOS based
varactors with their gate connected to an external control voltage (Vct). When the
control voltage changes, the effective capacitance of varactor is changed, and in turn
the resonant frequency is tuned.
The design shown in Figure 2-10 is designed to oscillate at a frequency band
around 2.4GHz, which is assigned for Bluetooth and 802.11b communication
Fundamentals of oscillators and phase locked loops
30
standards. As shown in Figure 2-11 and compared with RC based VCO phase noise
performance shown in Figure 2-9, the above LC-VCO has excellent performance in
terms of the signal purity, which can satisfy tough communication standard
requirements. Furthermore, the power consumption for this VCO is less than 1mW
under all working conditions. Compared to the RC based design shown in later
chapters, it will be shown that it is totally impossible for an RC based VCO to achieve
such an excellent noise figure together with such low power consumption.
-40
Phase Noise (dBc/Hz)
-60
-80
-127.7dBc/Hz@1MHz
offset
-100
-120
-140
-160
-180 3
10
4
10
5
6
10
10
Frequency (Hz)
7
10
8
10
Figure 2-11 Schematic level phase noise simulation of LC-VCO
Oscillation frequency (GHz)
2.5
2.45
2.4
2.35
2.3
2.25
2.2
0
0.2
0.4
0.6
0.8
Tuning voltage Vct (V)
1
1.2
Figure 2-12 Tuning range characteristic of LC-VCO
Indeed, due to the features of low noise and low power consumption, VCOs
embedded within a modern wireless transceiver tend to use the LC based design.
However, there are two major disadvantages of an LC-VCO that cannot be ignored.
First, the tuning range of the above VCO is considerably narrower than the RC
based approach. As shown in Figure 2-12, the tuning range of this VCO is about
220MHz. Such a narrow tuning range makes the robustness of the design a critical
Fundamentals of oscillators and phase locked loops
31
issue. In other words, when embedding this VCO within a PLL, considering the PVT
tolerance, another calibration loop must be incorporated to ensure the VCO can operate
within its designed frequency band, otherwise, the PLL will fail to lock. Furthermore,
one of the general requirements for modern-wireless transceivers is the capability of
multiple wireless standards, such as, software radio [88], which requires that the
transceiver can operate with most of the frequency bands shown in Table 1-1.
Therefore, to solve these problems, one of the simplest solutions is to create
coarse tuning steps as shown by grey lines in Figure 2-10. Furthermore, another
common solution is to incorporate multiple inductors within the design such as that
reported in [18]. Generally, the most effective solution is to use an SOI process, which
makes the potential of the bulk adjustable. Some examples of these kinds of approaches
are found in [61] and [67], both of which are reported for the multiple standards
capability. However, all of these solutions lead to the introduction of extra cost due to
chip area or additional process layers.
When compared with the RC based design shown in later chapters, the second
major disadvantage of LC based approach is the huge chip area. To make a fair
comparison, there is a published design reported in [61], which is also realized with the
st12-HCMOS9GP process used in this work. As shown in Figure 2-13, the reported
core area is about 600µm×600µm, which is significantly bigger than the VCO designs
reported later in this thesis. Besides this disadvantage, note that it is based on the SOI
version of the process.
Figure 2-13 Layout view of example LC-VCO reported in [61]
Fundamentals of oscillators and phase locked loops
32
Therefore, the focus of this project remains on RC based VCOs and the
investigation that certain approaches that can make a replacement of an exist design, or
say, just create another option for the wireless transceiver when the power consumption
is not a critical requirement.
2.2 Phase Locked Loop
The PLL (Phase-Locked Loop), as its name indicates, is a control system that
generates a clock signal that has a fixed mathematical relationship to a reference signal.
This clock signal could be the constant digital clock in a microprocessor; or it could be
a carrier signal in a typical RF communication system. Actually, for anywhere when
information needs to be transmitted within a certain medium, a stable and controllable
clock signal is required. At first glance, the VCO seems to be the right choice for this
task, since it shows a direct relationship between the instant control signal amplitude to
the signal frequency. However, reduced stability for the signal frequency and
susceptibility to external environmental factors are a major problem for the VCO. For
example, consider again the VCO illustrated in section 2.1 (Figure 2-5(b)) with its
tuning range characteristics shown in Figure 2-6, when the environmental temperature
is changed, its tuning behaviour shows a considerable difference from the typical case,
as illustrated in Figure 2-14.
Oscillation frequency (GHz)
8.0
− 40°C
7.0
27°C
6.0
100°C
5.0
4.8GHz
4.0
3.0
2.0
1.0
0.61
0
0
0.2
0.4
0.67
0.6
0.76
0.8
1.0
1.2
Tuning voltage Vct (V)
Figure 2-14 Tuning characteristic of current starved oscillator upon different temperatures
From simulation results, it can be found that for the same oscillation frequency,
4.8GHz, the corresponding control voltage could vary between 0.61V and 0.76V, when
the environmental temperature is changed from -40°C to 100°C. Furthermore, when
PVT variation is taken into account the real oscillation frequency could vary from its
Fundamentals of oscillators and phase locked loops
33
designed specification by a factor of 2-3. Therefore, the only practical solution is to
introduce a lock mechanism between the VCO‘s output signal to an external reference
signal (often from a crystal), and this is the purpose of the PLL. This locking
mechanism is demonstrated in Figure 1-1, and is presented again in Figure 2-15. Within
each clock cycle of the reference signal (fref), the phase difference between fref and fdiv is
compared by the PD/PFD block, the instant phase error (θe) is then filtered by the Loop
Filter (LF), after which its low frequency (DC) signal is output to the VCO‘s control
node. A corresponding output signal fvco is then divided by the frequency divider with a
programmable ratio (N), and hence forwarded back to the PD/PFD to form a loop.
Therefore, what we can conclude is that once the PLL is in lock, the frequency of the
output signal is a unique value, which is defined by the reference signal frequency and
divider ratio. On the other hand, either changing the reference signal‘s frequency or the
divider ratio can realize the controllability of the output signal frequency.
Phase/Frequency
Detector
θe
fref
PFD
Voltage-Controlled
Oscillator
Loop Filter
Phase
error
Vct
fvco
LF
Tuning
voltage
fdiv
÷N
Frequency Divider
Figure 2-15 Block diagram of Phase Locked Loop
In Chapter 1, two practical applications for the PLL were presented, one is clock
generation for digital microprocessors and the other is in an RF transceiver. Although
the detailed structure and design specifications for different applications could be
different, the basic concepts and mathematical models of the PLL in these applications
are the same. In this project, the designs are not driven into any specific application
area (e.g. microprocessor or RF transceiver), but the analysis and innovations are made
at a fundamental level. In the following two subsections, the basic concepts and open
loop/closed loop transfer functions of type I and type II PLL are introduced with
preliminary simulation results. From the comparison between these two types of PLL,
type II (charge pump) PLL is identified as the primary research target and a
comprehensive literature review of charge pump PLL is illustrated in the next chapter.
Fundamentals of oscillators and phase locked loops
2.2.1
34
Type I PLL
Within the linear model shown in Figure 2-15, the phase detector is responsible
for the phase difference comparison and outputs a signal, which depends upon the
degree of phase difference. Traditionally, as shown in Figure 2-16 and Figure 2-17,an
XOR gate is chosen to accomplish this task.
data
PD_out
dclock
VDD
0.92  m
0.13 m
data
data
dclock
1.5 m
0.13 m
1.5 m
0.13 m
datab
0.30  m
0.13 m
datab
1.5 m
0.13 m
dclockb
1.5 m
0.13 m
PD_out
0.92  m
0.13 m
dclock
data
dclockb
dclock
0.30  m
0.13 m
0.5 m
0.13 m
0.5 m
0.13 m
datab
0.5 m
0.13 m
dclockb
0.5 m
0.13 m
GND
Figure 2-16 Circuit diagram of XOR gate
data
Amplitude(V)
1.5
1
0.5
0
0
2
4
6
8
10
12
14
16
18
20
Time( ns)
dclock
Amplitude(V)
1.5
1
0.5
0
0
2
4
6
8
10
12
14
Time( ns)
16
18
20
16
18
20
Δɸ
PD_out
Amplitude(V)
1.5
1
0.5
0
0
2
4
6
8
10
12
14
Time( ns)
Figure 2-17 Simulation results of XOR gate
As can be observed in Figure 2-17, the width of the output pulse (PD_out) is
proportional to the phase difference (Δϕ) between two input signals (data/dclock). The
Fundamentals of oscillators and phase locked loops
35
output pulse is generated within each half cycle of reference signal and therefore the
maximum detectable phase difference is only π radians. Provided that the amplitude of
output pulse is VDD, the gain of phase detector can be obtained:
K PD 
VDD
(2.24)

Consequently, after this output pulse (PD_out) travels through the loop filter,
ideally, its DC component should be maintained while the high frequency components
are eliminated. For simplicity, this loop filter can be realized with a series connected
resistor (R) and capacitor(C) as shown Figure 2-18 and its transfer function can be
written as:
KF 
1
1  sRC
(2.25)
KF
KPD
ɸin
data
dclock
KVCO/s
R
VPD_out
VinVCO
ɸdclock
VCO
ɸout
C
ɸdclock= ɸout /N
÷N
Figure 2-18 Block diagram of a typical type I PLL
Next, the VCO will see this loop filter‘s output signal (VinVCO) and make an
instant adjustment on is oscillation frequency. It should be pointed out that within the
feedback loop system; ―phase‖ is the variable that indeed characterizes the system,
which means that VCO‘s transfer function should be termed with its total phase
accumulation, KVCO/s, but not its instantaneous oscillation frequency.
Therefore, for the system shown in Figure 2-18, its open loop transfer function
can be written as:
in
dclock
( s)
open
 ( K PD 
1
K
 VCO ) / N
1  sRC s
(2.26)
From equation (2.26), it can be found that one pole appears at s=-1/RC and
another pole appears at s=0. Since there is only one pole located at the origin, this type
Fundamentals of oscillators and phase locked loops
36
of PLL is termed as ―TYPE I PLL‖. Furthermore, from equation (2.1) and (2.26), the
closed loop transfer function can be written as:
in
dclock
( s)
close

K PD KVCO
s NRC  sN  K PD KVCO
2
(2.27)
From equation (2.27), it can be concluded that depending on different values of
system components (R, C, KVCO), the step response of this second order system can be
over damped, critically damped or under damped. Therefore, equation (2.27) can be
rearranged into the standard form of ζ, ωn, where ζ is the damping factor and ωn is the
natural frequency.
in
dclock
( s)
close  H ( s ) 
n2
s 2  2n s  n2
(2.28)
Where
n 
 
K PD KVCO
NRC
1
N
2 K PD KVCO RC
(2.29)
(2.30)
From equation (2.30), it is important to realize that increasing the value of R and
C will decrease the damping factor and hence make the system less stable. On the other
hand, from equation (2.25), increasing the value of R and C can decrease the loop
filter‘s cut-off frequency, which is a desirable feature for the VCO, since we want the
ripple on the control node of VCO to be as small as possible.
To make a quantitative demonstration of above theoretical analysis, we can
incorporate the VCO design shown in Figure 2-5(b) and PD design in Figure 2-16 to
create a PLL circuit. In this case, we choose a reference signal at a frequency of
150MHz, and the divider ratio N is 32. Thus, if the PLL is in lock, the VCO frequency
should be around 4.8GHz, which is almost around its centre frequency. According to
the simulation results shown in Figure 2-6 and Figure 2-14, we can estimate that the
VCO gain is about 7~8GHz/V around its centre frequency. Furthermore, in order to
ensure that the VCO can drive the corresponding load capacitance at frequency divider,
all transistor widths within the VCO circuit shown in Figure 2-5(b) are purposely
increased by a factor of 20.
Transient simulation results of the reference signal (data) and the post divider
feedback signal (dclock) are shown Figure 2-19(a)(b), from which we can observe that
Fundamentals of oscillators and phase locked loops
37
it takes about 200ns for the PLL to lock. On the other hand, it would be necessary to
point out that we set the resistor (R) within the loop filter at 400Ω and capacitor for
2pF, from which we can calculate that damping factor ζ is about 0.72. However, as
shown in Figure 2-20, a ripple signal with its amplitude at about 150mV is observed
with the control node (VinVCO) of the VCO, which is due to imperfect filtering of the
PD output signal.
1.5
Amplitude(V)
data
1.0
0.5
0
0
50
100
150
200
250
(a)
Amplitude(V)
1.5
300
Time(ns)
dclock
1.0
0.5
0
0
50
100
150
200
250
300
Time(ns)
(b)
Figure 2-19 Transient simulation results for type I PLL, (a) reference signal (b) feedback signal
after 5 stage frequency divider
1
0.9
0.8
Amplitude(V)
0.7
0.6
0.5
0.8
3.3ns
0.75
0.4
0.7
150mV
0.3
0.65
0.6
0.2
0.55
0.1
0
240
0
50
100
150
245
250
200
255
260
250
265
300
Time(ns)
Figure 2-20 Transient simulation results of type I PLL (control node voltage of VCO).
Fundamentals of oscillators and phase locked loops
38
This ripple is a problem that needs to be addressed. The designer may have to
increase the capacitor value, which indeed is a trade-off between the system stability
and high frequency suppression that is revealed by equation (2.30). If we sweep the
value of the capacitor from 0.5pF to 3pF, the simulations results shown in Figure 2-21
are observed. As expected, increasing the capacitor value does significant reduce the
ripple voltage on the control node of VCO, but makes the control loop become less
stable. Indeed, it can be observed from Figure 2-21, that when capacitor increases to
3pF, the damping factor drops to 0.589, and the control voltage oscillates, which is
unacceptable for a control system.
1.2
Amplitude(V)
Amplitude(V)
1.2
0.8
0.4
C=0.5pF
0
0
0.1
ζ≈1.44
0.2
0.8
0.4
0
0.3
Time( µs)
0.1
0.2
0.3
1.2
0.8
0.4
ζ≈1.206
C=1pF
Amplitude(V)
Amplitude(V)
0
Time( µs)
1.2
0.8
0.4
ζ≈0.645
C=2.5pF
0
0
0
0.1
0.2
0.3
0
Time( µs)
0.1
0.2
0.3
Time( µs)
1.2
0.8
0.4
C=1.5pF
ζ≈0.833
Amplitude(V)
1.2
Amplitude(V)
ζ≈0.72
C=2pF
0.8
0.4
ζ≈0.589
C=3pF
0
0
0
0.1
0.2
Time( µs)
0.3
0
0.1
0.2
0.3
Time( µs)
Figure 2-21 Control node voltage of VCO (VinVCO) with loop filter‘s cut-off frequency sweep
Finally, to make a summary, there are two major problems for the type I PLL:
First, the maximum detectable phase difference is only about π radians, hence the
PLL can only acquire lock within a small range. Normally, this ―acquisition range‖ is
roughly equal to the loop filter‘s cut-off frequency (1/RC)[4] and to solve this problem,
a detector, which can detect frequency and phase difference simultaneously is required.
Secondly, the trade-off between the loop stability and ripple voltage filtering at
the VCO‘s control node limit its usefulness in high performance applications. To solve
Fundamentals of oscillators and phase locked loops
39
this issue, additional poles are required, and a typical solution is the charge pump PLL,
which can be classified as a type II PLL.
Before entering into the dedicated analysis of the type II PLL, some explanation
needs to be made for the frequency divider chain in the above example. To generate a
divide ratio for 32, 5 stages of frequency divider (divide by 2) are necessary. Normally,
the TSPC (True Single-Phase Clock) divider [10] is the most frequent choice due to its
simplicity and capability of high frequency operation. Its circuit topology and
simulation results with input clock signal at 4.8GHz are shown in Figure 2-22.
However, the TSPC divider keeps previous clock cycles by storing the voltage level on
its internal parasitic gate capacitance, and this charge will leak with time. Therefore,
there is a lower limitation of frequency band that TSPC can handle [71].
VDD
clock
0.60  m
0.13 m
0.50  m
0.13 m
0.50  m
0.13 m
0.60  m
0.13 m
0.30  m
0.13 m
0.30  m
0.13 m
0.15 m
0.13 m
0.30  m
0.13 m
0.30  m
0.13 m
dclock
GND
clock
1.5
Amplitude(V)
205ps
1.0
0.5
0
271
271.5
272
272.5
Time(ns)
dclock
Amplitude(V)
1.5
410ps
1.0
0.5
0
271
271.5
272
272.5
Time(ns)
Figure 2-22 TSPC frequency divider and its simulation results
Consequently, for some special circumstance that the reference signal applied to
PLL has a very low (<10KHz) frequency, within the chain of a N stage frequency
divider, the master-slave D flip-flop (shown in Figure 2-23) may be a more reliable
Fundamentals of oscillators and phase locked loops
40
choice for those divider stages needed to work in the low frequency band. On the other
hand, it need to point out that there is limitation of the maximum operation frequency
that master-slave D flip-flop can handle with. According to simulation, based on st12
CMOS process, the maximum operation frequency of the master-slave D flip-flop is at
about 1.1GHz (clock signal).
D
clock
clk
dclock
Q
Q
D
Q
clk
Q
Figure 2-23 Block diagram of D flip-flop
2.2.2
Type II PLL
As its name points out, the type II PLL contains two poles at the origin of its open
loop transfer function. Bearing in mind that one pole at the origin comes from the
VCO; the generation of the other pole is the key issue for this type of PLL. Generally,
we know that a current integrated on a capacitor can give a pole at the origin,
furthermore, when this current is controllable and can instantly reflect the
phase/frequency difference information, a feedback control loop system is then created.
Actually, this is the general principle of a charge pump PLL that is widely realized
within various kinds of applications.
As shown in Figure 2-24, the block diagram of a type II PLL is illustrated. A
Phase Frequency Detector (PFD) is expected to dynamically detect both the phase and
frequency difference between reference signal (data, ϕin) and feedback-divided signal
(dclock, ϕdclock). Unlike the type I PLL, in this case, between the PFD and the loop
filter, a charge pump is inserted to convert the frequency/phase difference information
Fundamentals of oscillators and phase locked loops
41
from a voltage signal into a current signal. For simplicity, we can assume the amplitude
(Ipump) of current is defined by the current source/sink functions that were discussed in
section A. Consequently, if the PFD and charge pump are treated as a whole, the
transfer function can be obtained as:
K PFD _ I 
I pump
(2.31)
2
Ipump
KPFD
ɸin
KF
up
data
KVCO /s
VinVCO
PFD
ɸdclock
dclock
VCO
ɸout
R
down
C2
C1
Ipump
ɸdclock= ɸout /N
÷N
Figure 2-24 Block diagram of a typical charge pump PLL
Furthermore, it is not difficult to write down the transfer function of loop filter in
Figure 2-24:
KF 
sRC1  1
s RC1C2  s(C1  C2 )  1
2
(2.32)
In general, C2 is set at about one tenth (or even less) of C1 [10], equation (2.32)
may be further simplified to:
KF 
sRC1  1
sC1
(2.33)
Therefore, the open loop transfer function of type II PLL depicted in Figure 2-24
is:
H open ( s) 
in
dclock
( s)
open
 ( K PFD _ I 
sRC1  1 KVCO

)/ N
sC1
s
(2.34)
Following the approach that has been illustrated in the type I PLL, the closed loop
transfer function is obtained:
H close ( s ) 
in
dclock
( s)
close

K PFD _ I KVCO ( sRC1  1)
K
K R K
K
s 2  s( PFD _ I VCO )  PFD _ I VCO
N
NC1
Consequently, the natural frequency and damping factor are obtained:
(2.35)
Fundamentals of oscillators and phase locked loops
n 
 
K PFD _ I KVCO
NC1
n
2
 RC1 
R
2

42
I pump KVCO
(2.36)
2 NC1
I pump KVCOC1
(2.37)
2 N
Compared with the damping factor illustrated in equation (2.30) for the type I
PLL, the advantage of the type II PLL is that increasing values of R and C will not
decrease the system stability. To demonstrate this advantage more clearly, a design
example is created, which has a similar specification of that type I PLL shown in
previous section.
Firstly, the PFD is realized with the structure [10] shown in Figure 2-25, while its
simulation results are shown in Figure 2-26.
up
data
PFD
dclock
down
data
up
reset
down
dclock
Figure 2-25 Implementation of PFD
data
1.5
Amplitude(V)
Amplitude(V)
Fundamentals of oscillators and phase locked loops
1.0
0.5
0
25
30
35
40
1.0
0.5
0
30
35
0
25
40
45
30
35
1.0
0
0.5
0
35
40
45
25
30
35
50
1.5
Amplitude(V)
Amplitude(V)
down
0.5
0
30
35
50
40
45
50
40
45
50
1.0
0.5
0
25
30
35
Time(ns)
1.0
25
45
up
Time(ns)
1.5
40
6.66ns
Time(ns)
Amplitude(V)
Amplitude(V)
up
30
50
0.5
50
1.0
25
45
1.5
Time(ns)
1.5
40
Time(ns)
dclock
1.5
25
5ns
0.5
50
Amplitude(V)
dclock
Amplitude(V)
45
data
1.5
1.0
Δɸ
Time(ns)
43
40
45
50
1.5
down
1.0
0.5
0
25
30
Time(ns)
35
Time(ns)
(b)
(a)
Figure 2-26 Simulation results of typical PFD. (a) same frequency with a constant phase
difference, (b) different frequency
In the Figure 2-26(a), the signal data and dclock have same the frequency, but
with a constant phase difference Δϕ, therefore, as illustrated in simulation results, an
output pulse with width equal to Δϕ appears at output node down that indicate dclock
leads data by a phase Δϕ. On the other hand, as demonstrated in Figure 2-26(b), when
signal data has a higher frequency than dclock, the pulse only appears at node up to
indicate this difference.
Secondly, for the realization of a charge pump, we simply use the current source
and current sink that have been created within the cascode op-amp design (Figure
A-27). In this example, the amplitude of charge pump current is chosen to be 100µA.
With some necessary transistor size adjustment, the schematic of charge pump is shown
in Figure 2-27.
Fundamentals of oscillators and phase locked loops
44
VDD
Ipump
up
2.50 m
0.13 m
VinVCO
down
Vbias1
76.0 m
0.13 m
Vbias2
76.0 m
0.13 m
1.0 m
0.13 m
Vbias3
36.0 m
0.13 m
Vbias4
36.0 m
0.13 m
Ipump
GND
Figure 2-27 Schematic of an example charge pump
Finally, let us incorporate the above PFD and charge pump into the PLL structure
shown in Figure 2-24, while the VCO and frequency divider still have the same
topology as they are in type I PLL. In order to make the loop more stable, the target
damping factor is specified as 1. Therefore, the component values within the loop filter
are obtained as: C1=9pF and R=4.5kΩ, C2=0.45pF, which gives ζ=0.99. Actually, it
can be seen from equation (2.36) and (2.37), that the natural frequency and damping
factor is a function defined by the charge pump current (Ipump), loop filter (R and C) and
VCO gain (KVCO). Different combinations of these values can give the same damping
factor, however, as will be illustrated later in this thesis, choice of these design
parameters can make a significant difference at other design specifications. Designers
may have to experiment with these variables to ensure the system can sustain stability
over a variety of design scenarios.
Fundamentals of oscillators and phase locked loops
45
0.9
Amplitude(V)
0.8
0.7
0.6
0.6748
0.5
0.6746
0.6744
0.4
0.6742
0.3
0.674
0.6738
300
0.2
0.1
0
100
200
305
310
315
320
325
330
300
400
Time(ns)
Figure 2-28 Control node voltage of VCO (VinVCO) within type II PLL example
Simulation results demonstrate the loop stability. As shown in Figure 2-28, the
control node of VCO quickly converges to a constant level after about 250ns. Looking
at the details of the simulation results, it seems the ripple voltages from the charge
pump are totally removed by the loop filter. The existing small fluctuations on control
voltages are due to the oscillation signal coupling from VCO, the same as the
oscillation frequency.
2.3 Summary
The result shown in Figure 2-28 seems to yield a PLL which works well in terms
of loop settling time and stability. However, the noise performance of this PLL has not
yet been mentioned, or considered within the design procedure. From the analysis in
section 2.1, it has been shown that the VCO itself can introduce noise to the output and
to the PLL control loop, however, whether the PLL can calibrate these noise, or how
much of this noise the PLL can overcome has not yet been considered. Furthermore, it
is known that each component within the PLL will contribute a certain amount of noise
(e.g. white noise from resistor), and how to define their influence on the total PLL
noise performance is another issue that needs to be investigated.
Fundamentals of oscillators and phase locked loops
46
In certain applications where noise is not an important issue for design
specifications, the robustness of the above PLL still poses a strong concern. For
example, it has been shown in Figure 2-14, that the gain of the VCO could vary by a
factor up to 8 due to the environmental temperature changes and instantaneous control
voltage tuning. This means the damping factor ζ, defined by equation (2.37), could vary
by a factor of 2√2, and the total control loop may become unstable. When incorporating
all PVT variation factors, the robustness of a PLL could be a serious issue for the IC
designer.
Bearing all these issues in mind, the next chapter gives an in depth review and
analysis of PLL design, presenting a methodical approach that focuses particularly on
the noise analysis of RC based oscillators, from which an important weakness of
existing designs will be identified and later resolved in this thesis.
PLL literature review, noise theory and analysis
47
Chapter 3 PLL literature review,
noise theory and analysis
In this chapter, a comprehensive analysis for each component within the charge
pump PLL illustrated in Figure 2-24 is presented, together with a review of the
performance enhancement approaches that have been proposed in recent research.
Furthermore, to treat the PLL as whole system, several approaches for creating a PVT
tolerant and adaptive bandwidth PLL are analysed. The literature review starts from the
analysis of traditional PLL noise prediction approaches and leading to the introduction
of reported noise-minimization techniques. From this review, it is found that a
comprehensive transistor level noise model is essential for a PLL design, and hence the
research is focussed on the most critical component of PLL —VCO.
3.1 Literature review of charge pump PLL
Before going into detailed transistor level analysis, it is useful to undertake a
review of the charge pump PLL (Figure 2-24‒Figure 2-28) demonstrated in Chapter 2.
Generally, for the issue of loop stability, two rules of thumb [72] are considered as
design guidelines. They are, the loop bandwidth ―must‖ be less than 1/10 of the
reference frequency and damping factor ζ is preferred to be 1.
From the simulation results shown previously in Figure 2-14, it can be roughly
estimated that the gain of the VCO is in the range of 7GHz/V to 8GHz/V, when it
operates at 4.8GHz. If the charge pump current is chosen to be at the level of 100µA,
the value of the capacitor and resistor embedded in the loop filter can be obtained from
equation (2.35) to (2.37). As shown in Figure 3-1, from the bode plot of the PLL‘s open
PLL literature review, noise theory and analysis
48
loop transfer function (as defined by equation (2.34)), the unity gain frequency can be
found to be about 15MHz and the top level PLL specifications are summarized in Table
3-1.
Magnitude (dB)
100
50
15MHz
0
-50
Phase (deg)
-100
-90
-120
-150
-180
5
10
6
10
7
8
10
10
Frequency (Hz)
9
10
10
10
Figure 3-1 Bode plot of open loop transfer function of charge pump PLL in chapter 2
Table 3-1 Specifications of charge pump PLL in Chapter 2
Reference frequency fref
150MHz
Divider ratioN
32
Loop bandwidth
≈15MHz
Natural frequency ωn
≈7.8MHz
Damping factor ζ
≈1
Gain of VCO KVCO
7~8GHz/V
In band phase noise level
Unknown
Reference spur level
Unknown
Ripple voltage at VCO control node
Unknown
It is helpful at this stage to give some explanation for the last three items in Table
3-1. Obviously, until this stage, the noise performance of the PLL has not yet been
discussed, but clearly the ripple voltage at VCO control node can be observed directly
from the simulation results shown in Figure 2-28. However, as will be demonstrated in
Chapter 6, the PLL, which indeed is a dynamic control system, should respond to any
noise and interference within the system simultaneously. More specifically, an ideal
PLL should able to respond to the phase difference between the reference signal and
feedback signal due to the noise or interference, and then make an immediately
correction to this phase difference. Besides this, it is hoped that the amount of phase
PLL literature review, noise theory and analysis
49
correction is exactly equal to the phase difference. Therefore, we can conclude that a
ripple voltage on the VCO control node will always be present, but the amplitude of the
ripple voltage should be well controlled.
However, why does the control voltage shown in Figure 2-28 look clean (besides
the ac coupling from VCO)? Does this mean that the PLL shown in Figure 2-24 is
totally locked without any phase difference?
3.1.1
Dead zone cancellation of phase frequency detector
To answer these questions, let us further investigate the input and output signals
of the PFD shown in Figure 2-25, in particular its operating conditions in an in-locked
state are of interest. As shown in Figure 3-2 (a), when the PLL is locked, both the up
and down nodes of PFD stay at a logic low level and it seems that data and dclock
signal thoroughly align with each other. However, when zooming into one of the falling
edges of the data and dclock, as shown in Figure 3-2(b), it is found that about 31ps, a
considerable amount of phase difference, exists. This means when the phase difference
is less than a certain small amount (≈31ps in this case), the PFD shown in Figure 2-25
is unable to make phase error detection, and this kind of phenomenon is known as the
1.5
1.0
0.5
0
data
300
310
320
330
340
350
Amplitude(V)
Amplitude(V)
―Dead Zone‖ [4].
data
1.5
1.0
0.5
0
322.5
322.6
322.7
322.8
1.5
1.0
0.5
0
dclock
300
310
320
330
340
350
1.5
1.0
0.5
0
320
330
340
350
Amplitude(V)
Amplitude(V)
310
322.5
322.6
322.7
322.8
1.5
1.0
0.5
0
down
310
320
330
Time(ns)
(a)
323
323.3
323.4
323.5
323.1
323.2
323.3
323.4
323.5
322.5
322.6
322.7
322.8
322.9
323
323.1
323.2
323.3
323.4
323.5
323.1
323.2
323.3
323.4
323.5
Time(ns)
340
350
Amplitude(V)
Amplitude(V)
300
322.9
323.2
≈31ps
up
Time(ns)
1.5
1.0
0.5
0
323.1
Time(ns)
up
300
323
dclock
Time(ns)
1.5
1.0
0.5
0
322.9
Time(ns)
Amplitude(V)
Amplitude(V)
Time(ns)
1.5
1.0
0.5
0
322.5
down
322.6
322.7
322.8
322.9
323
Time(ns)
(b)
Figure 3-2 Illustration of ―dead zone‖ in PFD
The simplest way to solve this problem is to insert several additional inverter
stages before the reset nodes shown in Figure 3-3. Actually, the magnitude of the dead
PLL literature review, noise theory and analysis
50
zone is equal to the transmission delay through those two inverters (surround by the
dashed line), and the additional delay introduced at the reset node purposely creates a
pulse at the up and down node. As long as the width of this pulse signal is wider than
the transmission delay contributed by the two inverters, the difference of width of these
pulse signals at output nodes shows the information about instant phase difference at
input nodes.
data
up
N(N>2) stages delay
reset
down
dclock
Figure 3-3 Improved PFD for ―dead zone‖ cancellation
Actually, the PFD realized in the following design was designed with the same
principle, which eliminates the dead zone completely by generating an instantaneous
pulse signal. As shown in Figure 3-4, the PFD structure reported in [73] was chosen,
According to [73], the width of output pulse can be controlled by the M stages delay
element and the maximum operation speed is limited by the N stages delay element.
VDD
5.00 m
0.13 m
up
M(M is odd) stages delay
N(N is odd) stages delay
N(N is odd) stages delay
3.00 m
0.13 m
2.40 m
0.13 m
down
reset
M(M is odd) stages delay
dclock
data
GND
Figure 3-4 PFD realized for high speed operation
PLL literature review, noise theory and analysis
51
Some experimental simulations were made on the number of delay stages, since
the width of output pulse needs to be carefully considered. First, the width of the pulse
is preferred to be narrow to reduce the amount of charge pump flicker noise flowing
into the loop filter. Secondly, the pulse width needs to be wide enough to ensure that
the switches in the charge pump module can be thoroughly turned on or off at a
relatively high frequency. Therefore, as a compromise between these two requirements,
M and N were chosen to be M=5 and N=11 to give a pulse width of approximately
250ps. The layout of this PFD and its post layout simulation results are shown in Figure
3-5 and Figure 3-6, respectively.
Figure 3-5 Layout of PFD shown in Figure 3-4
1.4
1.0
1.2
0.5
1.0
0
100
102
104
106
108
110
Time(ns)
112
114
116
118
Amplitude(V)
Amplitude(V)
Amplitude(V)
data
1.5
120
dclock
1.5
0.8
1ps
0.6
0.4
1.0
0.2
0.5
0
100
0
102
104
106
108
110
Time(ns)
112
114
116
118
120
112.205
112.210
112.215
Time(ns)
Amplitude(V)
1.4
1.0
1.2
0.5
0
100
1.5
1.0
102
104
106
108
110
Time(ns)
112
114
116
118
120
down
Amplitude(V)
Amplitude(V)
up
1.5
0.8
0.6
1ps
0.4
1.0
253ps
0.5
0
100
0.2
0
112.24
102
104
106
108
110
Time(ns)
112
114
116
118
120
112.26
112.28
112.30
112.32
Time(ns)
Figure 3-6 Post layout simulation results of PFD shown in Figure 3-4
When running the simulation, each output node was loaded with a 0.1pF
capacitor. As can be observed from Figure 3-6, the pulse width is about 253ps and the
phase difference between the two-output pulse is 1ps. This is the same as the phase
difference that was purposely pre-set at two input nodes. Indeed, theoretically, any
amount of phase difference between the reference signal and feedback signal can be
PLL literature review, noise theory and analysis
52
detected and hence immediately be translated into the pulse width difference at the
output nodes of the PFD. Therefore, it would be interesting to see the results when this
new PFD is incorporated within the PLL design. Keeping all the other components
unchanged as they were in the previous example (Figure 2-24—Figure 2-28), the
simulation results are shown in Figure 3-7.
0.9
0.8
Amplitude(V)
0.7
0.6
≈84mV
0.5
0.4
0.3
0.2
0.1
0
100
200
300
400
Time(ns)
Figure 3-7 Control node voltage of VCO (VinVCO) after new PFD incorporated
It is surprising to find that the amplitude of ripple voltage at control node
increases to 84mV, which reveals the fact that the charge pump is unable to precisely
interpret these input pulses. The reason for this is an absence of a mismatch
cancellation function, presented in the next section of this thesis.
3.1.2
Performance enhancement
Firstly, it is necessary to explain the origin of this ripple voltage. It can be seen
that in the previous PFD (Figure 2-25) where the dead zone were not eliminated, no
ripple voltages appear at the VCO control node (VinVCO). This is because when the PLL
is locked, the output nodes of PFD are quietly stay at either logic high or logic low
level as shown in Figure 3-2. Therefore, in this scenario, the left branch of charge pump
is turned on whereas the right branch of the charge pump is turned off. As a result, all
PLL literature review, noise theory and analysis
53
the charge pump current (Ipump) flows through the left branch of the charge pump as
shown in Figure 3-8(a).
VDD
up
VDD
Vbias1
76.0 m
0.13 m
Vbias1
76.0 m
0.13 m
Vbias2
76.0 m
0.13 m
Vbias2
76.0 m
0.13 m
2.50 m
0.13 m
Ipump_P
Vcm
up
VinVCO
Ipump
down
2.50 m
0.13 m
VinVCO
Vcm
down
1.0 m
0.13 m
Ipump_N
1.0 m
0.13 m
Vbias3
36.0 m
0.13 m
Vbias3
36.0 m
0.13 m
Vbias4
36.0 m
0.13 m
Vbias4
36.0 m
0.13 m
GND
(a)
GND
(b)
Figure 3-8 Practical implementation of the charge pump: (a) without mismatch cancellation, (b)
with mismatch cancellation.
In contrast, to eliminate the ―dead zone‖ within the PFD, two complementary
reset pulses must be generated from the PFD and forwarded to the charge pump.
Consequently, within each reset pulse (≈250ps), one positive current (Ipump_p) and one
negative current (Ipump_n) are injected into/out of the loop filter simultaneously. Ideally,
if the amplitude of these two injected currents are the same, and if the P-switch
(PMOS) and N-switch (NMOS) are switched on and off with high speed clock edges,
then, the amplitude of the ripple voltage at VCO‘s control node can be maintained at its
most moderate level. However, this only happens in theory. In practice, when a certain
amount of amplitude difference exists between the pull current (Ipump_p) and push
current (Ipump_n), and when the switching behaviour of the P-switch and N-switch are
not that ideal, certain amount of unwanted charge pump current will be applied on the
loop filter and hence create a ripple voltage at the VCO‘s control node. How does the
PLL respond to this static error? Actually, if the PLL remains in lock, the average of
the VCO‘s control signal will maintain its original level as illustrated in Figure 3-7.
PLL literature review, noise theory and analysis
54
However, the PLL therefore has to create another phase error between the reference
clock and feedback clock to compensate for the existing static phase error and hence to
ensure the total current charge applied to the loop filter within each reference cycle is
zero.
To alleviate the effect of this mismatch and imperfection, the most
straightforward solution is to insert an op-amp with unity-gain configuration within the
charge pump as shown in Figure 3-8(b). This op-amp will ensure that nodes VinVCO and
Vcm have very close voltages (Ideally, same the voltage). Therefore, the common source
nodes between the left and right branch of switches could maintain the same voltage
before and after switching. To demonstrate the effects when a unity gain buffer is
incorporated, we use the wide band rail-to-rail op-amp created in section0 to perform
this task. Maintaining all the other components un-changed as they were in section
3.1.1, the simulation result is shown in Figure 3-9. It can be seen that the improvement
is significant, with a decrease of the ripple voltage amplitude from 84mV down to 8mV.
0.9
0.8
Amplitude(V)
0.7
0.6
0.5
0.680
0.4
0.678
8mV
0.676
0.3
0.674
0.672
0.2
0.1
295
0
100
300
200
305
310
315
320
300
325 330
400
Time(ns)
Figure 3-9 Control node voltage of VCO (VinVCO) after mismatch cancellation function
incorporated.
Obviously, glitches still exist in the VCO‘s control voltage, and numerous papers
[4][74]-[77] discuss the approaches to reduce the amplitude of these glitches and hence
to enhance the performance of the charge pump. However, it must be pointed out that
none of those reported approaches claim to be thoroughly effective for glitch
PLL literature review, noise theory and analysis
55
elimination across all the operating conditions. Take, for example, in [74], the high
frequency glitches are eliminated by decreasing the operational speed of the charge
pump; in [75], the charge pump will suffer from mismatch when the charge pump‘s
output voltage goes close to the rails. It seems by using the dummy switches within the
charge pump [4][77], the glitches could be somehow alleviated. However, the
phenomenon of clock feed-through is a specific problem that always accompanies high
speed digital clock switching. Besides this, in order to enhance the immunity to the
common-mode noise and supply variation, sometimes, a fully differential charge pump
is preferred. However, this will require a CMFB (Common Mode Feedback) structure
and sometimes a more complex function to suppress the differential mismatch errors.
To the best of the author‘s knowledge, the most comprehensive solution is the
design that is reported in [76], which seems to properly cover all the problems
mentioned above. It seems to provide a much optimized simulation result that seems to
remove glitches almost completely. However, it must be pointed out that there are two
important issues, which may have been overlooked within the above analysis and those
reported designs.

Firstly, the PVT variation and device mismatch. The reported charge
pump design may perform well within one simulation case (e.g. typical
corner at room temperature), but cannot maintain its best performance
over all PVT corners.

Secondly, even if the charge pump always operates at its ideal conditions,
does that mean we should expect that the output of charge pump will
always be clean? The answer is obviously: NO. It has been pointed out
previously that a PLL is dynamic control system that should be able to
respond to any amount of phase difference between reference signal and
feedback signal that is owing to noise or interference, and then make an
immediate correction to this phase difference. Therefore, what is desired
is a ripple voltage with its amplitude properly controlled, but in practice
not a total elimination of ripple voltage.
Therefore, in this work, rather than concentrating on the design and optimization
of the charge pump, it would be more useful to analyse and optimize the PLL at a
higher system level. More specifically, we do not want to state that the above reported
charge pump optimization approaches are faulted, but it must be pointed out that the
PLL literature review, noise theory and analysis
56
more important and productive job is to model properly the noise source and
imperfections which leads to a ripple voltage. Ideally, if all these noise sources and
imperfections within PLL can be quantified, then the amplitude of the ripple voltage
could be modelled accurately, and hence a new optimization approach that can enhance
the PLL‘s overall performance may be defined. Actually, as will be demonstrated in
later chapters of this thesis, this assumption becomes the primary guideline for this
project.
3.1.3
Adaptive bandwidth and PVT tolerant designs
Before starting with the noise analysis of the PLL, the basic understanding of the
lock acquisition behaviour of PLL needs to be strengthened. In other words, the
robustness of the PLL needs to be carefully considered when it is utilized in practical
applications. Within the design examples illustrated within Figure 2-24—Figure 3-9,
the reference frequency is fixed at 150MHz and the divider ratio N is fixed at 32,
meanwhile, all the simulation results are obtained with the simulation environment
setting at a typical process corner (―tt‖ for transistor, capacitor, resistor) at room
temperature. Associated with the equation (2.34)—(2.37) and existing thumb of rules,
the components values were estimated as listed in Table 3-1. However, in practical
applications, the reference frequency, or the divider ratio N could vary with a factor up
to 10, or even bigger. Therefore, according to the ―rule of thumb‖, the open loop
bandwidth of the PLL should also have the capability to change dynamically by a
factor up to 10. Otherwise, the PLL will fail to acquire lock.
Take for example, in the above design example, if the reference frequency is
required to vary between 20MHz and 200MHz, then the open loop bandwidth should
vary approximately between 2MHz and 20MHz. Furthermore, it is shown in [72] that
for a typical type II PLL, the natural frequency ωn, damping factor ζ and open loop unit
gain frequency ωc can be related by equation(3.1)
c  (2 2  1)  (2 2  1)2  1  n
(3.1)
Suppose that damping factor is fixed at 1, then the ratio of ωc/ωn can be estimated as
2.27. Therefore, the natural frequency ωn, which is defined by equation (2.36) should
vary adaptively between 880KHz and 8.8MHz. A PLL that incorporates the ability to
adaptively vary its loop bandwidth (natural frequency) can be classified into the
PLL literature review, noise theory and analysis
57
category of adaptive bandwidth PLLs. In general, the following two goals are
considered as the design targets for an adaptive bandwidth PLL:

The ratio between the natural frequency ωn and the reference frequency
should be a constant value.

The system damping factor ζ should be stable within all working
conditions.
I pump KVCO
n 
 
n
2
2 NC1
 RC1 
I pump KVCOC1
R
2
2 N
(3.2)
(3.3)
The resulting expressions of natural frequency ωn and damping factor ζ are
respectively given in equation (3.2) and (3.3). It can be found that to dynamically
change the natural frequency and damping factors, PLL designers have to create some
mechanisms that can adaptively control the charge pump current (Ipump), gain of VCO
(KVCO), resistor (R) and capacitor in the loop filter (C). Among these parameters, the
charge pump current (Ipump) and loop filter‘s resistance (R) have received the most
attention. Actually, almost all state of art PLL designs [70][78]—[84] have
incorporated the feature of adaptive bandwidth. The details of each approach may be
different, but the basic principles are the same. That is: the charge pump current needs
to proportionally increase with the increase in reference frequency and loop filter‘s
resistance needs to inversely vary with reference frequency.
In [78], a PLL using a regulated supply approach is proposed in which the charge
pump current is proportionally scaled with the VCO‘s regulated supply current (Ibias)
and loop filter‘s resistance (R) is inversely proportional to Ibias. In [79], the adaptive
control mechanism is realized with an adaptive biasing function, which indeed is biased
by the VCO‘s control voltage. Consequently, a relation between the reference
frequency and the charge pump current and small signal resistance (R=1/gm) of a diode
connected PMOS can be obtained. Similar approaches could be found in the designs
that are reported in [80]—[82]. In [85], these two approaches are summarised by a
theoretical approach, which is expressed by equation (3.4) and (3.5):
1
I pump

Tref
VCTRL
R  Tref
(3.4)
(3.5)
PLL literature review, noise theory and analysis
58
Noting that Tref=1/Fref, it can be found that these two equations are fundamentally
the same as the two principles stated above.
Some comments need to be made about the designs illustrated in [70][83][84]. In
[70], the loop filter is realized by a switch capacitor filter, in which the effective
resistance (R) is equivalent to the filter‘s switch frequency, which is in fact the
reference frequency. In [83][84], PVT tolerant PLLs are reported which must
incorporate the BGR and additional calibration function to conclude a temperature
compensation. However, what needs to be strengthened is that when a PLL is claimed
to be PVT tolerant, the capability of adaptively changing its loop bandwidth is the
primary requirement. This is not difficult to understand. Take for example, from Figure
2-14, when the temperature changes, the tuning range of the VCO will change, which
indeed directly reflects a change at the gain of VCO (KVCO). From equation (3.2) and
(3.3), it can be found that additional compensation functions should not only
compensate the VCO operation range, but also create a dynamic control function to the
charge pump current and resistor so as to ensure that the PLL always works at
optimized conditions.
The PVT tolerant PLL is not the research target of this project in itself; however,
it is useful to apply the adaptive bandwidth technique within the PLL design in this
project, which could significantly enhance the robustness and usability of the design.
To demonstrate the technique of adaptive bandwidth, we use the adaptive biasing
approach that is proposed in [79] and [84]. With some necessary modifications of the
circuit topology, the circuit schematic is shown in Figure 3-10.
PLL literature review, noise theory and analysis
VDD
Ipump
VDD
24.0 m
3.0 m
24.0 m
3.0 m
59
Adaptive Biasing
VDD
Ipump
8.0 m
3.0 m
0.5pF
5.0 m
0.13 m
up
2.50 m
0.13 m
2.0 m
3.0 m
0.5pF
0.2  m
6.0 m
GND
VinVCO
Vcm
2.0 m
0.13 m
down
1.0 m
0.13 m
35 m
6.0 m
R
0.5pF
C2
C1
8.0 m
3.0 m
GND
8.0 m
3.0 m
GND
GND
GND
GND
Loop Filter
Figure 3-10 Charge pump and loop filter with adaptive bandwidth biasing
It can be found that the VCO‘s instant control voltage (VinVCO) is utilized to
adaptively bias the current mirror, which in turn defines the amplitude of the charge
pump current. On the other hand, the effective resistor is realized with a PMOS
transistor, with its bulk and source nodes biased by the VCO‘s control voltage (VinVCO)
and gate node always tied to ground. Therefore, if the input reference signal has a
higher frequency, once the PLL is locked, the DC level of the VCO‘s control voltage
should go to a higher level as well. The adaptive biasing function will in turn produce a
higher charge pump current (Ipump), which satisfies the design guidelines denoted by
equation (3.4). On the other hand, a higher VCO control voltage will make that PMOS
overdrive voltage (VGS-Vth) become larger, which means that effective resistance (R) of
PMOS will drop to a lower value as expected by equation (3.5).
Obviously, it is impractical to expect that the PLL can maintain an exactly
constant damping factor and a fixed natural-frequency-to-reference-frequency ratio
across a variety of different conditions, but simulations could make the circuit close to
the perfect case. Take for example, firstly, five reference frequency points, which are
20MHz, 50MHz, 100MHz, 150MHz and 200MHz. With a fixed divider ratio N at 32, the
PLL‘s output frequency should be 640MHz, 1.6GHz, 3.2GHz, 4.8GHz and 6.4GHz,
respectively. From the VCO free running simulation results shown in Figure 2-14, we
can estimate that corresponding VCO‘s control voltage (VinVCO) should be 0.31V,
0.41V, 0.54V, 0.67V and 1.02V. Therefore, if it is assumed that the gain of the VCO is
PLL literature review, noise theory and analysis
60
constant (7GHz/V), and provided that the capacitor C1 is 9pF, once the charge pump
current (Ipump) and effective resistance (R) is obtained, the natural-frequency-toreference-frequency ratio and damping factor can be estimated. This can be established
by running the DC analysis of the circuit shown in Figure 3-10, with a DC source
sweeping at node VinVCO.
The final component values and transistor dimensions are shown in Figure 3-10.
The transistors within the current mirror function are sized with an extremely large
transistor length with particular concern of the transistor‘s flicker noise performance,
which will be discussed in section 3.2.
160
140
n
 0.046
ref
Ipump(µA)
120
100
n
 0.051
ref
80
n
 0.18
ref
60
n
 0.061
ref
n
 0.08
ref
40
20
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VinVCO(V)
16000
  1.61
Reff(Ω)
14000
12000
10000
  1.12
8000
  1.11
  1.02
6000
  1.05
4000
2000
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VinVCO(V)
Figure 3-11 Simulation results of charge pump current (Ipump) and effective resistance (R) with
adaptive control
Figure 3-11 plots the simulated charge pump current and effective resistance
together with the calculated natural-frequency-to-reference-frequency ratio and
damping factor at those five different control voltages. It can be observed that the
PLL literature review, noise theory and analysis
61
damping factor is always bigger than 1 and natural-frequency-to-reference-frequency is
less than 0.1 within the majority of control voltages. Finally, to validate the analysis
and calculation, we incorporate the PFD shown in Figure 3-4 and the adaptive control
module shown in Figure 3-10 with the charge pump PLL shown in Figure 2-24. As
shown in Figure 3-12, the PLL can correctly acquire lock with5 different reference
signals, which cover the frequency band between 20MHz to 200MHz.
1.2
Reference frequency
=200MHz
1.0
0.676
Amplitude(V)
0.675
0.8
2.4mV
Reference frequency
=150MHz
0.674
470
480
490
Reference frequency
=100MHz
0.6
Reference frequency
=50MHz
0.4
Reference frequency
=20MHz
0.2
0
0
200
400
600
800
Time(ns)
1000
1200
1400
Figure 3-12 Transient simulation results of an adaptive bandwidth PLL.
It seems that when the reference frequency is 200MHz, the loop‘s stability
degrades somewhat. This is because when the control voltage (≈1.0V) closes to the rail
of supply voltage, the gain of the VCO may decrease by a factor of 3-4, which can be
observed from Figure 2-14. Meanwhile, this voltage is applied as the common mode
input voltage to the op-amp, which is inserted within the charge pump. Remember that
when the input common mode voltage gets close to the rail, the op-amp shows a lower
DC gain and narrower bandwidth as has been shown in Figure A-30. Therefore, it is not
surprising that the ripple voltage is higher in this case.
When compared with the simulation results shown in Figure 3-9, it is found that
when the frequency of reference signal is 150MHz, the amplitude of ripple voltages
decreases from 8mV to 2.4mV. This is because we have purposely placed two
capacitors (0.5pF) at the common source nodes of the switches, to further suppress the
PLL literature review, noise theory and analysis
62
amplitude of the ripple voltage, as reported by [76]. Obviously, this is a considerable
improvement for the PLL‘s output signal purity, but to quantify this improvement we
must relate the PLL to the dimensions of phase noise or jitters. More specifically, as
has been discussed many times within previous sections, an approach that can correctly
characterise all the internal noise sources, external interference and all the non-ideality
within the PLL is required.
3.1.4
Noise modelling approaches
Generally, to evaluate the noise performance of a PLL, the phase noise curve of
the output signal is of interest. In the previous section, we derived the open loop
transfer function of the charge pump PLL, which indeed shows the frequency response
of output signal to the input reference signal. Therefore, following the same principle
and as shown in Figure 3-13, the noise generated by each block within the PLL can be
treated as an input signal applied to the PLL system. Consequently, using the linear
model of the PLL, the phase noise transfer function of each noise source to the output
phase noise can be derived as listed in Table 3-2. This is the most commonly used noise
modelling approach that is utilized by the PLL designer and some PLL noise analysis
tools [62].
icp_noise(s)
ɸin_noise(s)
ɸin(s)
KPFD_I
ϕvco_noise(s)
vlf_noise(s)
KF
KVCO/s
ɸdclock(s)
÷N
ϕdiv_noise(s)
ϕin_noise(s): input phase noise from reference signal
icp_noise(s): current noise associate with PFD and charge pump
vlf_noise(s): Voltage noise generate from loop filter
ϕvco_noise(s): VCO free running phase noise
ϕdiv_noise(s): phase noise generate by frequency divider
Figure 3-13 PLL linear phase noise model.
ɸout(s)
PLL literature review, noise theory and analysis
63
Table 3-2 PLL phase noise transfer function for each block
Transfer function
Noise source
Input noise from
reference
Expression
out ( s)
in _ noise ( s)
PFD and charge
out ( s)
pump noise
icp _ noise ( s)
Loop filter noise
VCO free running
phase noise
Frequency divider
noise

out ( s)
vLF _ noise ( s)
N
1  H open ( s)
H open ( s )
K PFD _ I 1  H open ( s)

Low pass
Low pass
KVCO
1
s 1  H open ( s)
Band pass
1
1  H open ( s)
High pass
VCO _ noise ( s)
div _ noise ( s)
H open ( s)
N
out ( s)
out ( s)
Type

 N 
H open ( s )
1  H open ( s)
Low pass
To examine the transfer functions listed in Table 3-2 more deeply, it is found that
two dominant factors characterize the filtering type of the noise transfer function,
which is emphasized by equation (3.6) and (3.7)
G1( s ) 
G 2( s) 
H open ( s )
1  H open ( s )
1
1  H open ( s )
(3.6)
(3.7)
Where Hopen(s) is the open loop transfer function of the charge pump PLL that has been
derived in equation (2.34). Obviously, the transfer function G1(s) that is defined by
equation (3.6) can be considered as a low pass filter, whereas transfer function G2(s)
that is defined by equation (3.7) can be treated as a high pass filter. In other words, for
the noise that originates from the input reference signal, charge pump and frequency
divider, the PLL works as a low pass filter. On the other hand, for the noise that occurs
in the VCO, the PLL works as a high pass filter. This is the reason why the selection of
the PLL‘s loop bandwidth is of great concern, since it defines the degree of noise
suppression for different noise sources.
To demonstrate the above analysis more clearly, we can substitute the design
specifications (Table 3-1) of the previous design example within section 3.1.2, into the
PLL literature review, noise theory and analysis
64
equation (3.6) and(3.7), and the bode plots (amplitude only) of these two transfer
functions are shown in Figure 3-14. When compared with the bode plot of PLL‘s open
loop transfer function shown in Figure 3-1, as expected, it is found that the two curves
intersect each other at the unity gain frequency of the PLL.
Bode Diagram
20
Magnitude (dB)
0
G2(s)
-20
-40
Loop Bandwidth
≈15MHz
-60
G1(s)
-80
-100
5
10
6
7
10
8
9
10
10
Frequency (Hz)
10
10
10
Figure 3-14 Bode plot of phase noise transfer functions in Table 3-2.
Furthermore, following the approach of the VCO noise analysis that was
discussed in section 2.1, the phase noise performance of the free running VCO
embedded in the above PLL can be extracted. Multiplying this phase noise figure with
the transfer function G2(s), the VCO‘s phase noise contribution to the PLL‘s phase
noise figure is obtained. The simulation and calculation results are shown in Figure
3-15, from which the suppression to those in-band noises can be clearly observed.
Magnitude (dB)
20
0
-20
G2(s)
-40
-60
Phase noise (dBc/Hz)
-80 5
10
-40
6
10
7
10
8
10
9
10
(a)
VCO free running phase noise
-60
PLL phase noise contributed by VCO
-80
-100
-120
-140
-160 5
10
(b)
6
10
7
10
8
10
9
10
Frequency (Hz)
Figure 3-15 Phase noise analysis of PLL. (a) transfer function of ratio between VCO phase
noise and PLL phase noise; (b) phase noise plot of VCO and its contribution to PLL
PLL literature review, noise theory and analysis
65
This is the most common noise modelling approach utilized by PLL designers
and some PLL noise analysis tools [62], commonly referred as the linear phase noise
model, or frequency domain model. However, there are three major issues when
utilizing this model in PLL design.
First of all, the above phase noise analysis illustrated from Figure 3-13 to Figure
3-15 is based on the precondition that the PLL can correctly acquire lock with
optimized loop stability. The phase noise plot can easily be obtained once the necessary
transfer function is derived, however, the transient simulations illustrated in Figure 3-9
are time consuming. It takes about 3-4 hours to run the transient schematic level
simulation to obtain the results shown in Figure 3-9, and when the simulations are
made at post layout level, it may take a few days or even longer. The problem is that
once some necessary modifications are required due to the frequency domain phase
noise analysis, transient simulation has to be run repeatedly to verify the PLL
performance. This kind of interactive design approach by combining the time domain
and frequency domain simulation are extremely time-consuming.
Secondly, one of the obvious disadvantages of the above linear phase noise
model is that non-linearity of some devices are not modelled. It has been shown in
Figure 2-6 and Figure 2-14 that the gain of VCO could vary by a factor of 3-4 at
different PVT conditions and control voltages. An effective phase noise model should
take into account this issue, although it is impractical to model the amount of linearity
variance accurately.
Thirdly, besides the phase noise performance, the level of reference spur is
another critical specification of concern to the IC designer. Especially, when the PLL is
embedded within a wireless transceiver, this unwanted spur signal will enter the mixer
and then be translated back to the band of interest. Actually, the periodic ripple voltage
appearing at VCO control node is the cause of the reference spur at the PLL‘s output
signal. Remember that VCO‘s output signal can be expressed by equation (3.8):
Vout  A cos 0t  A p sin( t )sin(0t )
 A cos 0t  A
p
2
[cos(0   )t  cos(0   )t ]
(3.8)
This equation holds its validity for the reference spur as well, where the spur signal
happens in the specific frequency band Δω=fref, and p is a function which symbolizes
the extra amount of charge applied on the VCO‘s control node, which is due to the
charge pump mismatch.
PLL literature review, noise theory and analysis
66
In previous sections of this thesis, the suppression of ripple voltage amplitude at
the VCO control voltage has been discussed several times. Actually, it is not expected
that the linear phase noise described can predict the reference spur level precisely, since
the causes of ripple voltage at the VCO control node are complex and somehow
unpredictable, however, an effective model could reveal the relationship between
different amounts of mismatch at the charge pump to the corresponding levels of
reference spur.
To overcome the above three challenges, some useful previous research [63]—
[65] has been carried out using a time domain model associated with the MATLABSimulink environment. Since the transient analysis is essential, by artificially creating a
time domain model for each block within the PLL, the phase noise curve of the PLL
can be obtained by examining the time domain output signal when the PLL is in lock.
Specifically, the different types of mismatches occurring in the charge pump can be
exhaustively modelled [64]. The non-linearity of the VCO voltage frequency tuning
characteristics can be modelled by a purposely-built look-up table function [63][65],
and those external interferences (e.g. supply noise) could also be modelled as well [63].
However, there still exist some problems when utilizing this model within the PLL
design. For example, in [63] the VCO tuning curve has been derived by simulating the
discrete VCO schematic. This implies that it still requires quite a lot of schematic level
simulation work when utilizing this model within the PLL design. On the other hand,
the VCO‘s noise performance is predefined with a fixed noise floor level and corner
frequency (between flicker noise and thermal noise). This means that the designer must
have a strong background knowledge about the VCO‘s noise performance at the circuit
topology level and relating directly to the transistor size. Meanwhile, these parameters
still require verification by schematic level simulation.
These two problems have driven the research in this project into the detailed
modelling of a VCO. Since it was decided to focus on the RC based VCO, as will be
demonstrated in Chapter 5, a RC based VCO model containing transistor sizing
information bridges the bottom level transistor sizing to the top level PLL locking and
phase noise performance.
PLL literature review, noise theory and analysis
3.1.5
67
Noise reduction methods
Before investigating the VCO‘s phase noise model, it would be useful to make a
brief review of recently reported advanced low noise PLL designs. By creating an
advanced PLL model, a deeper and more comprehensive understanding about all the
relevant noise sources that contribute to the overall PLL noise performance can be
developed, which ultimately may lead to an improved design.
The trade-off between the loop bandwidth and the in-band/out-band noise
suppression has been discussed and explained with the transfer function plot in the
previous section of this thesis. In addition to the noise suppression, another important
parameter is the loop settling time (TL), which is approximately related to the loop
bandwidth (fc) with equation (3.9)[72]:
TL 
4
fc
(3.9)
Provided that the loop bandwidth is less than 1/10 of the reference frequency.
In Table 1-1, the settling time of those commonly adopted wireless standards are
listed, all of which are at the level of >100µS. According to (3.9), this means that the
frequency synthesizer embedded in those transceivers has a loop bandwidth at about
40KHz. At such lower bandwidth, from the analysis of the VCO‘s phase noise in
Chapter 2, as a result, it seems the LC VCO is the only practical choice for those
wireless systems.
One obvious question is that why not choose to use a higher bandwidth PLL and
hence reduce the settling time. Since the transceiver cannot transmit or receive any data
during the period of frequency hopping, a shorter settling time can significantly
improve the system‘s performance. This means either the data rate of the system can be
increased or the amount of users in the same frequency band can be increased.
Ideally, if the loop bandwidth can be increased to 20MHz-30MHz, an RC based
VCO may become a suitable choice, since it seems to be practical that an RC based
VCO can achieve a phase noise level lower than -120dBc/Hz at 20MHz offset
frequency. Meanwhile, from the analysis in the previous sections, in the ideal case, all
the noise originating from the VCOs that are lower than this frequency (20MHz30MHz) may be suppressed by the PLL.
However, at such high bandwidths, the reference spurs would become the major
issue for the designer to overcome. It is because at such a high loop bandwidth, the
PLL literature review, noise theory and analysis
68
reference frequency must be in the range 200MHz to 300MHz (10 times the loop
bandwidth), which means that PFD and charge pump must able to meet this
requirement as well. In some recent reported designs [70], by using the technique of
adaptive bandwidth, the ratio between the reference frequency to the loop bandwidth
may be released to 5, but this still poses a challenge for the system integration. Take for
example, in the previous design example (Table 3-1), the loop bandwidth is about
15MHz, where the reference frequency is 150MHz. In order to minimize the mismatch
within the charge pump, one op-amp with unity-gain bandwidth 1.2GHz is adopted.
The realization and power consumption of such a wideband op-amp is often considered
to be a design challenge in itself. Even with no limitation of power consumption, what
we must point out is that this op-amp would contribute some noise directly to the
VCO‘s control node without any filtering. Note that the gain of VCO is about 78GHz/V, which is extremely sensitive to any ripple voltage or noise appearing at the
VCO‘s control node.
If the designer wants to reduce the influence of the ripple voltages on the signal
purity, there are three choices faced by designer, which are reducing the amplitude of
the charge pump current, decreasing the loop filter‘s cut off frequency, and decreasing
the gain of the VCO. However, either choice directly relates to the decrease of the loop
bandwidth, which again falls back into the trade-off between loop bandwidth and
noise/reference spur suppression.
Therefore, what must be pointed out here is that any techniques that are reported
to be effective for the PLL‘s noise reduction, must able to get rid of, or at least,
partially break, this existing trade-off between the loop bandwidth of PLL and noise
(reference spur) suppression. Generally, two commonly adopted methods are reported
to be effective for improving the PLL‘s output signal purity. The first one can be
categorized into sample-reset structure and the second is normally termed as a digitally
controlled approach.
Consider the circuit diagram shown in Figure 3-16, which is a typical example of
sample-reset filter utilized in a charge pump PLL [70]. Notice that the switch
―SHARE‖ functions only after the switches ―UP‖ and ―DN‖ are closed. Therefore, this
switch ―SHARE‖ behaves as an isolation between the instant charge pump current
integration result (Vim) and the loop filter‘s out signal (Vout+/-), which is seen by the
VCO. As a result, it is hoped that the node (Vout+/-) shows a feature of being ripple-
PLL literature review, noise theory and analysis
69
free, which is obviously desirable for reference spur reduction. A similar approach
could be found in [80] and [89], both of which are claimed to have the advantage of
low reference spurs. However, as long as the switch behaviour happens within the
filter, clock feed through is an unavoidable phenomenon within the filter. In other
words, the voltage ripple could be somehow alleviated, but it still exists due to the nonideal switching operation.
Figure 3-16 Example circuit of Charge Pump and sample-reset loop filter [70]
On the other hand, as shown in Figure 3-17, by embedding a Digital Controlled
Oscillator (DCO) in a PLL and applying a digital controller within the loop, the
reference spur problem can be significantly alleviated, since the digital control signal
applied to the VCO can be thought as a clean and stable signal.
Figure 3-17 Example circuit diagram of a digitally controlled PLL [90]
PLL literature review, noise theory and analysis
70
Some representative examples and designs can be found in [90]-[92], all of which
are talking about the realization and improvement of a digitally controlled PLL.
Actually, digitally controlled PLLs have become the most popular approach for the
local oscillator (LO) in industrial transceiver designs, to the extent that a book [6] has
been written on the subject, comprehensively addressing its design and realization in all
aspects. In this project, the claim is not to propose a new PLL structure that can be used
instead of this existing fully developed approach, but instead to propose a potentially
new research area, which will be a novel and attractive solution for low noise PLLs.
Any circuit topology poses positive and negative aspects at same time and the
digitally controlled PLL is no exception. One of the drawbacks of this approach is PVT
variation and the VCO‘s tuning linearization, which require additional specialized
calibration functions [90][92] to address. The additional calibration circuits further
increases the complexity of the system and make the realization of this kind of PLL
become one of the most challenging issues among all the functions within a wireless
transceiver.
Furthermore, it should be pointed out that the VCO core is preferred to be
realized as an LC VCO, for its excellent low noise performance. Otherwise, if an RC
based VCO approach is chosen, as has been exhaustively discussed in previous sections
of this thesis, a higher loop bandwidth must be selected to suppress noise originating
from the VCO. This is obviously a further challenge for the system integration. One of
the existing designs [91] does utilize an RC based VCO at the core of the DCO, of
which the number of delay stages are digitally controlled to provide coarse frequency
tuning. The drawback of this design approach is that power consumption is much
higher than an LC based approach.
Finally, to make a summary of the above analysis, we conclude that if we wish to
use the RC based VCO within a lower noise PLL design, two parameters are
significantly important:

First, the VCO‘s free running phase noise performance, from which the
designer could make a rough estimation of PLL‘s loop bandwidth.

Second, the gain and its non-linearity of a VCO, which significantly
influences the reference spur level of a PLL.
Either of these two parameters can be obtained by running a transistor level
simulation, but, for an efficient design methodology, these two parameters should able
PLL literature review, noise theory and analysis
71
to be roughly estimated before the design is realised at transistor level. Therefore,
bearing this purpose and all of the above PLL noise analysis in mind, an in depth
review of existing RC based VCO noise modelling approaches can be undertaken.
3.2 Literature review of RC based VCO noise models
The noise analysis of RC based VCOs starts from the most fundamental
unit−noise model of a single transistor. After that, we introduce two commonly
referenced noise models. The first one is termed as the Impulse Sensitivity Function
(ISF) based phase noise model, whilst the second one models the phase noise at the
level of transistor dimensions. From a thorough analysis and review of these phase
noise models, design guidelines can be ascertained for the effective design of VCOs,
that can be further utilized within a PLL design.
Furthermore, two existing techniques, which can contribute to significant
improvements of the oscillator performance, are introduced together with some
simulation results in the following section to demonstrate their effectiveness. Finally,
the commonly used FOM (Figure-of-Merit) term is defined and used as a standard to
evaluate and compare the most recently published designs, from which the most
competitive design — dual inverter based oscillators are chosen as the research
platform with the greatest promise for further enhancement
3.2.1
Noise model for single transistor
It is well known [32] that the flicker noise and thermal noise are the two main
sources of noise in a MOS transistor. The models of these two types of noise have been
investigated previously many times [4][10][30][33]. In standard simulation models,
such as SPICE2 [32] for example, the thermal noise is modelled as:
Sin white 
8k BTgm
3
(3.10)
where Sin is the drain current noise power spectral density (PSD), kB is the Boltzmann
constant, T is the absolute temperature in Kelvin and gm is the transconductance of
device. This model has been developed further in BSIM3v3 [32] where gm is specified
with the effective channel length Leff, effective carrier mobility µeff and total inversion
charge in the channel Qinv.
PLL literature review, noise theory and analysis
Sin  white 
4k BT eff
L2eff
72
Qinv
(3.11)
In fact, circuit designers use the model shown below in paper calculations to estimate
the thermal noise:
Sin white  4kBT  gm
(3.12)
where γ is a bias-dependent factor which may differ for different channel length.
According to [4],  is derived to be 2/3 for long channel transistors and must be
replaced by a large value for submicron MOSEFTs.
Similarly, different versions of the flicker noise model can be found in many
commercial circuit simulators/models, but the ones used for hand calculation are much
simpler. Taking SPICE2 as an example once again, the model for flicker noise can be
written:
Sin  flic ker 
K f I DS AF
(3.13)
COX Leff 2 f EF
where Kf is the flicker noise coefficient, Cox is the unit-area gate oxide capacitance, IDS
is the drain current, f is the frequency and AF, EF are the fitting parameters. The unified
flicker noise model in the BSIM3v3 model is more complex, whereas the compact
version used for hand calculation is shown in equation (3.14):
Sin  flic ker 
K f gm2
(3.14)
COX Weff Leff f
According to [20], the flicker noise coefficient Kf is a bias, process independent
parameter of the order of 10-24. In contrast, taking the model shown above, in [33], it
stated that Kf is a process and biasing dependent constant, which could be varied up to
an order of 1.5 when the minimum transistor length drop from 350nm to 130nm. To
clarify this contradiction, a simple amplifier test circuit was built as shown in Figure
3-18.
VDD
VDD
R=10Ω
+
-
10 m
0.4  m
R=180Ω
Vn2,out
I n2
+
-
10 m
0.4  m
VGS=0.9V
VGS=1.2V
(a)
R=980Ω
Vn2,out
I
2
n
+
-
10 m
0.4  m
GND
(b)
R=16.5KΩ
Vn2,out
I
2
n
+
-
10 m
0.4  m
VGS=0.3V
VGS=0.6V
GND
VDD
VDD
GND
GND
(c)
(d)
Figure 3-18 Common source amplifier including noise sources
Vn2,out
I n2
PLL literature review, noise theory and analysis
73
The transistor is configured as a common source amplifier. When there is a noise
current (In) travelling through the device channel, the induced output noise voltage can
be calculated using equation (3.15):


Kf
Vn2,out   4kT  gm 
gm2  R 2


COXWeff Leff f


(3.15)
which is the combination of equation (3.12) and (3.14). To carry out a noise analysis of
above test circuit, transistor Mn1 is sized as 10µm/0.4µm, which is large enough to
minimize the effects of dimensional variations and out-diffusion. The resistor R is
varied between 10Ω and 16.5KΩ, which simply ensures that the transistor is diode
connected (VGS≈VDS) around different biasing conditions, while the noise source of this
device is intentionally turned off during the simulation analysis. Changing the bias
voltage (VGS), the spectrum of output noise voltage at different bias conditions is
obtained as shown in Figure 3-19. Meanwhile, the noise coefficients (Kf, ) in equation
(3.15) can be adjusted, so as to make the modelling curves fit with the simulation
results.
-220
VGS=0.9V
Kf≈6.0x10-24
γ≈0.667
-240
Output noise V2/Hz (dB)
-260
VGS=0.6V
Kf≈2.9x10-24
γ≈0.667
VGS=0.3V
Kf≈0.53x10-24
γ≈0.3
-280
-300
VGS=1.2V
Kf≈8.0x10-24
γ≈0.667
-320
-340
-360
-380
1/ f
Calculation
-400
-420 3
10
Spectre Simulation
4
10
5
10
6
10
7
10
8
10
Frequency(Hz)
Figure 3-19 Output noise spectrum of single transistor
9
10
PLL literature review, noise theory and analysis
74
From results shown in Figure 3-19, it is found that the flicker noise coefficient Kf
varies from 8×10-24 to the 0.53×10-24 but basically always of the order of 10-24. In fact,
as will be shown in Chapter 5, measurement results prove that Kf≈10-24is valid for the
process we are using. For the thermal noise coefficient , it can be observed that it
depends on the different bias conditions, such that its value may differ from 0.3~0.667.
In fact, within this project, as will be demonstrated in Chapter 5, flicker noise is
considered to be the main source of noise that dominates the phase noise performance.
Indeed it has been pointed out in [32] and other previous work [20], that the
contribution of flicker noise should be carefully considered in designing RF circuits,
such as mixers, oscillators and frequency dividers that up-convert low frequency noise
to higher frequency and directly cause the phase noise to deteriorate.
3.2.2
Impulse sensitivity function model
Focussing on the flicker noise up-conversion mechanism, previous work [93]
introduces a mathematical model, which is defined as the Impulse Sensitivity Function
(ISF). This model assumes that each noise source can be considered to be an impulse
function applied to the electrical system. Therefore, an oscillator can be treated as a
system with n inputs (each associated with one noise current source i()) and two
outputs, which are the instantaneous amplitude A(t) and excess phase of the oscillator
(t). When there is an impulse function applied to such a system, the corresponding
phase fluctuation (t) in the output waveform can be described by a convolution
function, which is formed by the impulse function i() and impulse response function
h(t,) as depicted in Figure 3-20 and expressed with equation (3.16).
i(t)
0

i()
h(t,)
(t)
(t)
0
t

t
Figure 3-20 Phase impulse response model

 (t )   h (t , )i( )d

The unit impulse response h(t,) for excess phase is defined as:
(3.16)
PLL literature review, noise theory and analysis
75
(0 )
u (t   )
qmax
(3.17)
h (t , ) 
where u(t-) is the unit step and qmax is the maximum charge displacement across the
noise input node. (0) is the impulse sensitivity function (ISF), which is a
dimensionless, frequency and amplitude independent periodic function with period 2
which describes how much phase shift results from applying a unit impulse at time t=.
According to the appendix of [93], if the knowledge of an oscillator output signal
function, f(t), is provided, the ISF function of this signal can be defined approximately
using:
( x ) 
f
f   f 2
2
(3.18)
where f’ and f’’ are the first and second derivatives of the function f, respectively.
Specially, if f=cos(t), then, f’=-sin(t) and f’’=-cos(t). Therefore we can define the
Impulse Sensitivity Function (ISF) using:
(t ) 
 sin(t )
  sin(t )
sin (t )  cos 2 (t )
2
(3.19)
from which it may be surmised that the impulse sensitivity function (0) has the
same harmonic frequencies as the input signal function f(t). In fact, it was identified in
[93] that due to the periodic and frequency independent properties of the ISF function,
a Fourier series can be drawn:
(0t ) 
c0 
  cn cos(n0t   n )
2 n 1
(3.20)
Substituting equations (3.17) and (3.20) into (3.16), yields:
 (t ) 
1  c0
qmax  2

t

i
(

)
d


cn  i( ) cos(n0 )d 



n 1

t
(3.21)
This is a general function of (t) for an arbitrary input noise current i().
As a special case for the purpose of illustration, it is reasonable to suppose that
input noise is located only at frequency Δ0, which means:
i( )  I 0 cos( )
(3.22)
where I0 is the maximum amplitude of i(). Therefore, when substituting equation
(3.22) into (3.21), due to the average nature of integration, the arguments of all the
frequencies higher than 0 in equation (3.21) will be significantly attenuated, giving:
PLL literature review, noise theory and analysis
 (t )0 
I 0c0
2qmax

t

cos( )d 
76
I 0c0 sin(t )
2qmax 
(3.23)
Similarly, when the frequency components of input noise i() are concentrated at
0, i() is given as:
i( )  I1 cos[(0  ) ]
(3.24)
Substituting this equation into (3.21), it can be expected that all the other frequency
components are significantly attenuated except those frequency components close to
0. Therefore, a corresponding expression of (t) can be written as:
 (t )1 
I1c1 sin(t )
2qmax 
+(3.25)
Generally, from these two examples it can be surmised that when applying a
noise current i()=Incos[(n0+Δ)] to a system, a uniform function of (t) can be
deduced:
 (t )n 
I n cn sin(t )
2qmax 
(3.26)
Recalling that in section 2.3.4, it was assumed that (t)=psin(Δt) (Equation(2.19)).
Substituting this equation into (3.26) and rearranging for p:
( p )n 
I n cn
2qmax 
(3.27)
Subsequently, according to equation(2.21), the ratio of sideband power of the nth
harmonic to the power of the centre frequency is given by:
 I n cn 
PSBC   10log 

 4qmax  
2
(3.28)
Therefore, for a noise current with an unknown spectrum , it can be estimated that only
the noise components located at the vicinity of integer multiples of oscillation
frequency are transformed into the sideband noise PSBC{Δ}. Furthermore, it has been
illustrated in [93] that the sum of these noise contributors, each of which is weighted
by the coefficients cn, can be characterized as close-in single sideband phase noise as
depicted in equation (3.29).
  2 2 
  I n cn 

L   10 log  n 02
2
 16qmax  




(3.29)
PLL literature review, noise theory and analysis
77
More specifically, consider the case when the input noise sources are confined to
thermal noise and flicker noise respectively. For the former case, since its PSD is a
white noise distribution, the following relation can be obtained:
Sin  white 
I n2
2
(3.30)
where In is denoted as the peak amplitude of the input noise within equation (3.22) to
(3.29). Substituting equation into (3.29), yields:
L thermal


2 
S
 in  white  cn 
n 0

 10 log 
2
2
 8qmax  




(3.31)
which is the expression for white noise induced phase noise. For the flicker noise
source, as highlighted in Figure 3-19, a specific frequency point is named as the ―1/f
corner frequency‖ 1/f, at which the thermal noise band and flicker noise band intersect
each other. Below the corner frequency, the noise spectral density is inversely
proportional to the offset frequency, which may be expressed as:
Sin  flic ker  Sin  white
1/ f

(  1/ f )
(3.32)
Substituting this relation into equation (3.31), flicker noise induced phase noise is given
by:
L  flic ker


2 
S

 in  white 1/ f  cn 
n 0

 10 log 
2
3
 8qmax 





(3.33)
Owing to the fact that the frequency band of flicker noise is much lower than the
oscillation frequency in a majority of oscillator designs, only the frequency component
located in the vicinity of D.C. needs to be accounted for as highlighted by equation
(3.23). Consequently, equation (3.33) can be evolved into:
L  flic ker
 Sin  white1/ f c02 
 10log 

2
 8qmax
 3 

(3.34)
It is useful to note that the offset frequency Δ in the denominator of equation
(3.31) and (3.34) has an order factor of 2 and 3 respectively, which corresponds to
different roll off speed at -20dBc/Hz/Decade and -30dBc/Hz/Decade as has been
illustrated in Figure 2-9. In other words, the above derivations (equation(3.22)—(3.34))
PLL literature review, noise theory and analysis
78
mathematically explain the reason why the thermal noise induced phase noise has a roll
of factor of -20dBc/Hz/Decade whereas the flicker noise induced phase noise has a roll
off speed at -30dBc/Hz/Decade. Special attention needs to be paid to the point where
these two regions intersect each other as this means that the sideband power due to the
white noise given by equation (3.31) is equal to the sideband power arising from flicker
noise given by equation (3.34). Therefore, these two equations can be related and as
such they define the intersection point termed the ―1/f3 corner frequency‖, from which
the following relations can be derived:
1/ f  1/ f
3
c02

   c
n 0
(3.35)
2
n
Equation (3.35) reveals that the 1/f3 corner frequency is proportional to the
device‘s 1/f corner frequency, but with a factor which is formed by the coefficients cn.
From a circuit design perspective the goal is to minimise the numerator (ideally to zero)
which means that the flicker noise induced phase noise can be suppressed by certain
mechanisms. Coefficients c0 and cn are defined by equation (3.20), which are the
coefficients of a Fourier series of ISF function. From previous work in [93] the authors
believed that certain design guidelines could be drawn from the analysis of the ISF
function. More specifically, certain oscillators whose ISF functions have a zero D.C.
value would be favoured by circuit designers, because it seems that the flicker noise
induced phase noise can be suppressed. Previous work [29] utilized this assumption and
focussed their analysis only at thermal noise induced phase noise.
However, a problem occurs when applying these mathematical models to a real
oscillator design, since there are limited design guidelines given at the level of
configuration decision and transistor sizing for the IC designers. In [93], they
demonstrated that the D.C. (c0) level of the ISF function is highly related to the
symmetrical property of the output waveform, but it also mentions that this
symmetrical property (minimum value of c0) does not necessarily correspond to equal
transconductance ratios in pull-up and pull-down paths. The only practical design
implications are that it is necessary to use a linear load, such as resistors (formed by
poly) and linearized MOS devices. Thus, to address this problem, recently, another
stream of publications [20][39][40] proposed a new mathematical model which
attempted to directly bridge the phase noise with the transistors‘ dimensions.
PLL literature review, noise theory and analysis
3.2.3
79
Transistor sizing to phase noise
Unlike the previous model that treats the noise as an extra input to the oscillator,
this new approach highlights the time domain noise modulation mechanism, which
accompanies the oscillation behaviour. Associated with necessary mathematical
derivation, this noise modulation mechanism is transformed to a frequency domain
product, from which the IC designer can estimate the phase noise spectrum
immediately with the specified circuit parameters.
This new proposed phase noise model begins from the foundation knowledge of
previous research work..
Firstly, it utilizes the fact that the period of oscillation (T0) of a ring oscillator is
defined by the time it takes for a propagation delay (td) to propagate twice around the N
stages loop (section 2.1.3).
Secondly, without any assumptions and pre-conditions, it directly uses the
existing transistor noise model (section3.2.1).
Thirdly, the ISF based phase noise model has indicated that thermal noise
induced phase noise has a roll-off factor of -20dBc/Hz/Decade whereas the flicker
noise induced phase noise roll off is at the speed of -30dBc/Hz/Decade. This
conclusion is used within the derivation of new phase noise model.
Finally, it uses the existing mathematical models that relate RMS jitter to the
phase noise directly. The full derivation of this relationship can be found in Appendix
C.
To explain it clearly, simply consider the push-pull inverter based 5-stage ring
oscillator shown below in Figure 3-21. As has been discussed in section 2.1.4,
transistors are sized to achieve equal transconductance in push down and pull up paths
respectively
which
gives:
Wp/Lp=500nm/130nm
and
Wn/Ln=150nm/130nm.
According to the simulation results, the oscillation frequency (f0) for this example
design is 6.57GHz, which corresponds to 152ps of the oscillation period (T0).
The propagation delay, td, of the delay cell is defined as the time taken for a
change in the input node (A) to propagate to the output node (B), and this is normally
measured as the time between Vdd/2 crossing points [94]. The output waveforms at
node A and B are illustrated in Figure 3-22, from which it can be observed that a 1.52ps
propagation delay occurs that satisfies equations and (3.36)[28].
PLL literature review, noise theory and analysis
f0 
80
1
1

T0 2 Ntd
(3.36)
VDD
Mp
A
A
B
B
Mn
in
C
I
GND
Figure 3-21 Five stage ring oscillator
For simplicity, assume that within the propagation delay the amplitude of push
down current I will not change appreciably even if the NEFT (Mn) enters the triode
region and note that within this observation period, the drain voltage of Mn changes by
Vdd/2. Therefore, the propagation delay td can be expressed as:
td  RC 
Vdd
C
2I
(3.37)
where C can be modelled as the effective loading capacitances of the next stage
transistors in the design.
Amplitude(V)
Waveform at node A
T0=152.18ps
1
0.5
td≈15.2ps
0
29.7
29.75
29.8
29.85
Amplitude(V)
Waveform at node B
29.9
29.95
Time delay(ns)
1
0.5
0
29.7
29.75
29.8
29.85
Voltage(v)
29.9
29.95
Time delay(ns)
Crossing point Vdd/2
vn
Δtd
t(s)
Figure 3-22 Illustration of terms: To, td, Δ td, vn
PLL literature review, noise theory and analysis
81
However, as has been discussed in previous sections and illustrated in Figure
3-21, the noise current in which accompanies the drain current I contribute a small
fluctuation at the crossing point as highlighted by Figure 3-22. This noise current
integrates on the capacitor C over the time interval td and hence induces a voltage
fluctuation vn, which is given by:
vn 
1 td
in (t )dt
C 0
(3.38)
In addition, the time domain term, jitter (Δtd), is related to the slope of the voltage
waveform:
td 
vn
1 td
C   in (t )dt
I
I 0
(3.39)
Depending on the direction and strength of the noise current in, certain specific
fluctuations Δtd may happen ahead of or lag the ideal crossing point. However, when
this process repeats many times, the statistical result—Probability Density Function
(PDF)—displays certain meaningful information, from which the RMS jitter and
spectral density can be obtained.
Therefore, converting this definite integral to a convolution i.e. multiplying in by
a rectangular unit window wtd(t) of width td and integrating gives:
td (t ) 
1 
in ( x)  wtd (t  x)dx
I 0
(3.40)
Consequently, in the frequency domain, a multiplication product is expected which
combines the noise spectrum and the Laplace transform Wtd(s) of the rectangular
window wtd(t) .
Std ( f ) 
2
1
W
(
f
)
 Sin ( f )
t
I2 d
(3.41)
The Laplace transform of a rectangular window with width td is well known [36]:
1 0 td s 1  e std sin(td / 2)  jtd /2
Wtd ( s)  [e  e ] 

e
s
s
t d / 2
(3.42)
Its frequency response in magnitude is:
Wtd ( f )  td  sinc( ftd )  td
sin( ftd )
 ftd
(3.43)
Substituting equation (3.43) into (3.41), the spectral density of Δtd is given:
td2
Std ( f )  2 sinc2 ( ftd )  Sin ( f )
I
(3.44)
PLL literature review, noise theory and analysis
82
Since Δtd is a random variable with zero mean at the crossing point, the variance
Δtd2 is equal to average normalized power PΔtd, which can be obtained by integrating
its PSD function [37]. Therefore, the mean square value of the fluctuation of
propagation delay is given:

 2t   St ( f ) 
d
0
d
2
td Sin ( f )
 sin ( x)
td
S
(
f
)
dx

 I 2 in 0 x 2
2I 2
(3.45)
Recall that the phase noise L( f ) can be related to the timing jitter as given below
(Appendix C):

 2t  2 L ( f )
0
sin 2 ( f / f 0 )
df
 2 f 02
(3.46)
Therefore, from equation (3.45) and(3.46), the specific noise source induced phase
noise can be derived.
White noise induced phase noise
Owing to the fact, which has been demonstrated in section 3.2.2, that the
spectrum of phase noise has a roll-off factor at -20dBc/Hz/Decade when the noise
sources are dominated by the white noise, the following relation can be easily derived:
L( f ) 
Sw
f2
(3.47)
where Sw is a specific coefficient that symbolizes all the necessary parameters of the
oscillator. Substituting equation (3.47) into (3.46), the mean square value of timing
jitter can be further expressed as:
 2t  2

Sw
f2
2Sw
f 04

0


0
2S f
 w4 0
f0 

sin 2 ( f / f 0 )
df
 2 f 02

sin 2 ( f / f 0 )
df
( f / f 0 ) 2


0
sin 2 ( x)
dx
x2
(3.48)
Sw
f 03
Thus, combining the equation (3.47) and (3.48) gives
L( f ) 
 2t f 03
f2
(3.49)
Therefore, observing equations (3.45) and (3.49) together, it can be seen that once
the terms variance of single propagation delay, Δtd2, and variance of period jitter, Δt2,
PLL literature review, noise theory and analysis
83
are related, a comprehensive equation for the phase noise can be derived. Focusing on
the uncertainty of a single propagation delay Δtd2 (equation(3.45)) it can be recalled
that the spectrum of white noise Sin-white is given in equation (3.12), thus white noise
induced variance of the propagation delay can be expressed as:
 2t 
d
td 4kBT  g m 4td k BT  I

2I 2
I 2Veff
(3.50)
Furthermore, is has been pointed out in [20] that prior to the switching event the
channel resistance of FET deposits an initial noise on the capacitor. The mean square
value of the jitter is given:
 2t 
d
k BTC
I2
(3.51)
Therefore, combining equation (3.50) and (3.51) gives the total variance of a
single propagation delay:
 2t 
d
4td kBT  I kBTC
 2
I 2Veff
I
(3.52)
Where Veff= Vgs - Vth. Due to the uncorrelated relations among each FETs, when there
are N stages in a ring oscillator, shown in Figure 3-21, the total variance of period jitter
is the combination of mean square values of each pull up and push down process:
 2t  N ( 2t
d
 pullup
  2td  pushdown )
(3.53)
Assuming that the delay cell is symmetrically designed with equal
transconductance in each process means the propagation delay of each paths can be
identical (tdn=tdp=td), and the amplitude of both pull up current Ip and push down
current In are to the nominal current I .Thus, substituting equation (3.52) into (3.53) :
 2t 
NkBT 8td  I
(
 2C )
I2
Veff
(3.54)
Note that the nominal oscillation frequency f0 and propagation delay td are related
to the circuit parameters (I, C, Vdd) in equations (3.36) and (3.37) and that enables
equation (3.54) to be organized as:
 2t 
kT 4
2
(

)
If 0 Veff Vdd
(3.55)
Substituting equation (3.55) into (3.49), the single sideband phase noise due to
white noise can be derived:
PLL literature review, noise theory and analysis
L( f ) 
2kT 2
1 f0 2
(

)( )
I Veff Vdd f
84
(3.56)
Flicker noise induced phase noise
The analysis approach illustrated above can be easily migrated into the modelling
of flicker noise induced phase noise with a slight modification [39] . The primary
difference is that unlike the scenario where white noise is the dominate noise source,
the spectrum of flicker noise induced phase noise has a roll off factor at 30dBc/Hz/Decade (section 2.1.4 / section3.2.2), therefore, equation (3.47) can be
modified as:
L( f ) 
Sf
f3
(3.57)
where Sf is the specific coefficient that symbolizes all the necessary parameters of the
oscillator. Substituting equation (3.57) into (3.46) yields:
 2t  2

Sf
f3
2S f
f 04 f




0
0
sin 2 ( f / f 0 )
df
 2 f 02
sin 2 ( f / f 0 )df
( f / f 0 ) 2
(3.58)
On the other hand, when the flicker noise sources are considered as the dominant
noise source, the uncertainty of propagation delay can be given by substituting equation
(3.14) into (3.45):

2
td
K f g m2
Kf
td
td
2I 2


2 NI 2 COX Weff Leff f NI 2 COX Weff Leff f Veff2
(3.59)
Note that owing to the low frequency fluctuating rate of flicker noise, the
corresponding timing jitter displays a correlated effect around the N stages loop.
Therefore, one additional coefficient N is added in the denominator [40]. Adding the
noise effect of all the transistors while provided the equal transconductance
assumptions still hold valid, the mean square value of period jitter is given as:
 2t 
Kf
Kf
2 Ntd
(

)
NCOX Veff2 f Wneff Lneff Wp eff Lp eff
(3.60)
Note the additional coefficient 1/f, which simultaneously appears in the denominator of
equation (3.58) and (3.60). In [40], this term is considered to be a special function,
which is the inverse of low-pass filter and hence can be eliminated in both equations.
Therefore, relate these two equations and organized for Sf:
PLL literature review, noise theory and analysis
2S f
f 04


0
85
Kf
Kf
sin 2 ( f / f 0 )df
2 Ntd

(

)
( f / f 0 ) 2
NCOX Veff2 Wn eff Ln eff W p eff L p eff
2S f f 0
f 04 


0
Kf
Kf
sin 2 ( x)
1
dx 
(

)
2
2
x
Nf 0COX Veff Wn eff Ln eff W p eff L p eff
(3.61)
2S f 1 
Kf
Kf
1
dx 
(

)
3
2
f0  2
Nf 0COX Veff Wn eff Ln eff W p eff L p eff
Sf 
Kf
Kf
f 02
(

)
2
NCOX Veff Wn eff Ln eff Wp eff Lp eff
(3.62)
Finally, substitute equation (3.62) into (3.57), the SSB sideband flicker noise
induced phase noise is given as:
f 02
1
1
L( f ) 
(

)
NCOX Veff2 Wn eff Ln eff Wp eff Lp eff f 3
Kf
(3.63)
Since it was demonstrated that the flicker noise is the dominate source that
contributes to the phase noise up to a few MHz (section 2.1.4), equation (3.63) requires
more attention than equation (3.56) when the phase noise is the primary improvement
target. Specifically, equation (3.63) gives an immediate insight into the methods that
can improve the VCO phase noise. It can be seen that the factors which improve phase
noise are larger transistor dimensions (Wp, Lp, Wn, Ln), more delay stages (N) and a
greater difference between supply voltage Vdd and threshold voltage Vt (Veff=Vdd/2-Vt).
It should be mentioned that in previous work [20] the flicker noise modulation
mechanism is explained with a distinct model. Owing to the low frequency property of
the flicker noise source, push down and pull up currents that override by the flicker
noise may not fluctuate significantly over a single propagation delay td, but will vary
distinctly over many transitions. This scenario is more likely to apply low frequency
noise at the control node (say, the gate of a transistor) of the oscillator. Therefore, the
fluctuation of output frequency is directly proportional to the power of noise and the
sensitivity κV of oscillator to the noise at a specific nominal oscillation frequency.
According to [41], this relation is given as:
L( f ) =
V2
4f 2
Sin  flic ker ( f )
(3.64)
More specifically, for the N stage inverter based oscillator illustrated in Figure
3-21, its oscillation period and frequency can be written in a more accurate form:
PLL literature review, noise theory and analysis
T0 
CVdd
2
 1
1



 I N1 I N 2

2
f0 
CVdd
1
I NK

1
1


I P1 I P 2
 K 1
1 

 

 j 1 I Nj I Pj 
86

1 

I PK 
(3.65)
1
(3.66)
Where INj and IPj are the push down and pull up drain currents of jth stage of inverter
chain, respectively. Actually, for a symmetrical design, where each path‘s drain
currents INj, IPj are equal to I, equation (3.66) can be simplified into (3.36). However,
from equation (3.66), the sensitivity of f0 to the push down up current at kth stage can be
derived:
f 0
2  K 1
1


 
I NK CVdd  j 1 I Nj I Pj
CVdd f 02
f

 0
2
2 I Nk
2 NI
2
 1
 2
 I Nk
(3.67)
Thus, substituting this into equation (3.64), the single side band phase noise due
to flicker noise in the kth push down current is given as:
2
1  f0 
L( f ) 

 Si  flic ker  Nkth ( f )
4 f 2  2 NI  n
(3.68)
Finally, combining all the uncorrelated noise contributors around the loop, the
accumulated phase noise is:
2
1  f0 
L( f ) 

 N Sin  flic ker  N ( f )  Sin  flic ker  P ( f )
4 f 2  2 NI 


(3.69)
Furthermore, substituting the function of flicker noise spectrum that is given in
equation (3.14), the second version of flicker noise sources induced single side band
phase noise that is modelled from the control node noise modulation perspective is
yielded:
L( f ) 
Kf
4 NCOX Veff2
(
f2
1
1

) 03
Wn eff Ln eff Wp eff Lp eff f
(3.70)
To gain a deeper insight into the above two modulation approaches, it is found
that equations (3.63) and (3.70) contain the same coefficients which strengthen the
conclusion that has been made: factors which can improve phase noise are larger
transistor dimensions (Wp, Lp, Wn, Ln), more delay stages (N) and a greater value of
effective gate-source overdrive voltage. The only difference is the additional coefficient
PLL literature review, noise theory and analysis
87
―4‖ in the denominator of equation (3.70) that results in a 6 dB difference in the final
plot of the phase noise spectrum. Actually, as shown below in Figure 3-23, and as
further proven in chapters 4 and 5, equation (3.63) models phase noise with a higher
accuracy than equation (3.70). Based on the 5-stage push pull inverter based oscillator
that was shown in Figure 3-21, a phase noise spectrum is obtained by carrying out a
SpectreRF simulation at the schematic level, the result of which is plotted in Figure
3-23 with dark bold curve. Meanwhile, provided with the process parameters (Table
1-3) of process St12, the calculation results of the theoretical model (equation(3.63)) is
plotted in the same figure. The agreement between theory and simulation is very strong
below 10MHz offset frequency, where the phase noise is dominated by the flicker noise
sources.
Flicker noise induced phase noise of 5 stages ring oscillator
30
Phase noise (dBc/Hz)
Spectre Simulation
-10
Theory
-50
-90
-130 3
10



Dominate by flicker noise
Roll off factor -30dBc/Hz/Decade
Error less than 2dB between
theory and simulation
4
10
5
6
10
10
Offset frequency (Hz)
7
10
8
10
Figure 3-23 Flicker noise source induced phase noise modelling
Flicker noise in control module
In addition to the above analysis, concentrating on practical VCO design, it is
found that flicker noise in the control module plays the most significant role of all noise
sources in the oscillator circuit.
PLL literature review, noise theory and analysis
Delay
Cell
I
in
1/A
Delay
Cell
88
Delay
Cell
Delay
Cell
1
Mcn
Mtn
Mtn
Mtn
Mtn
C
Correlated
Figure 3-24 Flicker noise correlated modulation mechanism in control modules
Consider the VCO shown in Figure 3-24, which is formed by using a 4-stage
delay cell. An oscillation frequency tuning mechanism is achieved by creating a
commonly used current mirror structure, formed by one diode connected NMOS (Mcn)
and 4 NMOS (Mtn) transistors, each of which is embedded in the tail of each stage.
Normally, when making the transistor sizing decision of these FETS, only the DC level
bias point and tuning linearity is considered, which always makes the diode connected
FET (Mcn) smaller than the design in the tail current path with a ratio of 1/A. However,
when phase noise is considered to be the critical issue, these design guidelines need to
be further optimized.
If it is assumed that the oscillation frequency f0 has a linear relationship with the
current I, the following sensitivity function results:
I 
f0
I
(3.71)
When there is a noise current in originating from the diode connected FETs, the
corresponding SSB phase noise can be derived from equation(3.64):
 I2
2
1 f 
L ( f )  2 SI ( f )  2  0  SI ( f )
4f
4I  f 
(3.72)
Furthermore, it can be noted that slight fluctuations of the current I are mirrored into all
the other tail currents with an amplification ratio A. Therefore, when the spectrum of
noise source is distributed in the same manner as flicker noise, the corresponding noise
spectrum at each tail current can be derived as:
PLL literature review, noise theory and analysis
Sin  flic ker ( f )  A(
89
Kf
2I 2
)
Veff COX Wcn eff Lcn eff f
(3.73)
As demonstrated in Figure 3-24, these low frequency fluctuations happen around the
loop over many oscillation cycles, hence significantly deteriorating noise figure. Using
the derivation methods illustrated above, the resulting SSB phase noise due the flicker
noise in control module is given [20]:
L( f )  A
Kf
COXWcn eff Lcn eff
 1
 2
 Veff
  f 02 
  3 
 f 
(3.74)
It must be pointed out that in [20], equation (3.74) is specified to the differential
structure based oscillator only. However, we believe that as the nature of the low
frequency distribution and correlation modulation mechanism are the same for singleended and differential structures, equation (3.74) is valid for most VCO designs.
Actually, as demonstrated in Chapter 5, noise originating in the control module can
easily overwhelm the phase noise if the dimensions of those transistors embedded in
the control module are not carefully considered. To address this issue, some recent
work [44][45] proposed that a low pass filter can be inserted in the control module to
eliminate the noise component. Theoretically, this solution is achievable, but it requires
a large capacitor C, which is at the level of µf, which is almost impractical for on-chip
realization.
Finally, to make a summary of this section, it can be found that for the noise
figure of an RC based oscillator, existing phase noise models can precisely reveal the
relationship across a variety of design specifications to the given process parameters.
Therefore, the utilization of these model-based equations to a real oscillator design will
be the key research task and this is comprehensively described in Chapter 4 and 5 of
this thesis.
3.2.4
Performance enhancement
Before an exploration into the specifics of oscillator design, two existing
techniques are first discussed. According to the published literature, it is believed that
significant improvements can be made to certain aspects of oscillator performance.
PLL literature review, noise theory and analysis
90
Coupled oscillators
The first technique, ―coupled oscillators‖ is reported in many papers [43][8][9],
and exhibits a trade-off between power dissipation and noise.
Osc1
Osc2
Signal spectrum
after combined
number (M) of
identical oscillators
OscM
Figure 3-25 Signal spectrum of coupled oscillator
As demonstrated in Figure 3-25 and mathematically proved in [9], when the noise
sources of each oscillator are uncorrelated, the combination of the output voltages of M
identical oscillators corresponds to an increment at M2 of the carrier power, whereas the
noise power only increases by M. Therefore, it is expected that the phase noise
decreases by a factor M at the costs of a proportional increase in power and chip area.
To investigate this technique in more detail, the phase noise calculation equation
that was derived in section 3.2.3 is considered (equation (3.63)) and rewritten here:
L( f ) 
f 02
1
1
(

)
NCOX Veff2 Wn eff Ln eff Wp eff Lp eff f 3
Kf
(3.75)
It can be found that when two identical oscillators are coupled with each other, the
number of delay stages increases to 2N, and this contributes a -3dB improvement at the
phase noise spectrum. Generally, equation (3.75) can be further evolved into:
L( f ) 
Kf
MNCOXVeff2
(
1
1
f2

) 03
Wn eff Ln eff Wp eff Lp eff f
(3.76)
where M denotes the number of inter-coupled oscillators. To demonstrate this, a series
of SpectreRF analysis have been made for the cases of 1/2/4/8/16 coupled oscillators.
PLL literature review, noise theory and analysis
91
Phase noise results of X1/X2/X4/X8/X16 coupled oscillators
40
Spectre Simulation
3dB
-40
Theory
12dB
-50
10
Phase noise (dBc/Hz)
-60
-70
-20
5
6
10
10
-50
-80
-110
-140
3
10
4
10
5
6
10
10
Offset frequency(Hz)
7
10
8
10
Figure 3-26 Phase noise spectrum of 1/2/4/8/16 coupled oscillators
The dark black lines in Figure 3-26 demonstrate the simulation results, compared
to the theoretical calculation results in grey. There is a strong agreement between
theory and simulation with a 3dB gap appearing when the number (M) of oscillator
stages is doubled. The technique of coupling oscillators does therefore lead to some
improvement in phase noise, but at the price of considerable increase in power and chip
area, both of which are in demand in advanced IC design.
Multiple feedback
The multiple-feedback-loop ring architecture is another technique that is reported
in the literature [40][47]--[51]. This technique leads to a considerable increase in the
maximum achievable oscillation frequency. Take for example, the design discussed in
section 3.2.3 and illustrated again Figure 3-27(a), the oscillation frequency of which
can be modelled by equation (3.36) (f0=1/2NReffCeff).
PLL literature review, noise theory and analysis
VDD
Vin
VDD
Vin
Vout
-
Vout
92
Vina=Vin-
Vina
VDD
Vout
Vin
GND
GND
GND
VDD
VDD
0.15μm
0.13μm
0.5μm
0.13μm
0.15μm
0.13μm
GND
0.15μm
0.13μm
GND
(a)
(b)
Figure 3-27 (a) Five stage ring oscillator with single feedback loop. (b) Five stage ring
oscillator with double feedback loop
The minimum allowable transistor length is a defined parameter, and the effective
capacitance Ceff and resistance Reff cannot be adjusted significantly. Therefore, to
increase the oscillation frequency, the most intuitive solution is to reduce the number of
delay stages N. However, in some applications [52], such as clock recovery, where high
speed and multiple phases are required simultaneously, reducing the number of delay
stages increases the oscillation frequency at the price of fewer signal phases.
The ring oscillator shown in Figure 3-27(b) incorporates multiple feedback loops,
and provides the same number of phases whilst also achieving a significantly higher
operation frequency than traditional ring oscillators. The secondary loop is achieved by
dividing the main input port (Vin) to two ports (Vin and Vina), and skewing one of
ports (Vina) with - than the main loop signal. The only design principle required is
that the size of the transistors in the auxiliary loops must be smaller than those in the
main loop [49]. For the design example shown in Figure 3-27(b), the PMOS transistors
in the auxiliary loop are sized at 150nm/130nm, which is only about 1/3rd the size of the
devices in the single loop design.
PLL literature review, noise theory and analysis
93
1.3
Voltage(V)
1.0
T0=152.18ps
0.6
0.2
-0.2
29.6
29.65
29.7
29.75
29.8
29.85
29.9
29.95
30 Time(ns)
29.85
29.9
29.95
30 Time(ns)
(a)
1
Voltage(V)
0.8
0.4
T0=80.2ps
0
29.6
29.65
29.7
29.75
29.8
(b)
Figure 3-28 (a) Output waveform with single feedback loop. (b) output waveform with double
feedback loop
The output waveforms of these two design examples are shown in Figure 3-28,
from where it can be observed that by using the double feedback loop in the design, the
oscillation frequency is increased from 6.58GHz to12.46GHz. This comes without the
penalty of a reduced number of signal phases. It is important to consider the effect of
multiple feedback loops on phase noise performance. Indeed, it is found that the phase
noise model (equation(3.60)) discussed in section 3.2.3is still valid. For example, the
performances of the design examples shown in Figure 3-27 are illustrated in Table 3-3,
which includes a comparison between the simulated and the theoretical phase noise
performance.
Table 3-3 Performance comparison between single feedback loop and double feedback loop
Single loop
Double loop
Oscillation frequency
6.58GHz
12.46GHz
Transistor size
(500nm/130nm)
(150nm/130nm)
(PMOS) (NMOS)
(150nm/130nm)
(150nm/130nm)
Delay stage
5
5
Phase noise @1MHz offset(Simulation)
-63.1dBc/Hz
-51.5dBc/Hz
Phase noise @1MHz offset(Theory)
-64.7dBc/Hz
-53.9dBc/Hz
PLL literature review, noise theory and analysis
94
It could find out that the double feedback loop structure experience a 11.6dB
phase noise level increase. At one side, the doubled oscillation frequency contribute
about 6 dB noise increase, where on the other side, the decrease of the width of PMOS
transistor contribute another 5 dB noise enhancement.
Furthermore, owing to the advantage of greater immunity to common node noise,
differential circuits are preferred in most IC designs when compared to their singleended counterparts. Starting with the four-stage differential ring oscillator, Figure 3-29
shows the complex inter-connections when double and triple feedback loops are
incorporated within the design.
(a)
Vi+
Vo-
Vi+
Vo-
Vi+
Vo-
Vi+
Vo-
Vi-
Vo+
Vi-
Vo+
Vi-
Vo+
Vi-
Vo+
Vi+
Vo-
Vi+
Vo-
Vi+
Vo-
Vi+
Vo-
Vi-
Vo+
Vi-
Vo+
Vi-
Vo+
Vi-
Vo+
Via+
(b)
Via+
Via-
Via-
Via+
Via-
Vib+
Via+
Vib+
Via+
(c)
Via+
Via-
Vib+
Via+
Vib+
Via+
Vi+
Vo-
Vi+
Vo-
Vi+
Vo-
Vi+
Vo-
Vi-
Vo+
Vi-
Vo+
Vi-
Vo+
Vi-
Vo+
ViaVib-
ViaVib-
ViaVib-
ViaVib-
Figure 3-29 Four stage differential ring oscillator (a) single feedback loops (b) double feedback
loops (c) triple feedback loops
Depending on the application requirements, different delay cell structures may be
used in the multiple feedback loop architectures of Figure 3-29. Figure 3-30, shows the
commonly used differential delay cells illustrating their built-in multiple input ports.
From simulation, it was found that all of these designs result in an operation frequency
increase of up to 20%-50% when compared with the traditional single feedback loop
structure.
PLL literature review, noise theory and analysis
95
VDD
Vo-
VDD
Vo+
Vct
Vct
Vo-
Vi+
Via+
Via-
Vi-
Vib+
Vo+
Vi+
Via+
Vbias
Via-
Vi-
Vib-
Vbias
GND
GND
(a)
(b)
VDD
VDD
Vp
Vp
Via-
Via+
Via+
V o+
Vi +
Vo-
Vo+
Vct
Vi+
Vi -
Vo -
Vi-
Via-
Vn
Vn
GND
GND
(d)
(c)
Figure 3-30 (a) Double inputs source-coupled delay cell. (b) triple inputs source-coupled delay
cell. (c) double inputs cross-coupled delay cell. (d) dual inverter delay cell.
Some additional comments need to be made about the dual inverter delay cell,
which was first proposed in [22] as shown in Figure 3-31(a). In [40], a revised version
was reported as shown in Figure 3-31(b) which was reported to achieve a 100%
increase in oscillation frequency.
Vp
Mp2
Vgp Mp6
Vp
Vp
Mp2
Mp6
Vgp
Mp3
Mp1
Mp5
Mp1
Vout+
Vin +
Vin +
Vin -
Mp5
Mp3
Vout+
Vout -
Vin -
Vout -
Mn1
Mn5
Mn3
Mn1
Mn3
Mn5
Vgn
Vgn
Vn
Vp
Mn2
Mn6
Vn
Vn
Mn6
Vn
Vout
-
Vout 0º
Vgp
Vin + Vout Vin - Vout+
180º
Vgn
225º
45º
Vgp
Vin + Vout Vin - Vout+
90º
270º
Vgn
Vgp
Vin + Vout Vin - Vout+
Vgn
315º
135º
Vgp
Vgp
Vin + Vout Vin - Vout+
Vin + Vout Vin - Vout+
Vgn
Vgn
Vgp
Vgp
Vgp
Vin + Vout Vin - Vout+
Vin + Vout Vin - Vout+
Vin + Vout Vin - Vout+
Vgn
Vgn
Vout
+
Vout+
(a)
Vgn
(b)
Figure 3-31 Dual inverter delay cell based four stage ring oscillator. (a) negative feedback. (b)
positive feedback
PLL literature review, noise theory and analysis
96
Analysing the dual inverter delay cell based oscillators from a double feedback
perspective leads to the conclusion that each delay cell can be divided into two current
starved single-ended inverters, each of which are associated with a second input and
hence form a double feedback loop. The primary difference between the two versions
of dual inverter delay cell is that the secondary feedback loops in the original design
have a 45ºlag, whereas in the improved version the secondary loop leads by 45ºwhen
compared to the main loop signals. This different structure contributes to a frequency
increase of up to 100%, but also leads to a degradation in phase noise performance of
up to 6dB or more. In summary, as demonstrated in previous section, and as is proved
later, in Chapter 5, the phase noise still can be predicted accurately by equation (3.63).
3.2.5
Comparison of existing designs
Finally, a comprehensive comparison is made of the existing designs in terms of a
number of performances as illustrated in Table 3-4. In order to make a fair comparison,
a widely used Figure of Merit (FoM) [18][67] for the VCO is introduced:
 f
FoM  L  f offset   20log  0
f
 offset

 P 
  10log  DC 
 1mW 

(3.77)
which incorporates critical VCO parameters (power, frequency, phase noise). Although
this FoM is commonly used to evaluate the performance of the LC VCOs, it is found
that for an RC based VCO, a generally acceptable design must achieve a FoM of 155dB while an outstanding design should below the -160dB level.
Furthermore, from the comparison, it is found that the dual inverter delay cell
reported in [22] holds the highest score over all the other design approaches. This
conclusion is also proven by the measurement results that are illustrated in [53], where
the dual inverter based oscillator is compared with designs using the source-coupled or
cross-coupled delay cell. It should be pointed out that the results illustrated in Table 3-4
for high frequency (5GHz) designs are only based on simulation results. As will be
shown in Chapters 4 and 5, to realize these designs on silicon and build a suitable test
platform brings another level of challenge.
97
PLL literature review, noise theory and analysis
Table 3-4 Comparison of existing design
Process
Area
offset(dBc/Hz)
Phase Noise @1MHz
Tuning Range in
Tuning Range(MHz)
Flicker noise
Supply Voltage(V)
2
0.18
6750
913MHz
offset from
-116@600KHz
37.5%
650-1040
18.95
No
Yes
2
Measurement
1[22]
-157.48
2
0.5
12750
900MHz
offset from
-105.5@600KHz
47.4%
661-1270
15.4
No
Yes
2.5
Measurement
2[23]
-156.8
2
0.35
4035
866MHz
offset from
-106@500KHz
60.8%
450-1150
24.5
No
Yes
3.3
Measurement
3[56]
-159
2
0.18
----
700MHz
offset from
-109.6@600KHz
27%
549-765
15.34
No
Yes
1.8
Measurement
4[53]
-157
2
0.35
----
973Mhz
offset from
-117@1MHz
----
----
79.2
No
Yes
3.3
Measurement
5[44]
---
3
0.18
----
5.9GHz
offset from
-99.5@1MHz
14%
5160-5930
----
No
No
1.8
Simulation
6[51]
---
2
0.35
----
5.8Ghz
offset from
-117.5@10MHz
84%
900-5800
----
Yes
No
3.3
Simulation
7[54]
---
2
0.18
----
5.61GHz
offset from
-99.7@1MHz
24%
4650-5890
4.8
Yes
No
1.8
Simulation
8[55]
Design
# of delay cells
-166.8
Percent
Consumption(mW)
Power
included
Passive component
included
FoM
PLL literature review, noise theory and analysis
98
3.3 Summary
This chapter has demonstrated a theoretical model which can accurately predict
the noise performance of RC oscillators in a number of configurations. Furthermore, a
direct link between transistor dimensions and theory is proposed which allows circuit
designers to leverage the model and produce optimal designs. Finally, a Figure of Merit
(FOM) is introduced which provides a more effective method of assessing the
effectiveness of the approach and how well it compares quantitively with other work in
this area. The thesis will now demonstrate how this theoretical underpinning can be
applied to specific design cases, in the first instance an ultra wideband VCO.
Ultra wide tuning range ring oscillator
99
Chapter 4 Ultra wide tuning
range ring oscillator
Although the double feedback dual inverter VCO represents the best phase noise
performance for an inverter-based oscillator, in this chapter it will be shown that a
wider tuning range can also be achieved through a structural improvement to exist
design. Furthermore, this chapter will address the lack of published sizing guidelines to
help designers successfully size the circuits in real applications through a methodical
approach. More specifically, it is demonstrated in sections 2.1.1 and 2.1.3 that neither
the small nor the large signal model is robust enough to accurately explain the
oscillation behaviour in these circuits. Therefore, to address this issue, a preliminary
design methodology is proposed in section 4.2, which utilizes phase noise as an input
variable to link the design specification directly to transistor sizing. Finally, two 120nm
1.2V design examples are proposed and supported by post layout simulation results.
These two design examples were fabricated and preliminary test results are described in
section 4.4.
4.1 Improved delay cell structure
In order to explain the improvements of the new structure, the basic concepts and
drawbacks behind the standard existing structure are first explained. The structure of
the existing modified dual inverter delay cell based oscillator is shown again in Figure
4-1. Frequency tuning in this type of delay cell is achieved using the two differential
control signals Vp and Vn. As was demonstrated in section 3.2.4, Mp3 and Mn3
provide local positive sub feedback that increases the oscillation frequency. The
Ultra wide tuning range ring oscillator
100
transistor dimensions can be sized through equation (4.1), which relates the dimensions
of Mn1 to the dimensions of Mp1 and Mp3 [22] .Vtn and Vtp are the transistor threshold
voltages and μp and μn are their mobility parameters. The cascode devices Mp2 and
Mn2 are given the same dimensions as Mp1 and Mn1 respectively, and the opposite
site of the delay cell is designed in the same way [40].
Vp
I1 I2
Mp2
Mp6
Vp
Vgp
Mp1
Mp5
Mp3
Vout+
Vin +
Vin -
Vout -
I3
Mn3
Mn1
Mn5
Vgn
Vn
Mn2
Mn6
Vn
Vout Vgp
Vin + Vout Vin - Vout+
Vgn
Vgp
Vin +Vout Vin - Vout+
Vgn
Vgp
Vin + Vout Vin - Vout+
Vgn
Vgp
Vin + Vout Vin - Vout+
Vgn
Vout+
Figure 4-1 Existing double feedback dual inverter delay cell [40].
2
 VDD

 p  2  | Vtp |   W
W
W 
( ) n1 
V
 ( ) p1  ( ) p 3 
L
n  DD  | V |   L
L 
tn
 2

(4.1)
The principle drawback of the delay cell shown in Figure 4-1 is the amplitude
mismatch between the pull down current I3 and pull up current I1+I2 over the full
control voltage range. The mismatch is least noticeable when Vp=0V and Vn=Vdd,
provided equation (4.1) is observed. However as Vp is increased and Vn decreased, the
mismatch becomes greater, upsetting the Vout and Vin quiescent bias point and
ultimately causing oscillations to cease. This mismatch therefore has a direct impact on
the tuning range of the designed cell. A secondary effect of the mismatch is the
degradation of the waveform symmetry, which is highly related to phase noise as
previously discussed [93].
Ultra wide tuning range ring oscillator
Vp
101
I1 I2
Vp
Mp2
Mp4
Mp1
Mp3
Mp6
Vp
Vgp
Mp5
Vin -
Vout+
Vin +
I3
Vout -
Mn1
Mn3
Mn5
Mn4
Mn6
Vgn
Vn
Mn2
Vn
Vn
Figure 4-2 Improved double feedback dual inverter delay cell.
The improved delay cell presented in this work is shown in Figure 4-2. The
improvement addresses the mismatch between I1+I2 and I3 through the addition of two
control devices Mp4 and Mn4. These devices maintain the correct bias point over a
wider control voltage range. To demonstrate the advantage of adding Mp4 and Mn4,
Figure 4-3 shows a DC analysis of the quiescent bias voltage Vout with a range of
control signals (Vp) for both the delay cell of Figure 4-1 and the improved cell of
Figure 4-2. For this analysis, all transistors were sized according to equation (4.1) and
Vin and Vgp were fixed at Vdd/2. From Figure 4-3, for the existing delay cell, it can be
seen that Vout quickly drifts from the ideal bias point of Vdd/2 as Vp exceeds 0.3V. In
contrast, the improved delay cell maintains the correct bias point until Vp exceeds
0.65V. The improvement is significant and results in the potential for a much wider
tuning range, as will be demonstrated in section 4.3.
1.4
1.2
Existing delay cell
Vout (V)
1
0.8
0.6
0.4
Proposed delay cell
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Control Voltage Vp (V)
0.8
0.9
Figure 4-3 DC analysis for existing and improved delay cells.
1
Ultra wide tuning range ring oscillator
102
4.2 Phase noise model oriented transistor width sizing
The phase noise model for the push-pull inverter based oscillator has been
detailed in section 3.2.3. In this section, the model is further refined in order to help the
designer make intelligent transistor sizing decisions.
Provided that the delay cell is sized under the constraint of equation (4.1), the
branches on the left (Mn1) and right (Mp5) side of the delay cell should carry equal
current, giving:
Wp1  Wp3  Wp5
Wn5  Wn3  Wn1
(4.2)
Therefore, two simplifications can be made for the remaining analysis, both of
which have little impact on the model accuracy. Firstly, the differential structure is
considered as a single ended structure with twice as many stages and secondly the left
side of the delay cell, shown in Figure 4-4(a), can be simplified to that of Figure 4-4(b).
As a result, an N stage dual inverter delay cell based VCO can be modelled as a loop of
2N of the single ended delay cells shown in Figure 4-4(b).
Vp
I1
I2
Mp2
Mp4
Mp1
Mp3
Vp
Vp
I1+I2
Mp2+Mp4
Vgp
Mp1+Mp3
Vin +
Vin +
Vout Vout -
I3
Mn1
Vn
i
+ n
Mn2
(a)
I3
Mn1
C
Vn
i
+ n
C
Mn2
(b)
Figure 4-4 Theoretical model for proposed delay cell
Furthermore, two pre-conditions are defined within the phase noise modelling.
Firstly, since it was demonstrated in Chapter 3 that flicker noise dominates phase noise
spectrum up to a few MHz, only the flicker noise sources are considered in the phase
noise modelling. Secondly, from the analysis presented in [40], if we assume that the
cascode devices (Mn2/Mp4/Mp2) have the same dimensions of the inverting device
(Mn1/Mp1/Mp3), the overall noise contribution from these devices can be lumped into
a single transistor. Therefore, applying the flicker noise induced phase noise modelling
approach that was illustrated in section 3.2.3 to the proposed improved dual inverter
Ultra wide tuning range ring oscillator
103
delay cell based oscillator, it can be shown that the phase noise of this 2N stages loop is
given as:
 K fn
K fp   f 02 
1
L( f ) 


 
2 NVeff2 Cox  Wn1Ln1 Wp 5 Lp 5   f 3 
(4.3)
Substituting equation (4.2) into (4.1) and assuming Vtp≈Vtn gives (4.4). Equation
(4.4) is substituted into (4.3) and solved for Wp5 to give equation (4.5).
Wn1 
p
W
n p 5
K f f 02 (
Wp 5 
n
 1)
p
2 NVeff2 Cox L ( f ) Lf 3
(4.4)
(4.5)
The above two equations allow the width of Mp5 and Mn1 to be calculated as a
function of the specified phase noise and are used as the key part of the delay cell
design methodology illustrated in next section.
4.3 Design methodology
In order to make the analysis of the previous sections more accessible to
designers, a preliminary design methodology for the VCO design is now presented. The
first step is to determine the transistor length for a given oscillation frequency fosc.
Transient simulation results can be used for this basis, but it should be noted that a
reasonable margin needs to be added to account for process and temperature variation
and the likely reduction of oscillation frequency due to layout induced effects and
foundry model inaccuracies. Equations (4.4) and (4.5) are then used to calculate the
width of Mp5 and Mn1.
At this stage, a DC analysis of the simplified phase noise circuit model shown in
Figure 4-3 (b) is performed to ensure that with Vin=Vdd/2, Vout is equal to Vdd/2. Using
simulation, slight adjustment of the transistor sizes may be necessary to compensate for
differences between Vtp and Vtn, and further refine the performance. The ratio between
Wp1 and Wp3 will influence the upper or lower limit of the oscillation frequency.
From extensive simulation it has been found that as a guide Wp1=Wp3=Wp5/2 can be
used. Therefore, using equation (4.1), the size of Mp1 and Mp3 can be calculated. Mp2,
Ultra wide tuning range ring oscillator
104
Mp4 and Mn2 are made equal to Mp1, Mp3 and Mn1 respectively. The right side of the
cell is designed using the same method.
4.4 Design example 1&2 and simulation results
To demonstrate the wide tuning range of the improved delay cell and validate the
theoretical analysis in Section 4.2 and 4.3, two design examples are presented. Both
designs were implemented on ST-HCMOS9GP-120nm (known as st12) digital CMOS
process and are based on the VCO structure shown in Figure 4-2. The design
specifications for designs are shown in Table 4-1.
Table 4-1 Design example specifications
Specification:
Supply voltage
Frequency range
Phase Noise
Power
Number of stages
4.4.1
Design Example 1
1.2V
Wider than 40-4000MHz
Below the level of
-94dBc/Hz @ 1MHz offset
from 4000MHz
Minimised
4
Design Example 2
1.2V
Wider than 8-800MHz
Below the level of
-116dBc/Hz @ 1MHz offset
from 800MHz
Minimised
4
Design example 1: 32M—5.1GHz
Transistor sizing
The first design example demonstrates the high frequency potential of the
improved delay cell. To maximize the oscillator frequency, the minimum allowable
length is chosen for transistor length L. The width Wp5 is calculated directly from
equation (4.5) with N=4, L=130nm, L(f) and fo (calculated from the specification) and
Vt≈0.318V for L=130nm. Equation (4.4) is then used to calculate Wn1. The resulting
widths are Wp5=127.0µm and Wn1=40.38µm.
As discussed in last section, a DC analysis may be necessary for this stage, which
simply ensures that with Vin=Vdd/2, Vout is equal to Vdd/2. After Spectre based DC
analysis, Wp5 and Wn1 were refined to values of 100µm and 40µm respectively. It
should be noted that for the purposes of these DC simulations, Vp and Vn should be set
to a value ensuring that Mn2,4,6 and Mp2,4,6 work in the deep triode region,
minimizing their noise contribution whilst maintaining insensitivity to process and
temperature variation. In this case, the control voltage Vn is set at 1V (Vp=0.2V). Then,
Ultra wide tuning range ring oscillator
105
following the design guidelines illustrated in section 4.3, the other transistor
dimensions are obtained.
Vp
Mp2
50μ
0.13μ
Mp1
Mp4
100μ
Vgp
0.13μ
Mp3
Mp6
Mp5
Vout+
Vin +
Vout Mn1
40μ
0.13μ
Mn3
Vgn
Mn4
Mn2
20μ
0.13μ
Mn5
Mn6
Vn
Figure 4-5 Design dimensions of example 1
Layout of delay cell in design example1
In section A, three fundamental analogue layout techniques have been illustrated
within the layout of the beta multiplier block. In this section, once again, it can be
demonstrated how to apply these three commonly used analogue layout techniques
within the practical layout of each delay cell. Considering the left side of the delay cell
shown in Figure 4-5, Mn1 and Mn2 have the dimensions of 40µm/0.13µm, and Mp1-Mp4 have the dimensions of 50µm/0.13µm. Therefore, if each NMOS is divided into
40 fingers, which is multiple of 4, each PMOS has to be divided into 20 fingers so as to
ensure that there are total 80 fingers for NMOS and PMOS, respectively. The size of
fingers is illustrated in Figure 4-6
Vp
Mp2
Mp4
Mp1
Mp3
Vgp
2.5µm
1µm
Vin +
Vout Mn1
Unit N-stack sizing
Vn
Mn2
Unit P-stack sizing
Figure 4-6 Stack sizing for each FET
Furthermore, notice that transistor Mp2 and Mp4 share their gate and source
terminals that mean a continuous path for these two terminals can be created.
Meanwhile, it is found that transistor Mp1, Mp3, and Mn1 share one terminal, which is
Ultra wide tuning range ring oscillator
106
the Vout terminal of the delay cell whereas the Vin terminal is shared by the Mp1 and
Mn1, which means a continuous path can be created again for Vin and Vout, respectively.
Thus, taking into account all of these factors, the layout for the delay cell is given with
the structure and arrangement as shown in Figure 4-7.
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
D P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 D
P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1 N1
G
G
G
G
G
G
G
G
G
D N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 N2 D
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
Figure 4-7 Illustration of layout structure for left half delay cell
The adjacent stacks P2 and P4 share the Vdd terminal and two dummy transistors
(D) are added at the ends of the stack to ensure that the unit stacks of matched stacks
see the same adjacent structures, whereas the guard rings (G) are created to provide
effective isolation from other devices on the chip. The final layout for the left half of
the delay cell is shown below in Figure 4-8, where the common centroid arrangement,
guard rings and dummy transistors can be clearly observed.
Figure 4-8 Layout for the left half of the delay cell
Ultra wide tuning range ring oscillator
107
Using the same techniques, the right side of the delay cell is designed and hence
the total four-stage dual inverter based ring oscillator is created. Two versions of the
post layout simulation results were obtained as shown below in Table 4-2. One version
is the standard post layout simulation results based only on extracted devices, and the
other also considers parasitic capacitances. As expected, the presence of simulated
parasitic capacitances reduces the oscillation frequency. It is also clear that the
proposed improved delay cell can achieve a significantly wider tuning range than
previous reported designs. Furthermore, for the phase noise issue, which is the critical
design specification, it is found that when parasitic capacitances are taken into account,
the phase noise proportionally decreases with the oscillation frequency.
Table 4-2 Simulation results of design example 1
Vp(V):
Fc (MHz):
Post_layout
Power(mW):
Post_layout
Phase Noise @
1MHz offset
(dBc/Hz)
Post_layout
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
6729
6520
6242
5864
5329
4556
3490
2200
976
258.06
155(Vp=0.93)
36.3
35.26
33.89
32.05
29.49
25.87
20.9
14.71
8.19
3.59
2.86
-90.62
-90.86
-91.07
-91.59
-91.83
-92.22
-92.91
-94.49
-98.88
-106
-107
4.4.2
Fc (MHz):
Post layout
pair
capacitance
Power
(mW):
Post layout
pair
capacitance
5169
5006
4791
4485
4081
3481
2657
1671
744.5
198.5
32.2
36.41
35.36
33.98
32.13
29.54
25.87
20.84
14.61
8.117
3.55
1.91
Phase Noise @
1MHz offset
(dBc/Hz)
Post layout
pair
capacitance
-92.87
-93.22
-93.396
-93.707
-94.01
-94.42
-95.22
-96.98
-101.47
-108.76
-103.41
Design example 2: 4M—800 MHz
In order to demonstrate the trade off between frequency and phase noise in design
example 2, a starting length of 400nm has been chosen and equations (4.4) and (4.5)
are used to calculate Wp5 and Wn1 as 199.4μm and 63.2μm respectively. After DC
optimization the final transistor sizes are given inTable 4-3.
Table 4-3 Design example two dimensions
Transistor:
W/L (m):
Transistor:
W/L (m):
Mp1,Mp2
Mp3,Mp4
Mp5,Mp6
120/0.4
80/0.4
199/0.4
Mn1,Mn2
Mn3,Mn4
Mn5,Mn6
64/0.4
25.6/0.4
38.4/0.4
The phase noise and tuning results from post-layout simulation are shown in
Table 4-4. In this example the ratio of Wp1:Wp3 is chosen as 3:2, increasing the tuning
range further. As expected, the reduced frequency requirement results in an
Ultra wide tuning range ring oscillator
108
improvement in phase noise, with the simulated phase noise of -116.12dBc/Hz
comparing well to the design specification of -116dBc/Hz.
Table 4-4 Simulation results of design example 2
Vp(V):
Fc (MHz):
Post_layout
Power(mW):
Post_layout
Phase Noise @
1MHz offset
(dBc/Hz)
Post_layout
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.01
985.5
955.9
912.8
856.6
780.6
672.8
517
328.66
148.11
40.86
4.748
21.35
20.7
19.88
18.81
17.38
15.4
12.6
9.02
5.52
2.809
1.599
-114.8
-115.09
-115.3
-115.6
-115.8
-115.9
-106.6
-105.2
-106.9
-123.7
-125.7
Fc (MHz):
Post layout
pair
capacitance
Power
(mW):
Post layout
pair
capacitance
912
881
841
788.5
717.99
618.23
474.79
294.92
136.71
37.72
4.33
21.38
20.73
19.9
18.82
17.39
15.4
12.59
9.03
5.52
2.806
1.59
Phase Noise @
1MHz offset
(dBc/Hz)
Post layout
pair
capacitance
-115.63
-115.83
-116.12
-116.35
-116.59
-116.66
-115.81
-104.6
-110.34
-124.9
-126.67
4.5 Realization and testing of prototype chip 1
Figure 4-9 All layer view of chip 1 evaluation PCB
The layout view of the first evaluation PCB can be seen on Figure 4-9. The
output signal from chip passes through the amplifier circuit before it goes into the BNC
connector. After amplification, the output signal, which can be detected by the
oscilloscope, is shown in Figure 4-10.
Ultra wide tuning range ring oscillator
109
Figure 4-10 Output signal at 108.08MHz (864.6MHz) of design example 2
Figure 4-11 Jitter performance output signal at 108.08MHz (864.6MHz) of design example 2
The measured jitter performance of this signal is shown in Figure 4-11. The RMS
jitter is 44.01ps over the 2.13ns of oscillation period and the peak to peak jitter is
667.8ps. The main reason for the poor measured jitter values was the absence of onchip buffers. The tuning range of these two design examples are shown in Table 4-5.
Ultra wide tuning range ring oscillator
110
For design example 1, the output waveform is only obtained when the control signal is
higher than 0.6V. The reason for this is that the frequency divider used within this
design can only operate below 1.6GHz (approximately).
Table 4-5 Measurement results of chip 1
Design example 1
Vp(V):
Fc (MHz):
Measurent
0
Fc (MHz):
Reality=Measurement32
Design example 2
Fc (MHz):
Reality=Measurement8
864.6
Vp(V):
Fc (MHz):
Measurent
Unavailable
0
108.08
0.05
Unavailable
0.05
102.88
823
0.1
Unavailable
0.1
101.83
814
0.15
Unavailable
0.15
100.81
806
0.2
Unavailable
0.2
99.602
797
0.25
Unavailable
0.25
97.656
781
0.3
Unavailable
0.3
96.15
769
0.35
Unavailable
0.35
93.7
750
0.4
Unavailable
0.4
90.9
727
0.45
Unavailable
0.45
86.9
695
0.5
Unavailable
0.5
81.3
650
0.55
Unavailable
0.55
74.9
599
0.6
62.8
502
0.6
101.125
3236
0.65
93.13
2984
0.65
51.9
415
0.7
81.0
2592
0.7
39.8
318
0.75
66.19
2118
0.75
30.8
246.6
0.8
54.75
1752
0.8
23.06
184.48
0.85
40.94
1310
0.85
16.5
132
0.9
27.81
890
0.9
8.16
45
0.95
16.94
542
0.95
5.63
19.04
0.96
11.06
354
0.96
3.21
15.36
0.97
7.63
244
0.97
1.52
12.2
0.98
6.31
202
0.98
1.04
8.32
0.99
5.82
186
0.99
0.933
7.44
5.63
180
1
0.6
4.8
1
As shown in Table 4-5, the measured frequency band is located between 108.08
MHz and 0.6MHz. Since the measurement is taken at the output of 3 frequency divider
stages, the actual performance of design example 2 is given by multiplying the
measurement results by 8. The difference between the measured and simulated tuning
response is shown in Figure 4-12, where it is seen that at the highest operational
frequency, the RCc mode based post layout simulation results are close to the
measurement performance.
Ultra wide tuning range ring oscillator
111
1000
900
Oscillation Frequency (MHz)
800
700
600
500
400
Simulation (Capacitive only)
300
Simulation (RCc)
Measurement
200
100
0
0.2
0.4
0.6
0.8
1.0
1.2
Control voltage Vn (V) (Vn=1.2-Vp)
Figure 4-12 Performance comparison between simulation and measurement results of design
example 2
4.6 Summary
Firstly, at a theoretical level, it has been demonstrated that phase noise can be
used as an input variable to guide transistor sizing decisions. However, the design
methodology presented in this chapter has not been fully developed. One of the obvious
questions is that the transistor length must be decided based the designer‘s experience
and associated with transistor level transient simulation results. Furthermore, besides
the phase noise value, equation (4.5) requires another important variable to make the
transistor width decision, that is, the oscillation frequency (fo). Actually, we can find
that existing phase noise models (presented in Chapter 3) are all based on the
assumption that the oscillation frequency is fixed or pre-defined. Therefore, we believe
a comprehensive VCO model should be derived that directly bridges the gap between
transistor dimensions and oscillation frequency and phase noise.
Secondly, at the experimental level, the advantage of the ultra-wide tuning range
of the proposed new delay cell has been demonstrated with the noise figure needing to
be verified through a more reliable testing platform.
Ultra wide tuning range ring oscillator
112
These two reasons illustrate the necessity for deeper research into an advanced
VCO modelling analysis, which is presented in next chapter of this thesis.
A novel noise-aware oscillator model
113
Chapter 5 A novel noise-aware
oscillator model
In section 3.2, a through review was presented of existing VCO noise models and
VCO designs. In chapter 4, an improved VCO delay cell was presented. Both of these
chapters were essential preparation for the development of a new PLL model. The
practical application for an advanced VCO model is to be embedded within a
comprehensive PLL model, and hence be used to determine solutions for improving
PLL performance. In section 3.1.4, the requirement for developing an improved time
domain PLL model was highlighted. A perfect VCO model should accept the
instantaneous control voltage as an input variable and hence dynamically generate the
output waveform, while incorporating all the relevant noise sources. Further processing
of the VCO‘s output waveform could give the oscillation frequency and details of the
signal purity.
Therefore, in this chapter, based on the proposed new delay cell that was
described in Chapter 4, the aim is to build a mathematical relationship between the
instantaneous control voltage and the oscillation frequency. The fundamental VCO
parameters, such as: number of delay stages (N) and transistor dimensions (W/L) need
to be directly incorporated. Due to PVT variation, it is obviously impractical to
precisely predict the oscillation frequency, but it is necessary and useful to model the
non-linearity of the VCO‘s tuning behaviour. The detailed analysis for this issue is
presented in section 5.1.
Furthermore, as has been comprehensively reviewed in section 3.2.3, the most
recent VCO phase noise model directly relates the transistor dimensions to phase noise.
In this chapter, we will illustrate how to incorporate this frequency domain phase noise
A novel noise-aware oscillator model
114
model into the proposed time domain VCO model. The details of the modelling
approaches are illustrated in 5.2.
5.1 Modelling of frequency tuning behaviour.
Following the approach used previously in [63]−[65], the MATLAB-Simulink®
platform was chosen to create the VCO and PLL models, as it has a vast array of builtin mathematical functions and a fully developed graphical interface. Based on the
review and analysis that has been presented in section 2.1, it can be understood that
oscillation period To is the combination of 2N stages of delay td, which can be further
expressed with the product ReffCeff. Therefore, the critical issue is how to calculate the
effective resistance and capacitance, especially if we want to incorporate non-linearity
within the model. Referring back to the proposed new VCO delay cell, in Figure 4-3,
the differential mode delay cell was simplified into two single–ended modules,
consequently, an RC delay circuit could be derived from this single–ended module, as
shown in Figure 5-1. Notice that instead of naming these transistors with numbers, they
have been named based on their operation behaviour. The two internal transistors
always operate as an inverters, and are therefore named as inverting transistors,
Wni/Lni and Wpi/Lpi, whereas the two cascode transistors are responsible for the
frequency control, and we hence denoted these as the cascode devices, Wpc/Lpc and
Wnc/Lnc.
A novel noise-aware oscillator model
Vp
I1 I2
Mp2
Vp
Vp
Mp6
Mp4
115
Vp
I1+I2
Mp2+Mp4
Mp6
Mp1+Mp3
Mp5
Vp
Vgp
Mp1
Mp5
Mp3
Vin -
Vout+
Vin +
I3
Vin +
Vout -
Vout -
Mn1
Mn3
Mn5
Mn2
Vn
Mn4
Mn6
Vout+
I3
Vgn
Vn
Vin -
Vn
Vn
Mn1
Mn5+Mn3
Mn2
Mn6+Mn4
Vn
Transistor ON resistance
(Rctn/p), vary with
control signal
Rctp
Wpc Wp6
=
Lpc Lp6
Transistor ON (Ronn/p)
resistance
Ronp
Wpi Wp5
=
Lpi Lp5
cap
Transistor gate
capacitance (Cap) at load
Ronn
Wni Wn1
=
Lni Ln1
Rctn
Wnc Wn2
=
Lnc Ln2
Figure 5-1 Modelling of effective RC delay for the proposed new delay cell
According to [10](page 337-339), the load capacitance of an inverter should
incorporate the inverter‘s input capacitance (Cin) and the inverter‘s output capacitance
(Cout), which is expressed by (5.1)
Cout
Cin
3
Cap  (Wni  Lni  Cox  Wpi  Lpi  Cox )  (Wni  Lni  Cox  Wpi  Lpi  Cox )
2
5
 (Wni  Lni  Cox  Wpi  Lpi  Cox )
2
(5.1)
Since the ON resistance of these two inverting transistors (Wpi/Lpi, Wni/Lni) are
independent of the frequency tuning, they can be modelled with a fixed ON resistance
(Ronn/Ronp), (5.2) and (5.3).
Ronn 
VDS
VGS

I DS ( 1  C Wni (V  V )2 )
n ox
GS
th
2
Lni
(5.2)
A novel noise-aware oscillator model
Ronp 
VDS
VGS

I DS ( 1  C Wpi (V  V )2 )
p ox
GS
th
2
Lpi
116
(5.3)
It is difficult to decide the specific value of VGS and VDS within the equation (5.2)
and (5.3), since the voltages at the gate and drain nodes of the device dynamically
change within each oscillation cycle. Simulating the voltage waveforms at the gate and
drain nodes of transistor (Wni/Lni) gives the waveforms in Figure 3-22. This shows
that within each propagation delay (td), the gate voltage increases from VDD/2 to VDD,
whereas the voltages at the drain node decrease from VDD to VDD/2. Therefore, for
simplicity, it can be assumed that both drain and gate nodes stay at a middle point
(VDDx3/4) within the propagation delay (td). Thus, the transistor always works in the
saturation region and VDS=VGS=VDDx3/4.
On the other hand, if the two cascode transistors are modelled as two variable
resistors (Rctp/Rctn), the external control voltages (Vct=VGS) decide the value of each
resistor. Obviously, the linearity between the control voltage and effective resistance of
these transistors determines the linearity of the VCO‘s voltage-frequency relations.
Knowledge about the transistor‘s DC operating conditions show that it may either
operate in the deep triode region, which is characterized by equation (8.1) or in the
saturation region as depicted by equation (8.2). If the transistor works in the saturation
region, its drain node has the same potential as the gate node, as a result, we can use the
transistor (Wnc/Lnc) as an example:
Rctn _ sat 
VGS
1
Wnc
( nCox
(VGS  Vth )2 )
2
Lnc
(5.4)
When the transistor is working in deep triode region, from equation (8.1):
Rctn _ tri 
VDS
1

I D  C Wnc (V  V )
n ox
GS
tn
Lnc
(5.5)
It is difficult to determine the working conditions of these transistors, (i.e., whether that
transistors (Wpc/Lpc, Wnc/Lnc) are working in saturation region or deep triode
region), because with each oscillation period, the VDS of these transistors could vary by
several hundred mV. For this reason an approximation is made that the effective ON
resistance of these control transistors is a combination of equation (5.4) and (5.5),
where the percentage of each portion is determined linearly by the instantaneous
control voltage (Vct), as depicted by equation (5.6):
A novel noise-aware oscillator model
Rctn  Rctn _ sat (
117
VDD  Vct
Vct
)  Rctn _ tri(
)
VDD
VDD
(5.6)
It can be shown that Rctn_sat is proportional to 1/(VGS-Vth)2 whereas Rctn_tri is
propotional with VGS. As a result, the combination of the two must vary non-linearly
with VGS. Besides this, it must be noted that the VCO‘s control voltage (Vct) could
dynamically vary when this VCO model is embedded within a PLL model, therefore,
equations (5.4)−(5.6) should be realized with the Simulink model shown in Figure 5-2.
The variable resistance Rctp has the same structure as Rctn, with the difference only
happening in the process parameters (Kpn=μnCox/Kpp= μnCox).
VDD
Constant6
Subtract1
Divide1
1
In1
u2
Vct
Vth
Constant4
0.5*Kpn*(Wnc/Lnc)
Divide
Math
Function
Gain1
Kpn*(Wnc/Lnc)
Subtract
Product
1
Constant1
Add
1
Out1
Rctn
Divide3
Gain
Product1
VDD
Constant7
Divide2
Figure 5-2 Simulink model of the variable resistor (Rctn).
Once all the effective capacitive and resistive components are modelled, the
corresponding propagation delay (td) can be directly obtained from equation (5.7).
Further modelling of this equation with Simulink is shown in Figure 5-3.
td  Reff Ceff 
VDD
V /2
VDD / 2
C  DD

I
VDD
2I
/C
C
Rctn  Ronn
(5.7)
Fundamentally, equation (5.7) is same as equation (3.37), which has been used within
the phase noise model. Actually, it can be seen in later sections of this thesis that the
VCO‘s noise model is derived from this propagation delay model.
A novel noise-aware oscillator model
Push
current (I)
Variable resistor
Figure 5-2
1
In1
Vct
In1 Out1
Rctn1
118
Propagation
delay (td)
half_rail=VDD/2
half_rail
Constant7
VDD
Constant1
1
Divide2
Ronn
Divide
Add
Constant4
Divide1
Out1
Push-delay
Cap
Constant8
Figure 5-3 Simulink model of the propagation delay (push-delay)
Realizing that the pull-up path holds the same principle and the same structure as
the push-down path that is shown in Figure 5-3, for the dual inverter based ring
oscillator, it is straightforward to combine 2N stages of push delay and 2N stages of
pull delay to obtain the nominal oscillation cycle (To). Inverse of To should give the
frequency domain results shown in Figure 5-4.
Output waveform
Push delay
Figure5-3
1
Constant 1
In1
Out1
Pushdelay1
Vct
Constant 3
In1
Out1
Pulldelay1
Scope4
2*N
Scope1
Gain(delay_stage)
1
2
2*N
Divide
Gain(delay_stage)
Gain
s
0.6*sin(2*pi*u)
Transfer Fcn2
Fcn1
Parasiticdelay
freq
Constant2
To Workspace2
Add2
Nominal oscillation
period(To =2Ntd )
Gain=1 , If it is single- ended
Gain=2 , if it is dual inverter
Oscillation
frequency fo
phase
To Workspace1
Integration of fo
= phase
Figure 5-4 Preliminary Simulink model of VCO frequency tuning behaviour.
Due to the natural properties of the multiple-feedback structure of the proposed
dual-inverter delay cell, the oscillation frequency should be doubled as has been
explained in section 3.2.4. This is equivalent to adding an additional gain (=2) with the
frequency domain results. Actually, from the simplified circuit diagram shown in
Figure 5-1, the proposed model can be used for modelling a single-ended current
starved VCO (as shown in Figure 2-5(b)) as well. The differences are for the single
ended current starved VCO, the frequency gain should be set to ―1‖and the number of
A novel noise-aware oscillator model
119
delay stages should be N. Furthermore, notice that the pull-up path is realized by a
PMOS transistor, which indeed treats this differential control voltage (VDD-Vct) as |Vct|.
As a result, the control voltage Vct can be shared by pull-up and push-down paths
simultaneously.
To verify the proposed model, simply substitute the transistor dimensions of the
two design examples illustrated in Chapter 4 to examine the accuracy of the models.
Associated with the process parameters that are listed in Table 1-3, the simulated
oscillation frequency is shown in Figure 5-5, from which the tuning non-linearity can
be easily observed. If compared with the results presented in Chapter 4, the Simulink
models‘ results sit within the same range as the Spectre simulation results and
measurement results. It was never expected that the results from modelling should be
so exactly identical with measurement, since it has been pointed out in that the PVT
variation can make the oscillation frequency vary by up to a factor of 2-3 [4]. The main
result is that the relationship between the oscillation frequency and transistor
dimensions and number of the delay stages are correctly modelled.
Design example 1
Design example 2
800
700
5000
Oscillation frequency (MHz)
Oscillation frequency (MHz)
6000
4000
3000
2000
600
500
400
300
200
1000
100
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCO’s control voltage Vct=Vn (V)
VCO’s control voltage Vct=Vn (V)
Figure 5-5 Design examples‘ oscillation frequency simulated using Simulink
In addition, it is necessary to include the PVT uncertainty within the model. In
other words, the real oscillation frequency must be located within a certain range,
which could be modelled by introducing another coefficient −―Parasticdelay‖ (Figure
5-4). Within the model, in order to make it easier for the user to monitor the frequency
variation, the coefficient is defined to be several multiples (according to simulation, M
could be any value between -2 and 2) of the product of load capacitance and the ON
resistance of transistors Wni/Lni and Wpi/Lpi as expressed by equation (5.8):
Parasticdelay   M  (( Ronn  Ronp)  Cap) , (    )
(5.8)
A novel noise-aware oscillator model
120
The simulation results shown in Figure 5-5 are the case where the ―Parasticdelay‖
is null (M=0). In Figure 5-6, a further series of plot were made by changing factor (M)
from -1.5 to +1.5 and compared them with the post-layout simulation results (RCc
extraction). Obviously, from comparison between two platforms simulation results, it
can be found that some inaccuracy still exists. However, the puspose of creating the
VCO model is to embedded this within an overall PLL model. In this context, the two
important specifications, tuning non-linearity and tuning range, are properly modelled
making the proposed VCO model robust enough when utilizing it within a PLL design.
Design example 1
M=-1.5
1000
M=-0.5
6000
M=0
5000
4000
Simulation (RCc)
3000
M=0.5
2000
M=1.5
1000
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCO’s control voltage Vct=Vn (V)
Oscillation frequency (MHz)
7000
Oscillation frequency (MHz)
Design example 2
1200
8000
M=-1.5
M=-0.5
800
M=0
600
Simulation (RCc)
400
M=0.5
M=1.5
200
0
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
1.1 1.2
VCO’s control voltage Vct=Vn (V)
Figure 5-6 Design examples‘ oscillation frequency when PVT variation is included
5.2 Modelling of VCO noise
When embedding a VCO model within a PLL model, as has been fully analysed
in section 3.1.4, one of the most problematic issues is the modelling of noise. It is
essential to develop a time domain noise modelling approach, and so the origination of
the noise sources and hence the integration of those noise sources to the VCO model
become two major challenges. These challenges are addressed in following sections.
For rough analysis, based on the frequency domain noise models that have been
presented in section 3.2, it is possible to develop an intuitive solution, that is it should
be possible to mathematically convert any frequency domain models into a time
domain model. In other words, if each transistor is treated as a noise generator, it is
possible to simply combine all the noise generators and run the simulation for an
adequately long time. This should give a reasonable result. Indeed, these kinds of
A novel noise-aware oscillator model
121
approaches are normally termed as transient noise analysis and one of the most recent
commercial simulators (Mentor-eldo®) has incorporated this feature.
However, simply creating and combining all the relevant noise generators within
a Simulink model requires large amounts of physical resources (memory) and
simulation time. Therefore, the novel contributions of the model presented below are:
5.2.1

Reasonable assumptions can be made to valid the model.

Simplification of the system to enhance the simulation efficiency.

Integration of the noise model within the total VCO model.
Generation of time domain based flicker noise
In section 3.2.1, a preliminary review of a transistor‘s noise behaviour was
presented. It was shown that equation (5.9) can be used for characterizing a single
transistor‘s noise profile when a hand-calculation is required.


Kf
Vn2,out  ( Sin thermal  Sin  flic ker ) R 2   4kT  gm 
gm2  R 2


COXWeff Leff f


(5.9)
Where R is the load resistance of specific transistor.
Further analysis shows that device‘s corner frequency 1/f can be derived from
equation (5.9). As was highlighted in Figure 3-19, a device‘s corner frequency 1/f is
defined as the frequency point, where the thermal noise level intersects with the flicker
noise level. Therefore, the following relations were obtained as depicted by equation
(5.10).
4kT  g m 
f corner
Kf
CoxWeff Leff f
K f gm
g m2 
(5.10)
1
 fc 

CoxWeff Leff 4kT 
Equation (5.10) and the curves illustrated in Figure 3-19 reveal that the thermal
noise level and corner frequency can be used to characterize a specific transistor‘s noise
profile. Within the frequency bands that are higher than the corner frequency, noise
level is maintained at the thermal noise level, whereas lower than the corner frequency,
the output noise level (V2/Hz) increases with a roll-up factor of 20dB/decade. This
becomes the fundamental theory for the 1/f noise generation functions that are fully
discussed in [86], in which MATLAB based 1/f noise generation code was presented.
A novel noise-aware oscillator model
122
In this project, this 1/f noise generation function has been further developed by linking
it with the transistor dimensions and process parameters.
First of all, the Simulink random number generator built-in block is used to
generate the current mode device‘s thermal noise. The configuration of the block is
shown in Figure 5-7. It should be noted that the variance of the random number is
determined by both the absolute thermal noise level (Sin-thermal) and the system sampling
time (systs) (equation (5.11)). When the proposed noise model is used for the VCO
noise analysis, the system sampleing time (systs) could be set at higher value
(<1/(10*fosc)), which gives a excellent simulation efficiency. However, when the
proposed noise model is utilized within the PLL nosie analysis, a smaller sampling time
(<10ps) is preferred so as to enhance the simulation accuracy.
thermal _ floorn 
Sin thermal
2 systs

4kT  gm
2systs
Figure 5-7 Block definition of the random number generator
Variance 
Sin thermal
2 systs

4kT  gm
2systs
Where gm is the transconductance of a specific transistor.
(5.11)
A novel noise-aware oscillator model
123
Secondly, a bank of single-pole low pass filters are created to produce a noiseshaping filter, which can approximately generate a1/f response [86]. The transfer
function of this noise-shaping filter is given by:
100.5n
2 f c
n
2 s  2 10 f c
n 0
N 1
H ( s)  1  
(5.12)
Where fc is the device‘s corner frequency that is given in equation (5.10) and an N
value of approximately 10 is needed to properly model the 1/f noise. The realization in
Simulink of this noise-shaping filter (equation (5.12)) is illustrated in Figure 5-8:
1
thermal
(10^(-0.5*0)/sqrt(2))*[2*pi*cornern]
Random
Number1
Figure 5-7
s+2*pi*cornern*10^(-1*0)
Transfer Fcn
(10^(-0.5*1)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*1)
Transfer Fcn1
(10^(-0.5*2)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*2)
Transfer Fcn2
(10^(-0.5*3)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*3)
Transfer Fcn3
(10^(-0.5*4)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*4)
Transfer Fcn4
(10^(-0.5*5)/sqrt(2))*[2*pi*cornern]
2
s+2*pi*cornern*10^(-1*5)
Transfer Fcn5
flicker
(10^(-0.5*6)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*6)
Transfer Fcn6
(10^(-0.5*7)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*7)
Transfer Fcn7
(10^(-0.5*8)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*8)
Transfer Fcn8
(10^(-0.5*9)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*9)
Transfer Fcn9
(10^(-0.5*10)/sqrt(2))*[2*pi*cornern]
s+2*pi*cornern*10^(-1*10)
Add2
Transfer Fcn10
Figure 5-8 Simulink model of 1/f noise shaping filter
Two output ports are purposely created for the noise-shaping filter. One is the
thermal noise in current mode and the other is the flicker noise in current mode. It can
be seen later that this configuration enables a deeper analysis of the relationship
A novel noise-aware oscillator model
124
between different types of noise source and VCO‘s phase noise performance to be
made.
thermal
flicker
NoiseN1
noisevf
180
mup
Load Resistor
To Workspace3
noiseif
To Workspace2
Scope3
value=noisevf.signals.values;
f =[1e4:0.1e4:4.9e5,5e5:0.2e5:4.99e6,5e6:0.2e6:5.9e7,6e7:0.2e7:6.9e8,7e8:0.2e8:2.9e9,3e9:0.2e9:5e9];
Fs=1/systs;
[Pxx1,f] = periodogram(value,'', f, Fs);
figure(1)
semilogx(f,((20*log10(Pxx1/(1)))),'-b');
grid on;
Figure 5-9 Testing platform of the flicker noise generator illustrated in Figure 5-8.
To verify the validity of the proposed 1/f noise shaping filter, a testing platform
was created as shown in Figure 5-9. In this example, one of the testing examples that
was presented in Figure 3-19 was used, where an NMOS transistor is biased at 0.9V
and the flicker noise coefficient (Kf) is set at 6x10-24. The filter‘s output signal is
defined as current mode, which requires multiplication with a load resistor (=180Ω) to
give the voltage mode output noise. To calculate the output Power Spectrum Density
(PSD) of this time domain output noise, the MATLAB built-in function
―Periodogram()‖ was used, which can calculate the input data‘s PSD at a specific
frequency with a given system sampling frequency. The necessary post analysis code is
shown in Figure 5-9 and the analytical results are shown in Figure 5-10, in which the
Spectre based simulation results are presented as a comparison.
As expect, Simulink based analytical results almost overlapped with the Spectre
based simulation results. Some slight difference occurrs at the frequency bands
>108Hz, where thermal noise is the dominant source of noise. The reason is because
within the Simulink model, the transconductance gm of the transistor is simply
calculated from a hand calculation equation (8.27), whereas Spectre use an advanced
model to determine the transistor‘s transconductance gm.
A novel noise-aware oscillator model
125
-260
Spectre
-280
Simulink model
Output noise V2/Hz (dB)
-300
-320
-340
-360
-380
-400
-420
-440 4
10
5
10
6
10
7
10
8
10
9
10
10
10
Frequency(Hz)
Figure 5-10 Comparison between Simulink modelling results and Spectre simulation results
(NMOS: W/L=10μm/0.4μm, biasing at VGS=0.9V)
5.2.2
Integration of noise generator into the VCO model
Once the device‘s flicker noise and thermal noise are modelled correctly, the next
issue is to incorporate these noise sources into the VCO model. The difficulty is that
the output signal from the noise generator (Figure 5-8) is in the dimension of current
(A), whereas the purity of VCO‘s output signal are measured with a time domain
dimension, jitter (s), or frequency domain dimension, phase noise (dBc/Hz@offset
frequency). Therefore, a mathematical transformation must be undertaken to link these
two dimensions. Bearing in mind the existing phase noise model that was thoroughly
reviewed in section 3.2.3, intuitively, it seems that equation (3.39) has created a
relationship between these two dimensions. As shown below:
td 
vn
1 td
C   in (t )dt
I
I 0
(5.13)
It shows one simple fact that a noise current (in(t)) integrated for a time interval (td) and
then divided by the pull-up/push-down current(I) can give the specific jitter (∆td)
happening within a specific propagation delay(td). Luckily, the propagation delay (td)
A novel noise-aware oscillator model
126
and pull-up/push-down current (I) can be obtained directly from the model that is
illustrated in Figure 5-3. As a result, for an N stage dual inverter based VCO, with each
stage consisting of 4 transistors, 4N noise generators were created and incorporated
with the existing VCO model.
However, notice that each noise generator requires 11 filters (transfer functions)
to generate the 1/f noise. As a result, 4N noise generators demand 44N transfer
functions. Too many transfer functions will degrade the simulation efficiency of the
proposed model. In addition, the proposed model needs to be a unified model that
simply accepts the number of delay stages (N) as an input variable, but does not make
any modifications to the model‘s structure.
Therefore, some necessary simplification and assumptions need to be made
within the proposed model:
First of all, it is necessary to clarify the combination of noise contributors. Within
the existing reported design [40] and the methodology proposed in Chapter 4, it was
assumed that inverting transistors always have the same dimensions as the cascode
transistors and hence they are lumped into one single noise contributor. This means the
number of noise generators could be halved, which can enhance the efficiency of the
model.
Secondly, for this lumped transistor, the voltage tuning behaviour should be
included. Considering the previous simulation results that were listed in Chapter 4 for
the VCO design examples 1&2, it can be found that when the oscillation frequency
decreases by 50%−70% from its highest operation frequency, in design example1, the
phase noise is almost maintained at the same level, whereas in design example2, the
phase noise level increased by 5−15dB. On the other hand, sticking with the existing
phase noise models that are depicted by equations (3.63) or (3.70), we see that when
the oscillation frequency is halved, the phase noise level is expected to decrease by
6dB-9dB.
The detailed reasons for the noise level changing could be complex, but the
contradiction between the existing phase noise model and the simulation results show
that the voltage-frequency tuning behaviour plays a significant role in the determination
of the phase noise level and must therefore be incorporated into the model.
Modelled within Figure 5-3, was the level of pull/push current (I), mainly
determined by the biasing conditions of the cascode transistors. This means the
A novel noise-aware oscillator model
127
transconductance gm of the lumped transistor is also dependent on the instant control
voltage. In other words, if the inverting transistors‘ dimensions are used to characterize
the lumped transistors and assuming this lumped transistor always works in the
saturation region, its basing condition may need to be determined by the external
VCO‘s control voltage (Vct). As a result, the noise profile of this lumped transistor can
be determined by equation (5.14) and (5.15):
gm _ lump  nCox
fc 
Wni
(Vct  Vtn )
Lni
K f gm _ lump
1
CoxWni  Lni 4kT 

(5.14)
(5.15)
Thirdly, within the procedure of transformation from the electronic domain signal
into the time domain signal, some assumptions need to be made as well. If it is assumed
that the noise current (in(t)) stays at a constant value within that time interval (td),
equation (5.13) can be organized into:
td 
1 td
i
in (t )dt  n td

I 0
I
(5.16)
This means that the instantaneous amplitude of the jitter can be determined with the
ratio of instant noise current to the instant push/pull current and then multiplied with
the nominal propagation delay. Obviously, this relation holds it validity only if the time
interval is short enough.
If the change of the noise current within time interval (td) is noticeable, what is
known is that the spread of the amplitude of the jitter (∆td) is proportional to the length
of the time interval (td) [20] and transconductance, but inversely proportional to the
load capacitance (Cap). Futhermore, it is known that the spread of the amplitude of the
jitter is proportional with the device‘s corner frequency (fc). Within this model, it is
assumed that all these proportional relationships are linear with each other which
allows equation (5.16) to be further evolved as:
td (t ) 
in (t ) td  g m _ lump  (log10( fc))
td 
I
Cap 
(5.17)
As a result, based on above analysis and the equation (5.17), the proposed jitter
generator can be obtained as shown in Figure 5-11, which is a combination of the
propagation delay generator (Figure 5-3) and the noise generator (Figure 5-8). Note that
within this model, the level of noise current (in(t)), the level of the push current (I) and
A novel noise-aware oscillator model
128
the length of propagation delay (td) are all determined by the VCO‘s instantaneous
control voltage, which is one of important improvements of the proposed model.
Propagation
delay td
half_rail
Constant7
VDD
Constant1
1
Vct
Jitter ∆td
In1 Out1
Divide
Rctn1
Divide2
Add
Ronn
Constant4
thermal
Divide1
Cap
Constant8
flicker
NoiseN1
1
Divide3
Divide4
Noise current
generator
Figure 5-8
pushjitter
gm*log10(fc)
Current (I)
Cap
Constant2
Divide5
Figure 5-11 Simulink model of jitter generator (push).
The complete VCO model (includes jitter generators) is shown in Figure 5-12,
which is an evolved version of the VCO model that is shown in Figure 5-4.
1
Constant1
Vct
In1
ControlVoltage
Out1
Pushdelay1
In1
Out1
Pulldelay1
In1
Out1
2*N
Gain2
2
Sqrt(2*N)
Pushjitter
Gain3
In1
Sqrt(2*N)
Gain4
Out1
Pulljitter
Figure 5-11
2*N
Gain1
Parasiticdelay
Constant2
Divide
Gain
1
s
Transfer Fcn2
0.6*sin(2*pi*u)
Fcn1
Scope1
phase
Scope4
Add2
To Workspace1
freq
To Workspace2
Figure 5-12 Proposed Simulink model of VCO, which includes jitter generator
As shown in Figure 5-12, for an N stage dual inverter VCO, which indeed could
be modelled as a 2N stage single-ended current starved VCO, there exists 2N numbers
of PMOS based noise generators and 2N numbers of NMOS based noise generators.
Since all these noise contributors are un-correlated with each other, the total noise
contributions is the square(2N) of sinle noise contributors These noise generators are
then transformed into a jitter value. Summarising these jitter generators with 2N stages
A novel noise-aware oscillator model
129
the push/pull propagation delays give the instant oscillation frequency and output
phase.
It would be interesting to see the instant frequency plot, which is shown in Figure
5-12. Suppose the control voltage (Vct) is equal to 1.2V, using the transistor
dimensions of design example 2 as the input variables and associated process
parameters given in Table 1-3, the instantaneous oscillation frequency is shown in
Figure 5-13. Because noise sources are included, it can be found that the oscillation
frequency randomly wanders from its mean value. The histogram of the Probability
Density Function (PDF) of the oscillation frequency shows that the instant oscillation
frequency is distributed with Gaussian shape from its mean value.
Frequency(MHz)
18000
16000
14000
12000
8000
10000
6000
4000
0
762
761
761
760
760
759
759
758
758
757
757
756
756
755
755
754
754
753
753
752
2000
762
0
20
40
60
80
100
Time (μs)
120
140
160
180
200
752
Figure 5-13 Simulink model based oscillation frequency plot, which includes flicker noise
Although the histogram plot shown in Figure 5-13 reveals frequency spreading,
the amplitude of the spreading is dependent on the instant system-sampling period
(systs). Because the variance of the noise is partially determined by the systemsampling period (Figure 5-7), spreading of the oscillation frequency could be varied
significantly when we change the system sampling period.
As a result, to evaluate the purity of the oscillation frequency, once again, ―phase
noise‖ becomes the target for investigation. As has been illustrated in Appendix B and
previous work [40][93], the power spectral density (PSD) function of extra phase, S(f),
can be approximated to phase noise L ( f ) for large offset. Therefore, from two output
signals (frequency and phase) of our proposed VCO model, we can easily obtain the
time domain extra phase, which is shown in Figure 5-14.
A novel noise-aware oscillator model
Real oscillation
Frequency
Integration
with time
130
Real phase
(noise included)
mean()
Mean of Real
oscillation
Frequency
difference
Integration
with time
PSD()
PSD of extra phase
≈ Phase noise
ideal phase
(noise less)
Figure 5-14 Calculation flow chart: from instantaneous frequency and phase to phase noise.
Based on the proposed VCO model, shown in Figure 5-12, the comprehensive
MATLAB code is shown in Appendix D, which includes the input variable
initialization and post processing of the output frequency and phase.
The corresponding phase noise curves of design example 2 are shown in Figure
5-15, in which the blue curve is directly obtained by running the MATLAB commands
that are listed in Appendix D (Figure D-1 and Figure D-2), whereas the red curve is the
post layout simulation (RCc extraction) results obtained from Spectre. Comapring these
curves, they both have a roll-off factor at 30dB/decade, which is due to the presence of
device flicker noise. The difference is only around 3dB, which make the proposed VCO
model reasonable for the purpose.
-40
Spectre
Phase noise dBc/Hz
-60
Simulink model
-80
-100
30dB/decade
-120
-140
-160
-180 4
10
5
10
6
10
Frequency(Hz)
7
10
8
10
Figure 5-15 Flicker noise induced phase noise plot for design example 2, comparison between
the proposed Simulink model and Spectre based results
To further justify the proposed model, a deeper analysis was made by purposely
changing the noise source from flicker noise to thermal noise (Figure 5-8). As a result,
A novel noise-aware oscillator model
131
according to the theory analysed in section 3.2.2, the phase noise should have a roll-off
factor of 20dB/decade. The simulation result is shown in Figure 5-16, and confirms the
expectation. Meanwhile, the Spectre based simulation result is presented as a
comparison within Figure 5-16.
Simulation time is an important evaluation of any model. Each of the Simulink
based curves shown in Figure 5-15 and Figure 5-16, took 2 minutes and 40 seconds to
generate. Comparing this to Spectre, it would take many hours to obtain the results at
the post-layout analysis stage.
-70
Spectre
-80
Simulink model
Phase noise dBc/Hz
-90
-100
-110
20dB/decade
-120
-130
-140
-150
-160
-170 4
10
5
10
6
10
Frequency(Hz)
7
10
8
10
Figure 5-16 Thermal noise induced phase noise plot for design example 2, comparison between
the proposed Simulink model and Spectre based results
5.2.3
Verifications with simulation examples
The simulation results shown in Figure 5-15 and Figure 5-16 are encouraging, but
in order to justify the proposed model, it must be further verified under a wider variety
of conditions, for example when altering the control voltage.
The plot shown in Figure 5-15 is the case for the design example2 where the
control voltage (Vct) is 1.2V, and further simulation results for a variety of control
voltages (1.0V/0.8V/0.6V/0.4V) are shown in Figure 5-17. It can be found that in the
majority of cases, the proposed model is strongly consistent with the Spectre based
simulation results. The only deviation is in the case where Vct=0.6V and so further
A novel noise-aware oscillator model
132
analysis has been made on this design example. The special features for this design
example (Transistor dimensions listed in Table 4-4) are that main feedback loop (Wp1)
and the sub-feedback loop (Wp3 in design example 2) are chosen as 3:2. If this ratio is
reset to 1:1, it is found that the Simulink model based results are matched with Spectre
based simulation results. This conclusion is further proven with the final measurement
results
-50
-50
Vct=0.8V
Phase noise dBc/Hz
Phase noise dBc/Hz
Vct=1.0V
-100
-150
Spectre
Simulink model
-200 4
10
5
10
6
10
7
10
8
10
-100
-150
Spectre
Simulink model
-200 4
10
5
10
Frequency(Hz)
7
10
8
10
Frequency(Hz)
0
-50
Vct=0.6V
Phase noise dBc/Hz
Phase noise dBc/Hz
6
10
-50
-100
-150
Spectre
-200 4
10
5
-100
-150
Spectre
Simulink model
Simulink model
10
Vct=0.4V
6
10
7
10
8
10
-200 4
10
Frequency(Hz)
5
10
6
10
Frequency(Hz)
7
10
8
10
Figure 5-17 Flicker noise induced phase noise plot for VCO design example 2, comparison
between the proposed Simulink model and Spectre based results with tuning voltage 0.4V~1.0V
The other design examples from the previous Chapter were also investigated with
the proposed model, and the corresponding simulation results with the control voltage
equal set to 1.2V~0.4V are shown in Figure 5-18.
It can be found that in the majority of cases, the difference between Simulink
based simulation results and Spectre based simulation results are negligible, which
strongly supports the proposed model.
A novel noise-aware oscillator model
133
0
Vct=1.2V
Phase noise dBc/Hz
Phase noise dBc/Hz
0
-50
-100
Spectre
-150
Simulink model
-200 4
10
5
6
10
10
7
10
8
10
Vct=1.0V
-50
-100
-150
-200 4
10
Spectre
Simulink model
5
10
Frequency(Hz)
0
7
10
8
10
0
Vct=0.8V
Phase noise dBc/Hz
Phase noise dBc/Hz
6
10
Frequency(Hz)
-50
-100
Spectre
-150
Simulink model
-200 4
10
5
10
6
10
Frequency(Hz)
7
10
8
10
Vct=0.6V
-50
-100
-150
-200 4
10
Spectre
Simulink model
5
10
6
10
7
10
8
10
Frequency(Hz)
Phase noise dBc/Hz
0
Vct=0.4V
-50
-100
Spectre
-150
Simulink model
-200
4
10
5
10
6
10
7
10
8
10
Frequency(Hz)
Figure 5-18 Flicker noise induced phase noise plot for VCO design example 1, comparison
between the proposed Simulink model and Spectre based results with tuning voltage 0.4V~1.2V
To further justify the proposed model, VCO design example 3 is presented. In
this case the proposed dual inverter base VCO is used, but some modifications were
made.

First, the transistor ratio between the main feedback loop and subfeedback loop were purposely made to be large (≈15).

Secondly, the dimensions of the cascode transistors were purposely
reduced by 33% from the inverting transistors.

Thirdly, the number of delay stages was reduced to 3.
As a result, the transistor dimensions of each delay cell are shown in Figure 5-19
and the layout view of the total VCO is shown in Figure 5-20. It can be found that for
the three stage dual inverter VCO, each stage consists of a left half and a right half
portion, which in total corresponds to six identical sections in the layout.
A novel noise-aware oscillator model
134
Vp
Mp2
Mp4
Mp1
Mp3
Mp6
Vgp
Mp5
Vin -
Vout+
Vin +
Vout Mn1
Mn3
Mn5
Mn4
Mn6
Vgn
Mn2
Vn
Vp
Mp2
Mp1
50μ
0.13μ
71.25μ
0.13μ
Vgp
3.75μ
0.13μ
Mp3
50μ
0.13μ
Mp6
75μ
0.13μ
Mp5
Vin -
Vout+
Vin +
Vout -
Mn1
Vn
Mn2
25μ
0.13μ
Vgn
Mn3
17μ
0.13μ
1.25μ
0.13μ
23.75μ
0.13μ
17μ
0.13μ
Mn5
Mn6
Figure 5-19 Schematic of delay cell for VCO design example 3
59μm
91μm
Figure 5-20 Layout of VCO design example 3
A novel noise-aware oscillator model
135
Based on this new design example, the first issue to be justified is the proposed
voltage-frequency tuning behaviour. Using the transistor dimensions shown in Figure
5-19 as the input variable, the corresponding results obtained from our proposed model
are shown in Figure 5-21. Meanwhile, the RCc extraction mode based post layout
simulation results are presented as a reference and these show that the best matching
happens when the ―Parasticdelay‖ parameter M equal 2.
Obviously, it is understood that with different PVT conditions, the real oscillation
frequency could be varied significantly, but the result shown in Figure 5-21 indicates
that the result obtained from the proposed model is sits in same range as the advanced
post-layout model based result.
4500
Oscillation frequency (MHz)
4000
Simulink M=2
3500
3000
Kvco≈ 5GHz/V
2500
Simulation (RCc)
2000
1500
1000
500
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
VCO’s control voltage Vct=Vn (V)
Figure 5-21 Voltage frequency tuning behaviour of design example 3 (Simulink modelling
results and RCc extraction mode based post layout simulation result.)
The next issue is the phase noise performance for different VCO control voltages.
Once again, the results obtained from two platforms are shown together for comparison
in Figure 5-22. As in the previous example, the biggest difference occurs when the
control voltage drops to the lower end, but even then the difference is not great.
Phase noise dBc/Hz
136
0
Phase noise dBc/Hz
0
Vct=1.2V
-50
-100
Spectre
-150
Simulink model
-200
4
10
5
10
6
10
Frequency(Hz)
7
10
8
10
Vct=0.8V
-50
-100
Spectre
-150
Simulink model
-200 4
10
5
10
6
10
Frequency(Hz)
Vct=1.0V
-50
-100
-150
Spectre
Simulink model
-200
4
10
5
10
6
10
7
10
8
10
Frequency(Hz)
0
Phase noise dBc/Hz
Phase noise dBc/Hz
Phase noise dBc/Hz
A novel noise-aware oscillator model
7
10
8
10
0
Vct=0.6V
-50
-100
-150 4
10
Spectre
Simulink model
5
10
6
10
Frequency(Hz)
7
10
8
10
0
Vct=0.4V
-50
-100
Spectre
-150
Simulink model
-200 4
10
5
10
6
10
7
10
8
10
Frequency(Hz)
Figure 5-22 Flicker noise induced phase noise plot for design example 3, comparison between
the proposed Simulink model and Spectre based results with tuning voltage 0.4V~1.2V
It was shown in section 3.1.4, that moderately increasing the PLL‘s loop
bandwidth can easily suppress a few dBs a noise originating from the VCO. It will be
further demonstrated in section 5.3, that any external noise source can dramatically
overwhelm the VCO noise performance, which makes a few dBs noise level difference
negligible.
5.2.4
Advanced flicker noise modelling in control module
A comprehensive time domain Simulink based VCO model has been created,
which is ready to be utilized for the modelling and design of a PLL. However, flicker
noise in the VCO‘s control module has so far been ignored within the analysis and must
now be considered.
In section 3.2.3, it was shown that flicker noise in the control module plays a
more significant role than any other noise source in the oscillator circuit. In order to
eliminate this noise source, within the above design example, two differential control
voltages were used to make a voltage-frequency tuning. If these VCO designs were
used within a PLL, a differential charge pump must be created, which can generate two
differential control voltages. However, the realization of a differential charge pump
A novel noise-aware oscillator model
137
may considerably increase the system complexity, since it requires a Common Mode
Feed Back (CMFB) structure to be incorporated.
In contrast, if a single-ended (Figure 3-10) charge pump is chosen, as has been
illustrated within Figure 2-5, a current mirror is required to generate the approximate
differential control voltages. Therefore, the motivation for this section is to correctly
model the flicker noise in the control module and hence conclude the design guideline
for the voltage control module (current mirror). The theoretical circuit diagram used for
modelling is shown in Figure 5-23, in which a current mirror (Mcn/Mcp) has been
created to generate approximate differential control voltages.
Mcp
Mp2
Mp2
Mp6
Mp4
Mp1
Vgp
Mp1
Mp5
Mp3
Vout+
Vout -
Vout Mn3
Mn1
Mn5
Mn1
Vgn
Vct
Mcn
Mn2
Mp5
Mp3
Vin -
Vout+
Vin +
Mp6
Mp4
Vgp
Mn3
Mn5
Mn4
Mn6
Vgn
Mn4
Mn6
Mn2
Figure 5-23 Dual inverter based VCO together with the voltage control module.
It it shown in [20] and was reviewed in section 3.2.3, within this current mirror
structure, that the diode connected transistor is the major noise contributor, which is
Mcp in this design example. Consequently, using the noise current generator function
that has been created in Figure 5-8, the corresponding noise current can be generated,
with its PSD dependent on the specified transistor dimensions. The main aspect
needing to be explained is that this noise current is then transformed to the voltage
mode noise by multiplying the noise current with the output resistance of Mcp. At this
stage, we cannot find a simplified equation for calculating the output resistance of a
specific transistor. As a result, a Spectre based DC analysis may have to be made in
advance to obtain the necessary output resistance (1/gds) value and then this value used
within the proposed model. The complete model is shown in Figure 5-24, which is an
extended version of the previous VCO model that was shown in Figure 5-12. It can be
seen that a voltage mode noise is summed with the instant control voltage and then the
―pulldelay‖ and ―pulljitter‖ cells are applied, which exactly describe the noise
modulation mechanism in the real case (Figure 5-23).
A novel noise-aware oscillator model
138
1
Constant1
2*N
Gain1
In1 Out1
Pushdelay1
In1
2*N
Gain2
Out1
Pulldelay1
In1
Pushjitter
In1
2
Sqrt(2*N)
Gain3
Out2
Transfer Fcn2
1
s
Divide
Gain
Sqrt(2*N)
Gain4
Out1
Pulljitter
Fcn1
Scope1
phase
Scope4
Parasiticdelay
Constant2
0.6*sin(2*pi*u)
To Workspace1
freq
To Workspace2
Add2
Vct
ControlVoltage
thermal
flicker
NoiseMcP
1/gdsMcp
Constant3
Scope2
mutiply
Add1
Figure 5-24 Proposed Simulink model of VCO including voltage control module included
Focusing on design example 2 from Chapter 4 and modelled in the last section,
an investigation is made into the transistor dimensions of Mcp and Mcn. Four
analytical cases were created with differences in both transistor dimensions (Table 5-1).
In order to make a fair comparison, the differential control voltages generated from the
control module were designed to be almost identical (Vct=1.2V), resulting in almost
identical oscillation frequencies.
Table 5-1 Transistor dimensions of analytical design cases, which are created for voltage
control module‘s noise analysis.
Case1
Case2
Case3
Case4
Mcn
0.15µm/0.13µm
2µm/0.4µm
16µm/0.4µm
160µm/1µm
Mcp
0.45µm/0.13µm
6µm/0.4µm
48µm/0.4µm
480µm/1µm
gdsof Mcp
23µ
44.77µ
374.4µ
849.2µ
However, a significant difference is apparent for the phase noise performance of
these four design examples, which is shown in Figure 5-25. As in the previous design
example, both the Spectre based Post layout simulation results and the Simulink model
based results were obtained. As expected, the phase noise results obtained from two
platforms show a tiny difference for these four analytical design cases, which once
again, confirms the accuracy of the proposed VCO model.
A novel noise-aware oscillator model
0
W
MCP = 0.45μ
L
0.13μ
MCP
-50
Phase noise dBc/Hz
Phase noise dBc/Hz
0
-94.31dBc/Hz
-100
-150
139
Spectre
-50
-107.9dBc/Hz
-100
-150
Spectre
Simulink model
Simulink model
-200
4
10
W
MCP = 6μ
L
0.4μ
MCP
5
6
10
7
10
10
-200
4
10
8
10
5
10
Frequency(Hz)
-100
-113.9dBc/Hz
-150
Spectre
-100
-150
-114.7dBc/Hz
Spectre
Simulink model
5
10
8
10
W
MCP = 480μ
L
1μ
MCP
Simulink model
-200
4
10
7
10
-50
W
MCP = 48μ
L
0.4μ
MCP
Phase noise dBc/Hz
Phase noise dBc/Hz
-50
6
10
Frequency(Hz)
6
10
7
Frequency(Hz)
10
8
10
-200
4
10
5
10
6
10
Frequency(Hz)
7
8
10
10
Figure 5-25 Flicker noise induced phase noise plot for VCO design example 2, with different
transistor dimensions in the voltage control modules
The reason these four analytical cases were created was to investigate the
relationship between the transistor sizing decision of the voltage control module and
the phase noise performance, although this relation has been preliminarily explained by
equation (3.74)(5.18):
L( f )  A
 1

COXWMcp LMcp  Veff2
Kf
  f 02 
  3 
 f 
(5.18)
However, equation (5.18) only reveals one design guideline, that is: increasing the
transistor dimensions can decrease the phase noise. Our proposed model further
indicates that a lowering of the output resistance is another essential requirement for
decreasing the phase noise. To lower the output resistance, from equation (8.13), it
means a higher current is required, which means a higher ratio of W/L is required.
Furthermore, making a close observation of these four analytical cases, it can be
found that case 3 and case 4 deliver the best phase noise performance. Obviously, this
is due to the effect of a longer transistor length and a bigger ratio of W/L, all of which
are meeting the design guidelines. Indeed, the simulation results shown in Figure 5-15
show that the VCO‘s noise performance is about -115dBc/Hz, which means the <1 dB
difference in phase noise performance between case 3 and case 4 could be ignored.
However, the price paid for the 1dB difference is that case 4 uses a particularly big
A novel noise-aware oscillator model
140
transistor within the control module. DC analysis of these transistors shows the gate
capacitance of transistor Mcn (160µm/1µm) in case 4 is about 1.8pF. If this VCO is
used within a wideband PLL design, such a big input capacitance seen by the loop filter
will surely influence the PLL‘s loop stability. Therefore, we believe the transistor
dimensions of case 3 are more practical and reasonable when using the approch with a
practical design.
5.3 Realization of prototype chip 2
The second prototype chip contained an implementation of the VCO design
examples 1 and 2 that were realized with first prototype chip with some modifications
made to validate the proposed VCO model. (Figure 5-26)
Firstly, the voltage control module was included, with the transistor dimensions
set as Case 3 in Table 5-1.
Secondly, for the VCO design example 2, the transistor dimensions between the
main feedback loop and sub-feedback loop were set with a ratio of 1:1, which was 3:2
in the first prototype chip.
Thirdly, frequency dividers have been avoided in this prototype chip to ensure
testing can be made directly at the output of the oscillator.
(a)
(b)
(c)
VCO
Design example 1
Vout+
Vout -
VCO
Design example
2_1
Vout+
VCO
Design example
2_2
Vout+
Vout -
Vout -
Buffer
Differential
→Single
Common
source
Output Buffer
Probepads
Probe
station
testing
Buffer
Differential
→Single
Common
source
Output Buffer
Probepads
Probe
station
testing
Buffer
Differential
→Single
Common
source
Output Buffer
Bonding
-pads
On board
testing
Figure 5-26 Top level structure of chip 2
As shown in Figure 5-27, a common source output buffer was created. According
to the post-layout simulation (excluding the parasitic resistance), this buffer is capable
of driving a capacitance of 3pF in series with a 50Ω resistor at a frequency of 6GHz.
A novel noise-aware oscillator model
2.0 m
0.13 m
6m
0.13 m
2.0 m
0.13 m
18 m
0.13 m
141
54  m
0.13 m
162  m
0.13 m
Clk_out
Clk_in
3pF
10 m
0.13 m
1 m
0.13 m
3 m
0.13 m
9m
0.13 m
27  m
0.13 m
50
81 m
0.13 m
Figure 5-27 Schematic of the output buffer
In the case of design example 2, which has a lower oscillation frequency, it was
decided to test the VCO using both probe pads and conventional bonding pads. Two
identical designs were therefore created with identical transistor sizing for the VCO and
output amplifier the only difference being that one design was to be measured by the
on-chip probe pads, and the other with a normal PCB based approach. A comparison
will be made between these two approaches in order to obtain experience for designs.
The layout view of final chip is shown in Figure 5-28, from which 9 probe pads,
three oscillator designs, and output buffer designs can be observed. The large array in
the top left of the chip was not part of this project.
Figure 5-28 Entire chip layout
A novel noise-aware oscillator model
142
5.4 Measurement of prototype chip 2
5.4.1
PCB design
The all layer view of the evaluation PCB for the second prototype chip is shown
in Figure 5-29. The complexity of this layout is much reduced compared to the first test
PCB (Figure 4-9), with the aim of eliminating potential unwanted interference from
peripheral components on board. The board can be divided into three parts: power
supply, voltage tuning and output connector.
From previous work [53], a battery is considered to be a good candidate to
provide a constant noiseless DC level voltage source for the VCO design testing. Since
the st12 process requires a 1.2V power supply, a regulator is used to provide constant
1.2V voltage source. Furthermore, as it has been assumed that the 3V voltage provided
by the battery has negligible noise, it was decided that the control voltage Vct should
be obtained directly through a voltage divider function, which divides the 3V voltage
with a ratio and hence generates an instant control voltage (<1.2V). To ensure the
integrity of the control signal, large capacitors (several µf) are embedded between the
control node and the ground. The SMA connector is used as the output interface, which
is then followed by a chosen adaptor, which bridges the connection between the
BNC/Type-N interface of the oscilloscope/spectrum analyzer to the SMA connector.
External power @3.0V
(Before regulate)
Inernal power @1.2V
(After regulate)
Vout
Ground
Voltage
divider
Vct
Figure 5-29 All layer view of chip 2 evaluation PCB
A novel noise-aware oscillator model
5.4.2
143
Time domain measurement results
An Agilent DSO80204B Infiniium oscilloscope, which has a 40GHz sampling
frequency and 2GHz bandwidth, was used to make the time domain signal purity
measurements.
Tuning range
The first design target of the improved oscillator was the wide tuning range that
was discussed in Chapter 4. Without any frequency division, the output signal of the
oscillator can be measured directly.
Tuning range
900
843MHz
Oscillation frequency(MHz)
800
Simulation
Measurement
700
600
748.3MHz
500
400
300
200
197KHz
100
0
0
0.2
0.4
0.6
0.8
Control Voltage(V)
1.0
1.2
1.4
Figure 5-30 Tuning range of design example 2.
The measured tuning range is shown in Figure 5-30, from which it can be seen that
the tuning range is 748.3MHz ---197KHz (more than 11 octaves). The post layout
simulation (STAR_RCxt RCc) results were plotted for comparison. It can be seen that
some differences still exist between the simulation results and measurement results
when the control voltage is higher than 0.6V. However, if compared with the results
(Figure 5-6), which are obtained from the proposed Simulink based model, it is found
that above measurement result is still consistent with the results that were predicted
from the proposed model. The output signal at 748.3MHz and 197KHz as seen on an
oscilloscope are illustrated below in Figure 5-31 and Figure 5-32.
A novel noise-aware oscillator model
Figure 5-31 Output signal at 748.3MHz
Figure 5-32 Output signal at 197KHz
144
A novel noise-aware oscillator model
145
Jitter
The measured jitter (rms/p-p) and the corresponding percentage (%) to the
oscillation period over the full tuning range are shown in Figure 5-33 and Figure 5-34.
rms jitter
rms jitter/oscillation period
70
0.20
63.87ps @8.07MHz
RMS jitter(ps)
50
40
2.34ps @441.87MHz
30
8.75ps
@48.13MHz
20
2.41ps
@748.3MHz
10
0
0.2
0.4
0.6
369.97MHz
0.18
RMS jitter (% of period)
60
0.8
Control voltage(V)
1.
0
748.3MHz
0.16
0.14
0.12
0.10
8.07MHz
0.08
505.35MHz
0.06
1.2
0.04
0.2
0.4
0.6
0.8
Control voltage(V)
1.0
1.2
Figure 5-33 Measured rms jitter (left) and as a percentage of oscillation period (right).
p-p jitter/oscillation period
p-p jitter
2.0
700
369.97MHz
644.9ps @8.07MHz
600
1.8
1.6
p-p jitter (% of period)
p-p jitter (ps)
500
400
20.95ps @441.87MHz
300
84.26ps
@48.13MHz
200
20.49ps @748.3MHz
100
1.4
748.3MHz
1.2
1.0
0.8 8.07MHz
0.6
0
0.2
0.4
0.6
0.8
Control Voltage(V)
1.0
1.2
0.4
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Control Voltage (V)
Figure 5-34 Measured p-p jitter (left) and as a percentage of oscillation period (right).
Using the highest oscillation frequency as an example, the PDF function of
measured jitter is shown in Figure 5-35, from which it can be found that the rms jitter
(std Dev) is 2.41ps, and the peak to peak jitter is 20.49ps. It is important to note that the
distribution of the jitter and the frequency display a Gaussian shape, this is consistent
with the results obtained from the proposed model (Figure 5-13).
A novel noise-aware oscillator model
146
Figure 5-35 Measured jitter histogram at 748MHz
5.4.3
Frequency domain measurement results
As has been illustrated many times in previous section, the most important
specifications of the VCO design is the phase noise plot. In this project, the phase noise
result is measured on an Agilent E4443A 3Hz-6.7GHz spectrum analyzer.
Frequency spectrum to phase noise
The definition of phase noise and the relationship between the phase noise value
and the absolute signal power is explained in section 3.2 and illustrated in Figure 2-8.
Therefore, it is interesting to plot the output signal spectrum and its corresponding
phase noise in the case of the measured chip.
Comparing the signal spectrum and phase noise spectrum shown in Figure 5-36
and Figure 5-37, it can be found that the absolute signal power at an offset of 1MHz
from carrier is about -60dB smaller than the peak power of carrier. Furthermore, the
measured phase noise value at 1MHz is -112.8dBc/Hz, which is the product of the
single sideband power at 1MHz offset frequency divided by the total carrier power in
full bandwidth.
A novel noise-aware oscillator model
147
The phase noise spectrum shows a roll off speed of -30dBc/Hz/decade, which
means that the flicker noises are the dominate noise sources. In addition, it would be
important to note that the results shown in Figure 5-37 are approximately consistent
with the modelling results and simulation results shown in Figure 5-15.
Figure 5-36 Measured signal spectrum at 746MHz with 100MHz/2MHz span using PCB based
appraoch
Figure 5-37 Measured phase noise at 744MHz using PCB based approach.
Phase Noise over tuning range
Besides the phase noise level at certain specific frequencies, it is interesting to
investigate the phase noise variation trend with the voltage tuning mechanism that is
A novel noise-aware oscillator model
148
modelled in sections 5.2. The measured phase noise plots among variety voltage signals
are shown in Appendix C and are summarized within Table 5-2. Furthermore, the
spectre based post layout simulation results are listed within bracket.
Table 5-2 Measured phase noise over full tuning range
Effective Control
Oscillation
Measured Phase Noise (dBc/Hz)
voltage (V)
frequency (MHz)
(Spectre simulation results)
1.2
1.06
0.93
0.8155
0.7157
0.619
0.5
0.414
0.353
743.6
721.7
685.2
646.1
569.8
455.7
288.9
164.9
97.55
100KHz offset
1MHz offset
10MHz offset
-82.23
-112.8
-140.25
(-84.1)
(-113.9)
(-141.3)
-73.1
-112.25
-140.06
(-84.0)
(-113.8)
(-141.2)
-69.38
-112.55
-139.38
(-83.7)
(-113.6)
(-141.0)
-87.24
-112.26
-139.66
(-83.4)
(-113.3)
(-140.5)
-75.56
-109.14
-137.81
(-83.1)
(-113.1)
(-140.1)
-78.27
-109.45
-136.00
(-82.6)
(-112.6)
(-139.5)
-79.42
-107.35
-134.75
(-82.7)
(-112.7)
(-139.8)
-81.8
-109.32
-135.28
(-83.9)
(-113.8)
(-140.2)
-83.17
-110.66
-136.6
(-85.7)
(-115.6)
(-143.2)
Among the majority of control voltages, the variations of phase noise at 1MHz
and 10MHz offset from the carrier are less than 5dB, which is consistent with the
prediction of the proposed model and spectre based simulation results. The ramp in the
phase noise spectrums within the frequency offset of <100 KHz is likely to be due to
the noise of the DC voltage source, which is not modelled within this project.
5.4.4
Discussion of probe pads based measurement results
The measuring platform for probe pad measurement is shown in Figure 5-38.
A novel noise-aware oscillator model
149
Figure 5-38 RF probe pads based measuring platform
The chip is soldered within a specially designed PCB, which is fixed within the
RF probe station. Three DC signals were applied to the PCB, which are the power,
ground and instant control signal of the VCO. A RF probe with GSG configuration is
applied to the probe pads of the chip. The die photo of the chip and GSG probe pads is
shown in Figure 5-39.
Figure 5-39 Die photo of the chip being measureing
A novel noise-aware oscillator model
150
The final measurement results from this approach are much worse than the PCB
based results. Take for example, based on the identical VCO and buffer designs and
applying with same control voltage, the output spectrum and phase noise plot are
shown in Figure 5-40 and Figure 5-41. If compared with results shown in Figure 5-36
and Figure 5-37, it can be find that phase noise performance is 30dB worse.
Firstly, it has been pointed out that in order to reduce the parasitic capacitance,
only the top two metal layers are used with this prove pad layout. This kind of structure
makes the pads very sensitive to physical pressure applied by the probes. When the
pressure was slightly increased, the pads were physically damaged and unable to be
used. Therefore, it seems another new structure of pads needs to be created which uses
all the metal layers while minimizing the effective capacitance.
Secondly, impedance matching is another issue should have been more carefully
considered. Specifically, the equivalent impedance model of these pads and probes may
need to be modelled before creating the buffer.
Figure 5-40 Measured signal spectrum at 752MHz using RF probe pads based approach
A novel noise-aware oscillator model
151
Figure 5-41 Measured signal spectrum at 752MHz using RF probe pads based approach
5.5 Summary
The main conclusion of this chapter is that the measurements results obtained
have demonstrated the validity of the proposed noise aware VCO model. In particular,
the measurement results and the model based analytical results are consistant across the
majority of the voltage tuning range. One of the advantages of the proposed model is
that it can directly help with the transistor sizing decisions, however, the most
important utilization of the proposed model is to embed it within a PLL model, which
is the research target in next chapter.
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152
A novel noise aware PLL model and low-noise PLL
153
Chapter 6 A novel noise aware
PLL model and low-noise PLL
The first focus of this chapter is the implementation of a new PLL model, which
should correctly model all the noise sources and non-ideal effects within a practical
PLL circuit. The second focus is to use the proposed new PLL model as a research
platform to design a novel PLL structure with improved noise performance.
6.1 Two PLL (type II) design examples
The importance of PLL loop bandwidth selection has been highlighted many
times previously in this work. Therefore, the first two PLL design examples have been
purposely created to illustrate this important issue. Both of the examples have the same
fundamental structure as shown in Figure 6-1, but PLL design example 1 has an open
loop bandwidth of 25MHz, whereas PLL design example 2 has a loop bandwidth at
4MHz.
A novel noise aware PLL model and low-noise PLL
Icp
154
Using the adaptivebandwidth biasing
technique(Circuit topology
shown in Figure 3-10)
KPFD
ɸin
KF
up
data
PFD
ɸdclock
dclock
KVCO
VinVCO
VCO
ɸout
R
down
C2
C1
Icp
ɸdclock= ɸout /N
÷16
Figure 6-1 Block diagram of a typical charge pump PLL
The VCO used within these PLL design examples is the VCO design example 1
that has fully analysed and modelled in the previous two Chapters. From the simulation
results shown in Figure 5-6, when the instant control voltage is at 0.6V-0.7V, the
oscillation frequency is about 2.1GHz-2.6GHz and the gain of the VCO (KVCO) is
approximately 5GHz/V. Therefore, after substituting this fixed VCO gain (KVCO) into
the open loop transfer function of the PLL (equation (2.34)), the selection of loop
bandwidth has to be realized with a necessary adjustment at the charge pump current
and loop filter‘s component value. In Table 6-1, the resulting calculated design
specifications of these two PLL examples are listed. In Figure 6-2 and Figure 6-3, the
corresponding bode plots of the open loop transfer function of these two design
examples are shown, from which the large loop bandwidth can be observed.
A novel noise aware PLL model and low-noise PLL
155
Table 6-1 Specifications of PLL design example 1 & 2
Dimensions
PLL design
PLL design
example 1
example 2
Loop bandwidth
≈25MHz
≈4MMz
Charge pump current (Icp)
100µA
10µA
R(effective)
5KΩ
8KΩ
C1
6pf
10pf
C2
0.3pf
0.5pf
Damping factor (ξ)
≈1.08
≈0.707
Reference signal frequency(Fref)
150MHz
150MHz
Divider ratio(N)
16
16
Gain of VCO(KVCO)
5GHz/V
5GHz/V
Magnitude (dB)
100
20MHz-25MHz
50
0
-50
Phase (deg)
-100
-90
-120
-150
-180
5
10
10
6
10
7
10
8
10
9
10
Frequency (Hz)
Figure 6-2 Bode plot of open loop transfer function of PLL design example 1
10
A novel noise aware PLL model and low-noise PLL
156
60
Magnitude (dB)
40
4MHz
20
0
-20
-40
-60
Phase (deg)
-80
-90
-120
-150
-180
5
10
10
6
10
7
10
8
10
9
Frequency (Hz)
Figure 6-3 Bode plot of open loop transfer function of PLL design example 2.
The PFD is realized using the circuit diagram shown in Figure 3-4. The frequency
divider is realized with a three-stage TSPC frequency divider (Figure 2-22) and one
stage D Flip-Flop based frequency divider (Figure 2-23). The charge pump and loop
filter are realized with the feature of adaptive biasing, which has been fully analysed in
section 3.1.3 and the circuit diagram is shown in Figure 3-10. The only difference is the
transistor dimensions within the charge pump and loop filter, which are adjusted to
meet with the design specifications listed in Table 6-1.
The transistor level simulation is made at partially post-layout level by using the
hierarchy-editor. Among all the components of the PLL, only the VCO is simulated at
the post-layout level (RCc extraction mode). The loop settling behaviour of these two
design examples are shown in Figure 6-4 and Figure 6-5, respectively.
A novel noise aware PLL model and low-noise PLL
157
1.3
0.648
1.2
0.647
0.646
0.645
0.644
1.1
0.643
Voltage(V)
0.642
5.6mV 0.641
1
0.64
0.639
0.638
0.9
345
350
355
360
365
370
375
380
385
0.8
0.7
0.6
0.5
0
100
200
Time(ns)
300
400
500
Figure 6-4 Transistor level simulation results (Spectre) of PLL design example 1
1.3
0.646
1.2
0.644
0.642
Voltage(V)
1.1
0.64
6.3mV
1
0.638
2.24
0.9
2.26
2.28
2.3
0.8
0.7
0
0.5
1
1.5
2
2.5
3
Time(μs)
Figure 6-5 Transistor level simulation results (Spectre) of PLL design example 2
The settling time of PLL design example 1 is about 300ns, whereas the settling
time for PLL design example 2 is about 1.8μs. Note that settling time is a direct
reflection of the loop bandwidth defined by the equation (3.9), thus it is believed that
A novel noise aware PLL model and low-noise PLL
158
these two PLL design examples successfully meet the bandwidth requirement.
However, the important consideration behind the selection of the loop bandwidth is the
degree of noise suppression among different noise sources. If it is required to make a
further analysis of the system‘s noise figure, the noise transfer functions listed in Table
3-2 have to be utilized. However, incorporating the noise analysis within the time
domain loop‘s settling behaviour analysis could considerable alleviate the complexity
of the PLL design.
6.2 Realization of the proposed new PLL model
6.2.1
Model of PFD
The example circuit of the PFD has been shown in Figure 3-3, which is formed
using many standard digital gates. When creating the model for this digital transmission
gate, the non-ideal effects must be included by considering that propagation delay of
these digital gates. Using the St12 process, the transistor level transient simulation
results show that the typical propagation delay for these digital gates is about 5ps-10ps.
Therefore, for each digital gate, a ―transport delay‖ module is incorporated with its
―time delay‖ parameter set at 10ps, which is the longest propagation delayhappened
within the digital gate.
One of the special concerned module is the NAND4 (Figure 6-6) gate, which is
embedded within the PFD as been highlighted in Figure 6-7. It has been demonstrated
in section 3.1.1 that the width of the PFD‘s output pulse is indeed defined by the
propagation delay of this NAND4 module. Stick to the simulation results shown in
3.1.1, this pulse width is purposely set at 250ps within all of following simulations.
Furthermore, as shown in Figure 6-7, two ―Rate limiter‖ is embedded within the output
port of the PFD, which indeed define the maximum allowable slew rate of the output
signal. In the following simulation, according the transistor level simulation results, this
rate is defined at ±50GHz.
A novel noise aware PLL model and low-noise PLL
1
>= 0.5
In1
Compare
To Constant1
2
>= 0.5
In2
Compare
To Constant2
NAND
3
In3
159
double
Logical
Operator
1
Transport
Delay
Data Type
Conversion
Out1
>= 0.5
Compare
To Constant3
4
>= 0.5
In4
Compare
To Constant4
Figure 6-6 Modelling of the digital gate with propagation delay (NAND4)
NAND2
NOT
NAND8
Out1
1
In1
NOT3
NOT2
In1
Out1
In1
Out1
In1
Out1
In2
In1
In1
In2
In3
Out1
NOT6
In1
1
Out1
Rate
Limiter
Out1
NAND1
In1
In2
Out1
NAND3
In1
NAND7
Out1
In2
In1
In2
In3
In4
NAND4
In1
In2
Figure 6-6
Specified with 250ps
propagation delay
Out1
Out1
NAND5
In1
Out1
In2
NOT1
2
In1
Out1
In2
NAND6
NOT4
NOT5
In1
In2
In1
Out1
Out1
In1
Out1
NAND9
In1
In2
Out1
In3
NOT7
In1
2
Out1
Rate
Limiter1
Out2
Figure 6-7 Modelling of the PFD
6.2.2
Model of frequency divider
It has been shown in 2.2.1 that frequency divider can be realized using D-Flip-
flops. Therefore, as shown in Figure 6-8, using the standard model ―D Flip-Flop‖ from
the Simulink library, the frequency divider can be modelled. Same as other digital gates
that have been realized within PFD model, a transport delay (set at 50ps) is
incorporated as well.
A novel noise aware PLL model and low-noise PLL
D
Q
1
CLK
In1
!CLR !Q
1
Constant
160
double
Data Type
Conversion
1
Transport
Delay
Out1
D Flip-Flop
Figure 6-8 Modelling of the frequency divider
6.2.3
Model of charge-pump
The model of the charge pump has a similar structure to that illustrated in [64].
Besides a user defined current amplitude, the degree of the charge pump current
mismatch can either be modelled at the amplitude level by specifying different ―gain‖
value or could be modelled at different transmission delay by specifying different
values for propagation delay at push down and pull up paths.
1
1
In1
Mutiply
Gain1
Transport
Delay (up)
1
Out1
2
In2
1
Mutiply
Gain2
Transport
Delay (down)
100e-6
Charge_pump
Current
thermal
flicker
NoiseCP1
Figure 6-9 Modelling of the charge-pump with mismatch control
The approach of generating noise current from a given transistor dimensions has
been thoroughly explained in section 5.2.1. Therefore, with the transistor dimensions in
the charge pump module, the corresponding noise level could be modelled
approximately.
A novel noise aware PLL model and low-noise PLL
161
A question arises about the transistor sizing decisions of the transistors within the
charge pump. Within the model, firstly, from equation (5.10), it can be found that with
the same DC biasing condition, bigger transistor length and width can lead to a lower
corner frequency of the flicker noise. Therefore, to minimize the flicker noise
contribution, in the practical circuit realization and also in the circuit modelling
examples illustrate below, the transistor length was purposely set at 1µm.
6.2.4
Comprehensive PLL model.
Until this stage, all the components within a typical charge pump PLL have been
modelled individually, except the loop filter. As shown in Figure 6-10, a transfer
function, with its numerator and denominator coefficients specified with loop filter‘s
component (R&C) values, can be used to depict the behaviour of a loop filter. Besides
this, the noise contribution from the effective resistor(R) can be modelled by using the
same approach as the noise generation function used in charge pump and VCO.
Within the previous VCO‘s phase noise analysis, the mean value of the VCO‘s
oscillation frequency was denoted as the central frequency, which was then used to
define an ideal noise-less phase generator. Within the PLL model, the reference
frequency applied to the PFD could be directly used as the source of phase generator.
As a result, the phase noise result is obtained by processing the phase difference (phase
offset) between the instant VCO‘s output phase and the integration of reference
frequency as shown in Figure 6-10.
Scope8
totalphase
0.6
VDD
Constant1
Scope1
Constant2
Scope2
To Workspace1
Out1
Reference
Clock
In1
In2
Out1
In1
In2
Out2
(5e3*6e-12)s+1
Out1
(6e-12*0.3e-12*5e3)s +(6e-12+0.3e-12)s
Charge_pump
PFD
Saturation
Loop Filter Transfer Fcn1
flicker
vct_control
RLF
Constant3
To Workspace3
Divide
In1
Frequency_divider4
Out1
In1
Frequency_divider3
Out1
1
s
(1/6.67e-9)*16
Reference Frequency
Out1
Out2
VCO
thermal
Noise of
LoopFilter
Scope3
In1
2
In1
Frequency_divider2
Out1
In1
Compare
To Zero
Transfer Fcn2
phaseoffset
To Workspace2
<= 0
Frequency_divider1
Scope5
Figure 6-10 Model of the comprehensive PLL
To justify the proposed model, firstly, the PLL design example 1 was used. The
corresponding design specifications and component values listed in Table 6-1 are used.
A novel noise aware PLL model and low-noise PLL
162
The analysis starts from the ideal case where both the charge pump and loop filter are
assumed to be noise-less and mismatch has been disabled within the simulation.
1.3
0.6697
1.2
0.6673
1.1
0.6648
0.6623
Voltage(V)
1.0
0.6598
0.9
310
320
330 340
350 360
0.8
0.7
0.6
0.5
0.4
0
100
200
300
400
500
Time(ns)
Figure 6-11 Settling behaviour (vco_control) of PLL design example 1, obtained within
Simulink model (excluding in-band noise and without charge pump mismatch)
The settling behaviour of the VCO‘s control voltage is shown in Figure 6-11. If
compared with the transistor level simulation results shown in Figure 6-4, it can be
found that the settling time are almost the same. Furthermore, the most meaningful
information obtained from the proposed PLL model is that small ripple voltage happens
at the VCO‘s control node, as been highlighted in Figure 6-11. It would be important to
note that our proposed VCO model has included the all the devices noise, which are
directly specified with the transistor dimensions.
In order to further justify the proposed model, the phase noise plot of the PLL‘s
output signal is of interest. As shown in Figure 6-12, both the VCO‘s free running
phase noise plot and PLL‘s phase noise plot are shown, and the attenuation to the
VCO‘s noise components that are less than the PLL‘s loop bandwidth can be clearly
observed.
A novel noise aware PLL model and low-noise PLL
163
-60
VCO free running
PLL
-80
Loop
bandwidth≈25MHz
Phase noise dBc/Hz
-100
-120
-140
-160
-180
-200 5
10
6
10
7
10
8
10
9
10
Frequency(Hz)
Figure 6-12 Phase noise curve of the PLL design example 1 obtained from Simulink (excluding
in-band noise and without charge pump mismatch)
Obviously, the results shown in Figure 6-11 and Figure 6-12 are ideal, since
charge pump mismatches are ignored and all the other noise sources are excluded,
except the VCO. As a result, the next step is to incorporate all these noise sources and
mismatches within the PLL model.
Due to the fact that both the pull up and push down currents are derived from the
same current mirror function, the amplitude of both are the same. In other words, the
mismatch only affects the propagation delay. According to the transistor level
simulation, the difference of the propagation delay between the push and pull current is
about 50ps (approximately). Therefore, within the behaviour level simulation, the pull
up current is set to 50ps propagation delay, whereas the push down current is set to
100ps propagation delay.
A novel noise aware PLL model and low-noise PLL
164
1.3
0.70
1.2
0.69
1.1
0.68
0.67
Voltage(V)
1.0
0.66
0.65
0.9
310
0.8
320
330
340
0.7
0.6
0.5
0.4
0
100
200
300
400
500
Time(ns)
Figure 6-13 Settling behavioural (vco_control) of PLL design example 1, obtained within
Simulink Model (including loop filter noise and charge pump mismatch)
The PLL‘s settling behaviour is shown in Figure 6-13, in which a periodic ripple
voltage can be clearly observed. As expected, due to the pre-defined mismatch within
the charge pump module, the period within each ripple is about 6.67ns, which is same
as the reference signal. It needs to be pointed out that the absolute amplitude of this
noise variance is misleading. Because the variance of the noise is partially determined
by the system-sampling period. Therefore, only the phase noise plot really reveals the
PLL‘s noise performance, as shown in Figure 6-14.
A novel noise aware PLL model and low-noise PLL
-60
VCO free running
PLL
-80
Loop bandwidth≈25MHz
Noise peak level ≈-127dBc/Hz
-100
Phase noise dBc/Hz
165
-106dBC/Hz
-120
-140
-160
-180
-200 5
10
6
10
7
10
8
10
9
10
Frequency(Hz)
Figure 6-14 Phase noise curve of the PLL design example 1 obtained from Simulink (including
loop filter noise and charge pump mismatch)
For these phase noise analysis, it would be very useful to make a close
comparison between the previously idea case (Figure 6-12) and the noise included case
(Figure 6-14). Two important differences should be highlighted and explained.
Firstly, when above the PLL‘s loop bandwidth (>25MHz), in Figure 6-12, the
PLL‘s phase noise curve are almost overlapping with the VCO‘s phase noise plot. In
contrast, within Figure 6-14, the PLL‘s phase noise plot is slightly higher than the
VCO‘s noise performance. This is because that charge pump noise and loop filter‘s
noise is considered within the simulation in the later case.
Secondly, two spurs can be observed in Figure 6-14. This is mainly because of
that charge pump mismatch is modelled within the simulation. Since the frequency of
reference signal is 150MHz, according to the equation (3.8), the reference spur
therefore will happen at multiples of the reference signal. In Figure 6-14, only the first
and a second reference spur are plotted, located at 150MHz and 300MHz.
Furthermore, an important result is that the PLL‘s phase noise curve is less than 120dBc/Hz, which can meet the requirement of the RF communication standards listed
A novel noise aware PLL model and low-noise PLL
166
in Table 1-1. Therefore, we may come to the following conclusion, providing that the
PLL has a sufficient wide bandwidth, the RC based VCO could be used within a
practical Local Oscillator (LO) design, if the issue of the reference spur can be solved.
It has also been pointed in out in that [70] the major issue within the wideband PLL is
the suppression of reference spur.
As has been thoroughly explained in section 3.1.4, either decreasing the charge
pump current or increasing the capacitor value within the loop filter can attenuate the
reference spur. However, either solution will decrease the PLL‘s loop bandwidth!
Therefore, the noise performance of the PLL design example 2 (4MHz loop bandwidth)
is of interest.
1.3
0.70
1.2
0.68
1.1
Voltage(V)
0.66
1.0
0.64
1.35
0.9
1.4
1.45
1.5
0.8
0.7
0
0.5
1
Time(µs)
1.5
2
Figure 6-15 Settling behaviour (vco_control) of PLL design example 2, obtained within
Simulink Model (including loop filter noise and charge pump mismatch)
As can be observed in Figure 6-15, when substituting the components‘ values
(listed in Table 6-1) into the proposed PLL models and running the simulation, the
settling time of the PLL is about 1.2µs. Compared with the transistor level simulation
results shown in Figure 6-5, the reason that the transistor level simulation has a longer
settling time (1.8µs) is mainly because that non-linearity of these transistors within the
real charge pump circuit are not modelled in the proposed charge pump models. In
other words, in practical circuit, the charge pump current is gradually increased from 0
A novel noise aware PLL model and low-noise PLL
167
to 100µA, whereas in the ideal the charge pump current is set with a constant value,
100µA.
-60
Phase noise dBc/Hz
-80
Loop bandwidth ≈ 4MHz
Noise peak level ≈ -109dBc/Hz
VCO free running
PLL
-100
-125dBC/Hz
-120
-140
-160
-180
-200 5
10
6
10
7
10
Frequency(Hz)
8
10
9
10
Figure 6-16 Phase noise curve of the PLL design example 2, obtained from Simulink (including
loop filter noise and charge pump mismatch)
The phase noise plot of the PLL design example 2 is shown in Figure 6-16. It can
be observed that reference spur‘s level is reduced to -125dBc/Hz. This is mainly due to
the reduction of the charge pump current amplitude and the increasing of the capacitor
size in loop filter, both of which contribute to the decreasing of the PLL‘s loop
bandwidth, which is about 4MHz in this example. As a result, the peak level of the
phase noise is about -109dBc/Hz as been highlighted in Figure 6-16.Obviously, this
phase noise level cannot meet the requirement of RF communication standards.
Until this stage, the trade-off between the loop bandwidth and the degree of the
noise suppression has been clearly demonstrated within above two design examples.
For the proposed PLL model, the main components (VCO, loop filter, charge pump)
are specified with transistor dimensions and passive components values, which directly
bridge the behavioural level noise model to the transistor level circuit design.
A novel noise aware PLL model and low-noise PLL
168
Therefore, the designer can investigate the final PLL‘s performance under a variety of
conditions.
The advantage of the proposed model is that this is comprehensive, including the
time domain settling verification, non-ideal effect modelling, transistor sizing decision
and the noise analysis of the PLL.
6.3 A new PLL structure
If reviewed the VCO model that is shown again in Figure6-17. It is important to
realize that when the VCO is embedded in a practical PLL design, the noise originating
from charge pump current and the loop filter shows the same behaviour as the flicker
noise in the VCO‘s control module. Especially, the charge pump mismatches, which
create the periodic voltage ripple at the VCO‘s control node. Take for example, within
previous PLL design examples 1&2, the reference frequency is 150MHz, which means
that the ripple voltage at the VCO‘s control node was a period 6.67ns. As a result, the
propagation delay (td) of all the delay cells within the VCO are varied a period of
6.67ns. Note that all the delay cells respond to this voltage fluctuation with a correlated
behavioural. Therefore, the next step is to break the correlation among all the delay
cells. The initial approach was to make a separate control for each delay cell.
1
Constant1
2*N
Gain1
In1 Out1
Pushdelay1
In1
2*N
Gain2
Out1
Pulldelay1
In1
Pushjitter
In1
2
2*N
Gain3
Out2
Divide
2*N
Gain4
Out1
Pulljitter
Transfer Fcn2
1
s
Gain
0.6*sin(2*pi*u)
Fcn1
phase
Scope4
Parasiticdelay
freq
Constant2
To Workspace2
Add2
To Workspace1
Vct
ControlVoltage
thermal
flicker
NoiseMcP
Scope2
1/gdsMcp
Constant3
mutiply
Add1
Figure6-17 Proposed Simulink model of VCO including voltage control module
Scope1
A novel noise aware PLL model and low-noise PLL
169
Specially, focusing on the PLL design example 1&2, since there are four stages
delay cell within the VCO, we therefore guess that a quadrature controls to each delay
cell could introduce some un-correlation. Realizing that the change within each control
signal only happens at the propagation delay, an all-pass filter therefore becomes the
candidate to accomplish the task. The transfer function of a typical all-pass filter is
given by equation (6.1), where a 90° phase shift happen at the corner frequency
ω=1/RC. When using the all-pass filter within this specific example, the PLL‘s
reference frequency is then become the target corner frequency as defined by equation
(6.2).
sRC  1
sRC  1
(6.1)
f ref  1 / 2 RC
(6.2)
H ( s) 
The idea was firstly tested with the proposed PLL model. As shown in Figure
6-18, the proposed VCO model was then divided into four separate sub-blocks, with
three of them accepting the output signal from the corresponding all-pass filters.
Transfer
function
of the
all-pass
Filter
Figure 6-18 Applying the all-pass filter within the proposed VCO model
It is noted that these all-pass filters contribute some extra delay within the total
PLL‘s loop. To maintain the loop bandwidth and stability, some necessary
modifications are made at the amplitude of the charge pump current and passive
component‘s value. Finally, the charge pump current was increased to 120uA and the
A novel noise aware PLL model and low-noise PLL
170
effective resistor value is increased to 6.5kΩ. After running the simulation, the phase
noise plot is then shown in Figure 6-19.
-60
VCO free running
PLL
-80
Loop bandwidth≈30MHz
Noise peak level ≈-120dBc/Hz
Phase noise dBc/Hz
-100
-137dBC/Hz
-120
-129dBC/Hz
-140
-160
-180
-200 5
10
6
10
7
10
8
10
9
10
Frequency(Hz)
Figure 6-19 Phase noise curve of PLL design example 3, obtained from Simulink (including
loop filter noise and charge pump mismatch)
The results are excellent. If compared with the phase noise plot of the PLL design
example 1 that is shown in Figure 6-12, the first reference spur has almost been
removed completely, while the peak level of the phase noise is still less than 120dBc/Hz. Therefore, the challenge is to then rerun to the transistor level design.
Based on the proposed dual inverter VCO and the model shown in Figure 6-18, the
circuit topology was obtained as shown in Figure 6-20.
VinVCO
(From Loop Filter)
Vct1
Mcn
Vin +
Mcp
R=10kΩ
C=60fF
(106fF)
R=10kΩ
Mn2
Mn1
Mp3
Mp1
Vgn
Vout -
Mp4
Mp2
Mn4
Mn3
Mp6
R=10kΩ
Mn6
Mn5
Mp5

Op_amp
(Figure A-28)

Vout+
Vgp
Vin -
Vct2
Mcn
Vin +
Mcp
R=10kΩ
C=60fF
(106fF)
R=10kΩ
Mn2
Mn1
Mp1
Mp2

Vout+
Mp6
Mn6
Mn5
Mp5
R=10kΩ
Mn4
Mn3
Vgp
Op_amp
(Figure A-28)

Vgn
Vout -
Mp3
Mp4
Vin -
Vct3
Mcn
Mn2
Mn1
Mp1
Mp2
R=10kΩ
C=60fF
(106fF)
R=10kΩ
Vin +
Mcp

Mn4
Mn3
Mp6
Mn6
Mn5
Mp5
R=10kΩ
Vout+
Vgp
Op_amp
(Figure A-28)

Vgn
Vout -
Mp3
Mp4
Vin -
Vct4
Mcn
Vin +
Mcp
Mn2
Mn1
Mp1
Mp2
Vgn
Vout -
Mp3
Mp4
Vout+
Mn4
Mn3
Vgp
Mp6
Mn6
Mn5
Mp5
Vin -
A novel noise aware PLL model and low-noise PLL
Figure 6-20 Modified VCO topology by incorporating three stage all-pass filters
171
A novel noise aware PLL model and low-noise PLL
172
It can be seen that each delay cell has its own control signal, obtained from the
corresponding all-pass filter, except the first stage delay cell. The all-pass filter,
targeting for the corner frequency (150MHz), initially, these passive components were
calculated as R=10kΩ and C=106fF, (150MHz=1/(2π*10K*106fF)) However, when
running the ac analysis, the capacitor value was reduced to 60fF. The main reason for
this difference between the calculated results and simulation results is that the polysilicon base resistors also introduce some extra effective capacitance.
The model shown in Figure 6-18 and the circuit shown in Figure 6-20 are defined
as PLL design example 3, with the transistor level simulation results are then shown in
Figure 6-21.
1.3
Vct4
1.2
0.66
Vct2
1.1
Voltage(V)
0.68
Vct3
Vct1
0.64
1.0
0.62
0.60
0.9
285
290
295
300
305
310
315
320
0.8
0.7
0.6
0.5
0.4
0
50
100
150
200
Time(ns)
250
300
350
400
Figure 6-21 Transistor level simulation results (Spectre) of PLL design example 3, with 4
control signals applied to the VCO.
If the VCO is considered as a single block, the effective control signal seen by the
VCO is then to be the mathematical average of the four control signals, which is shown
in Figure 6-22. Further observation of the control signal shows that the periodic ripple
has almost been removed and the peak-to-peak amplitude variation is 3.1mV, which is
considerably less than the ripple voltage (5.6mV) of the PLL design example 1
highlighted in Figure 6-4.
A novel noise aware PLL model and low-noise PLL
173
1.3
1.2
3.1mV
Voltage(V)
1.1
0.644
1.0
0.643
0.642
0.9
0.641
0.640
0.8
0.639
290
295
300
305
310
315
0.7
0.6
0.5
0
50
100
150
200
Time(ns)
250
300
350
400
Figure 6-22 Transistor level simulation results (Spectre) of PLL design example 3, average of 4
control signals that are applied to the VCO.
There are some excellent results both in the behavioural and transistor level.
However, the results shown from Figure 6-19 to Figure 6-22 are obtained using some
unrealistically conditions such some obvious question arise.

If a quadrature structure can remove the ripple voltage at the reference
clock‘s frequency, why don‘t we choose a differential structure? In other
word, if a replica version of the control signal with a phase shift at 180°
can be created, then the results should be the same as the proposed
quadrature structure.

If the VCO is formed with N stages delay cell, does that means the
corresponding phase delay among each delay cell is then expected to be
360°/N?

Our knowledge about PVT variation tells us that we should never expect a
filter to always work at its designed corner frequency. If the corer
frequency of these all-pass filters is changed from its designed value,
then, the function will fail to meet its design target.

Finally, even if say, the PVT variation problem could be somehow
alleviated, one of the unavoidable issue is the DC-offset of the op-amp,
A novel noise aware PLL model and low-noise PLL
174
which could be clearly observed from Figure 6-21. This means that the
propagation delay (td) of each delay cell are fundamentally different. This
in turn creates another kind of jitter among each delay cell.
To solve these issues, once again, the research returned to the behavioural models
that have been created in previous sections. Firstly, the DC-offset of the op-amp is
considered. If that PLL design example 3 can be concluded with a structure shown in
Figure 6-23, then, if these four control signals can be summed and averaged in front of
the VCO, the issue of the DC-offset could be solved. The corresponding block diagram
is shown in Figure 6-24.
Icp
AP_1
KPFD
ɸin
KF
up
data
VinVCO
PFD
ɸdclock
dclock
AP_2
ɸout
R
down
VCO
C2
AP_3
C1
Icp
ɸdclock= ɸout /N
÷N
R
R

Op_amp

R
C
Figure 6-23 Block diagram of PLL design example 3
Icp
AP_1
KPFD
ɸin
KF
up
data
PFD
ɸdclock
dclock
KVCO
VinVCO
AP_2
C2
C1
AP_3
Icp
ɸdclock= ɸout /N
VCO
ɸout
R
down
1/4
÷N
Figure 6-24 Block diagram of the proposed novel PLL
A novel noise aware PLL model and low-noise PLL
175
Further analysis of the block diagram shown in Figure 6-24, it is found that any
stages of RC VCOs and any structure of the VCO (even LC based VCO) could benefit
from this structure. In other words, as long as the PVT variation issues of these all pass
filters can be solved, then, a reference spur free PLL could be expected.
To solve the problem of PVT variation, another complex calibration circuit may
need to be created. However, some simple solution may be effective. In practical
circuits, it is surely unable to expect that the corner frequencies of an all-pass filter are
always exactly same as the reference signal frequency, but it is practical to expect the
corner frequency of an all-pass filter is locating within certain range. Therefore, for the
three stages all-pass filters, the nominal corner frequency of each stage could be
designed with a gap. As a result, the corner frequency of each all-pass filter is located
within a certain range, but these ranges are overlapped.
Therefore, as shown in Figure 6-25, using the dual inverter delay cell as an
example, the operation of the sum and average of these four control signals are realized
by summing four current signals, each of which is controlled by an all-pass filter. It
would be important to note that the nominal corner frequencies of each all-pass filter
are purposely made with some differences, which is corresponding to 142MHz,
149MHz, and 157MHz, all around the target frequency−150MHz. The corresponding
PLL, denoted it as PLL design example 4, is shown in Figure 6-26.
VinVCO
(From Loop Filter)
Vct1
Vct1
Mcn
Vctp1
Mcp
variation is considered
R=10kΩ
Mcn
C=55fF
(106fF)
R=10kΩ
Vct2
Vctp2
Mcp
Vct3
R=10kΩ
Vct4

Op_amp
(Figure A-28)

Mcn
Vctp3
Mcp
Mcn
Vctp4
Mcp
Vct1
Vctp1
Vctp3
C=61fF
(106fF)
R=10kΩ
Mn2_4
Vn
Vp
Mp2_4
Vin +
Vct4
Mn2_3
Mp2_3
Vctp4
R=10kΩ
Vct3
Mn2_2
Mp2_2
Vct2
Vct2
Mn2_1
Mp2_1
Vctp2

Mn6
Vct4
Mn4_3
Mn4
Mn5
Mp5
Mp6
Vctp4
Mp4_3
Mn3
Vct3
Mn4_2
R=10kΩ
Vct2
Mn4_1
Vn
Vgn
Vout+
Vgp
Vp
Vctp3
Mp4_2
Vout -
Mp3
Mp4
Mp4_1
Vctp2
Op_amp
(Figure A-28)

Vct1
Mn2
Mn1
Mp1
Mp2
Vctp1
Mn4_4
Vn
Vp
Mp4_4
Vct1
Vin -
Vctp1
Vct3
Vct2
Mn6_1
Mp6_1
Vctp2
Vct4
Mn6_3
Mp6_3
Vctp4
C=65fF
(106fF)
R=10kΩ
R=10kΩ
Vct3
Mn6_2
Mp6_2
Vctp3
Mn6_4


R=10kΩ
Op_amp
(Figure A-28)
Mp6_4
Vct4
A novel noise aware PLL model and low-noise PLL
176
Figure 6-25 Improved VCO topology by incorporating three stage all-pass filters, the PVT
A novel noise aware PLL model and low-noise PLL
1
177
1
In1
Saturation1
-1*[1 -2*pi*142e6]
s+2*pi*142e6
Transfer Fcn
Out1
2
Saturation
Out2
-1*[1 -2*pi*149e6]
s+2*pi*149e6
Transfer Fcn1
3
Saturation2
-1*[1 -2*pi*157e6]
s+2*pi*157e6
Transfer Fcn2
Out3
4
Saturation3
Out4
Reference
Clock
In1
Out1
In2
Out2
In1
In2
Out1
Out2
In1
Out3
Out4
2
(6e-12*0.3e-12*6.5e3)s +(6e-12+0.3e-12)s
Charge_pump
PFD
Loop Filter Transfer Fcn1
All-pass Filter bank
thermal
flicker
Noise of
LoopFilter
Out1
In1
Out1
In1
Frequency_divider3
To Workspace1
Out1
1/4
Scope3
In1
1/4
Out2
Saturation
VCO
vct_control
RLF
Constant3
To Workspace3
Divide
Out1
1
s
(1/6.67e-9)*16
Reference Frequency
Frequency_divider4
Constant2
Scope2
(6.5e3*6e-12)s+1
Out1
totalphase
0.6
VDD
Constant1
Scope1
Scope8
In1
Frequency_divider2
Out1
In1
Compare
To Zero
Transfer Fcn2
phaseoffset
To Workspace2
<= 0
Frequency_divider1
Scope5
Figure 6-26 Comprehensive PLL model of the proposed novel PLL
After running the simulation, the phase noise plot obtained from the proposed
PLL model is shown in Figure 6-27. Compared with the phase noise plot of PLL design
example 3 (ideal case) shown in Figure 6-19, the only difference is that the peak level
of the phase noise plot is slightly worse than the ideal. Since the result obtained from
more practical system settings, it was therefore believed that the proposed PLL
structure shown in Figure 6-24 is extremely effective for reference spur reduction.
Especially, when the wideband become the essential requirement of certain PLL, this
novel structure could become an alternative solution, removing the trade-off between
the loop bandwidth and the suppression of the reference spur.
A novel noise aware PLL model and low-noise PLL
-60
178
VCO free running
PLL
-80
Loop bandwidth≈30MHz
Noise peak level ≈-119dBc/Hz
-140dBC/Hz
Phase noise dBc/Hz
-100
-120dBC/Hz
-120
-140
-160
-180
-200 5
10
6
10
7
10
8
10
9
10
Frequency(Hz)
Figure 6-27 Phase noise curve of PLL design example 4, obtained from Simulink (including
loop filter noise and charge pump mismatch)
Furthermore, based on the proposed PLL model, the spectrum of the PLL‘s
output signal can be analysed as well. As shown in Figure 6-28, the spectrums of the
PLL‘s output signal, which are obtained from PLL design example 1 and PLL design
example 4, are compared. The improvement at the reference spur is clear.
A novel noise aware PLL model and low-noise PLL
179
-60
PLL design example 1
Power(dB)
-80
-100
-120
-140
2
2.2
2.4
2.6
2.8
Frequency(GHz)
-60
PLL design example 4
Power(dB)
-80
-100
-120
-140
2
2.2
2.4
2.6
2.8
Frequency(GHz)
Figure 6-28 Spectrum of the PLL‘s output signal, obtained from Simulink model (PLL design
example 1 and 4)
Until this stage, the key issues that arose from the PLL design example 3 have
been solved with three, except the first issue, ―why don‘t we use the differential
structure to cancel the ripple voltage at the VCO‘s control node?‖ To explain this issue,
it would be useful to write down the system open loop transfer function of the novel
PLL structure that is shown in Figure 6-24. The open loop transfer function of the
proposed novel PLL structure can be expressed with equation (6.3)
H ( s )open 
( s 1  1)  KVCO  I CP  (1  AP1  AP1  AP2  AP1  AP2  AP3 ) / 4
s 2 ( s 2  1)  (C1  C2 ) N
 1  R1C1; 2   1  C2 / (C1  C2 )
AP1  AP2  AP3 
(6.3)
sRapCap  1
sRapCap  1
For the PLL design example 3, where the corner frequencies of all the all-pass
filters are same as the reference signal frequency, the bode plot of open loop transfer
function is shown in Figure 6-29. It can be found that all the frequency components
locate at 150MHz are thoroughly removed. It will be important to point out that only in
A novel noise aware PLL model and low-noise PLL
180
this ideal condition, that differential structure can effectively remove the reference
signal induced ripple. In other words, the replica version of the original signal is
exactly shifted by 180°. Otherwise, the cancellation cannot work.
.
100
Magnitude (dB)
50
0
-50
-100
-150
-200
-90
Phase (deg)
-135
-180
-225
-270
-315
5
10
6
10
7
8
10
10
9
10
10
10
Frequency (Hz)
AP1=AP2=AP3
Figure 6-29 Bode plot of open loop transfer function of PLL design example 3
By setting a gap between the corner frequencies of each all-pass filter, the
cancellation to the reference spur still can be achieved. The bode plot of the practical
situation is then shown in Figure 6-30. It can be observed that attenuation at 150MHz is
about -50dB, which is sufficient in most practical applications. For the traditional
charge pump PLL structure, to achieve the same degree of attenuation, the only
solution is to decrease the loop bandwidth, which has been proved with PLL design
example 2, with its open loop transfer function shown in Figure 6-3. In other word,
these three stages all-pass filters create a notch filter, which could be fit for certain
frequency ranges, but not only effective with one specific frequency. We thus may able
to claim that the special features and advantages of the proposed new PLL structure has
been demonstrated with the bode plot of the transfer function (equation(6.3)).
A novel noise aware PLL model and low-noise PLL
181
100
Magnitude (dB)
50
Frequency (Hz): 1.48e+008
Magnitude (dB): -52.3
0
-50
-100
-150
360
Phase (deg)
180
0
-180
-360
5
6
10
10
7
10
8
10
9
10
10
10
Frequency (Hz)
Cutoff frequency of AP1 =142MHz AP2=149MHz and AP3=157MHz
Figure 6-30 Bode plot of open loop transfer function of PLL design example 4
6.4 Advanced verification of the proposed new PLL structure.
To demonstrate the special features of the proposed novel PLL structure, PLL
design example 5 and PLL design example 6 were created with approximately the same
loop bandwidth. The PLL design example 5 was designed using a traditional charge
pump PLL structure, which is shown in Figure 6-1. In contrast, the PLL design
example 6 was designed using the novel PLL structure shown in Figure 6-24, in which
the corner frequency of the all-pass filters were purposely defined to be PVT tolerant as
shown in Figure 6-25.
When designing these two PLL examples, the VCO design example 3 illustrated
in Chapter 5 are used. Due to the requirement for the quadrature controls to each delay
cell of the VCO, some modifications are made at the circuit topology and layout. The
new layout of the VCO design example 3 is shown in Figure 6-31. It can be seen the
four control signals are generated with four separate VCO control module, which is at
left end of the layout.
A novel noise aware PLL model and low-noise PLL
182
VCO control module
Figure 6-31 Layout of VCO design example 3, modified with quadrature control to each delay
cell
Consequently, the PLL design example 5 and 6 are created, with their design
specifications and features listed in Table 6-2. Besides the basic specifications, the
power consumption of each design example is recorded from the simulation. It is found
that the proposed novel PLL require additional 2.64mW power consumption, which is
mainly due to the adoption of the three stages all pass filter.
Table 6-2 Specifications of PLL design example 5 & 6
Dimensions
PLL design example 5
PLL design example 6
Structure
Traditional
Proposed novel PLL
loop bandwidth
≈30MHz
≈30MHz
Charge pump current (Icp)
120µA
120µA
R(effective)
5KΩ
6.5KΩ
C1
6pf
6pf
C2
0.3pf
0.3pf
150MHz
150MHz
Divider ratio(N)
16
16
Gain of VCO(KVCO)
5GHz/V
5GHz/V
Power consumption of VCO
15.36mW
15.6mW
Power consumption of PLL
16.92mW
19.56mW
Reference signal
frequency(Fref)
A novel noise aware PLL model and low-noise PLL
183
The post layout simulation results of the PLL design example 5 are shown in
Figure 6-32. The periodic ripple voltage at the control node can be clearly observed,
with the amplitude of the ripple voltage at 6.2mV.
1.3
1.2
0.66
6.2mV
1.1
0.656
0.654
1.0
Voltage(V)
0.658
0.652
375
380
385
390
395
400
0.9
0.8
0.7
0.6
0.5
0
100
200
300
400
500
Time(ns)
Figure 6-32 Post layout simulation results (Spectre) of PLL design example 5
1.3
0.68
1.2
0.67
Vct4
0.66
Vct3
1.1
0.65
Vct2
0.64
Vct1
Voltage(V)
1
0.63
420
430
440
0.9
0.8
0.7
0.6
0.5
0.4
0
50
100
150
200
250
300
Time(ns)
350
400
450
500
Figure 6-33 Post layout simulation results (Spectre) of PLL design example 6, with four control
signals applied to the VCO
A novel noise aware PLL model and low-noise PLL
184
Voltage(V)
1.3
1.2
0.658
1.1
0.656
2.6mV
1.0
0.654
0.9
0.652
445
0.8
450
455
460
0.7
0.6
0.5
0.4
0
50
100
150
200
250
300
Time(ns)
350
400
450
500
Figure 6-34 Post layout simulation results (Spectre) of PLL design example 6, average of four
control signals that are applied to the VCO.
In contrast, by using the proposed novel PLL structure, the post layout simulation
results of PLL design example 6 shows a significant improvement of the ripple
voltage‘s amplitude. These four control signals are shown in Figure 6-33, from which a
DC-offset can still be observed. However, since each delay cell indeed sees these fourcontrol signals as a combinational signal, we believe this DC-offset has no influence to
the noise performance of the VCO. The equivalent signal seen by each delay cell is
then plot in Figure 6-34. It is found that the amplitude of ripple voltage is 2.6mV, which
is much less than the traditional PLL‘s results (6.2mV) shown in Figure 6-32.
It must be pointed out that within the post layout verification results, the stability
of the loop is slightly reduced when compared with a traditional PLL structure. There
are two reasons lead to this performance drop.
First, at system level, when incorporating these all-pass filters within the design,
the phase margin of the system does decrease by 10-20 degrees. This could be observed
from bode plots of the system transfer function (Figure 6-30).
Second, the parasitic effects vary the value of the passive components, especially
the PMOS based effective resistor (R) are slightly higher than the nominal value, which
in turn slightly decreases the phase margin.
A novel noise aware PLL model and low-noise PLL
185
Furthermore, as a compensation for the previous experimental work, an AC
coupling based output buffer circuit[70] is created with its circuit diagram shown in
Figure 6-35 and the layout shown in Figure 6-36. Compared with the output buffer
circuit realized in Chapter 5, the most important change is that within this output
buffer, a resistor (20kΩ) is used to biasing the trigger point of each inverter at VDD/2,
thus the problem of ―duty-cycle distortion‖ is significant alleviated.
2.7  m
0.13 m
4.05 m
0.13 m
12.15 m
0.13 m
36.45 m
0.13 m
109.35 m
0.13 m
Clk_out
Clk_in
150 fF
3pF
1.35 m
0.13 m
0.9  m
0.13 m
4.05 m
0.13 m
12.15 m
0.13 m
50
36.45 m
0.13 m
20K
Figure 6-35 Schematic of the optimized output buffer
Figure 6-36 Layout of the optimized output buffer
When running the post-layout simulation (extraction with RCc mode), the output
load is set with 3pF capacitor in parallel with 50Ω resistor, which is should be
sufficient for practical measurement. When applying a 4GHz square wave at the input
node, as shown in Figure 6-37, the amplitude of the output waveform is still higher than
0.6V, which is robust enough for noise and jitter analysis.
A novel noise aware PLL model and low-noise PLL
1.2
Clk_in
1.0
Voltage(V)
186
0.8
0.6
0.4
0.2
0
30
30.5
31
31.5
32
32.5
33
33.5
34
Time(ns)
Voltage(V)
0.8
Clk_out
0.6
0.4
0.2
0
30
30.5
31
31.5
32
Time(ns)
32.5
33
33.5
34
Figure 6-37 Post layout simulation results of the improved output buffer
6.5 Summary
This chapter has highlighted two main contributions. Firstly, a comprehensive
time domain PLL model has been introduced, which correctly model the time domain
PLL‘s settling behaviour, the non-ideal effects within the charge pump and loop filter,
and the noise behaviour of the RC based VCO.
Second, using the proposed PLL model, a novel PLL structure has been proposed
and verified at behavioural level, schematic level and post layout level. The proposed
PLL structure is a universal structure, which could be applied to any VCO structure.
The most obvious advantage of this new structure is the reference spur suppression, and
this feature is particularly beneficial for wide bandwidth PLLs.
Conclusions and further work
187
Chapter 7 Conclusions and
further work
7.1 Conclusions
This thesis has developed a number of important areas within analogue integrated
circuit design. In particular, there are a number of theoretical, modelling and practical
design innovations that have been made as a result. A new theoretical noise model for
VCOs have been developed, and then testing with practical designs. In addition, the
thorough testing of these ideas has been completed with two chip fabrications, leading
to credible measured results, which validate the proposed design techniques. Finally, an
integrated modelling approach was introduced and developed to the extent that a
complete PLL can be designed and the noise performance predicted. These
contributions are listed below in more detail.
1. A schematic level improvement was made on the topology of an existing
VCO delay cell. The wider tuning range, which is the advantage of the
proposed new VCO topology, was demonstrated through simulation and
measured results.
2. A novel time domain noise model has been created for the proposed VCO
topology and further verified with measurement results of a practical
circuit design. The features of the proposed VCO noise model include its
comprehensive modelling of a variety of design parameters, including
voltage frequency tuning, phase noise performance, tuning range and
transistor sizing decisions.
Conclusions and further work
188
3. A comprehensive PLL model is investigated by incorporating the
proposed VCO model. It has demonstrated that this proposed PLL model
can effectively model the trade-off between noise performance and the
selection of PLL loop bandwidth, giving the choice of transistor
dimensions.
4. A novel PLL structure is proposed, that of use the proposed PLL model
within a practical PLL design. The proposed PLL structure is further
improved for its use within practical circuit design. Final simulation
results prove that this novel PLL structure is extraordinary effective for
reference spur suppression.
7.2 Future work
There are several areas of potential further research work to be undertaken behind
this work in the future. Briefly, the research could be based on the following three
levels:
Firstly, within the modelling level: the advantage of introducing three all-pass
filters to eliminate reference spurs has been thoroughly explained. However, the allpass filter, which is formed with an op-amp, must also contribute some noise to the
control node of the VCO. The good news is that all these noise sources among each opamp are un-correlated, and when these noise sources are translated to the VCO noise,
each of them will only effective 25% of the VCO gain. However, this does require
further verification by including the op-amp output noise within the model.
Secondly, within the prospect of circuit design: the realization of these all-pass
filters could be improved with a more practical approach. One of the obvious
limitations of the proposed PLL structure is that it can only to be effective at one
reference frequency. If the design can be correctly operated with multiple reference
frequencies, then the usability of the proposed structure can be enhanced. For general
consideration, we believe the circuit shown in Figure 7-1 could be a possible solution to
tune the corner frequency of the all-pass filter. However, when considering the PVT
variation, precise control of the corner frequency of these all-pass filters may require
another PVT calibration loop to be created.
Conclusions and further work
189

Op_amp



Op_amp
Op_amp


Digital Control
C1
Cn
Figure 7-1 Corner frequency tuning of the all-pass filter
Thirdly, for the improvement of measurement approach: The noise problem
with the RF probe pads based testing platform has been highlighted within this thesis. It
is hoped to make some further deeper analysis regarding RF testing as a potential future
research work.
Finally, based on the proposed novel PLL structure, a frequency synthesizer,
which can meet with the requirement of industrial RF communication standards, is
envisaged. Especially, this wideband PLL could be incoporated within a practical
transceiver design to remove the reference spur within the PLL. The advantages and
benefits ofthis approach could be further investigated and compared to the state of the
art designs.
Conclusions and further work
190
Appendix A
Fundamental building blocks
191
Appendix A Fundamental building
blocks
In this appendix, some of the fundamental circuit blocks and design techniques
relating to analogue IC design relevant to this thesis are introduced. Although all the
circuit diagrams used in this chapter are already discussed in the literature [4][10][30],
for each block there still exists huge amounts of discussion regarding performance
enhancement approaches and design methodologies. For this reason, efficient
realization of these blocks on a modern DSM process still challenges the skills of the
designer. The majority of blocks discussed below are part of the functionality within
the final PLL design, which means a certain degree of trade-off among the power
consumption, chip area, performance and robustness needs to be carefully considered.
A.1 DC signal generation
The transistor is the smallest design unit within the analogue IC design procedure
and the operation regions of each transistor can be summarised using the standard
equations shown in (8.1) and (8.2).
Triode : I D  nCox
for VGS
Saturation : I D 
2


VDS
(
V

V
)
V

tn
DS
 GS

2 

 Vtn and VDS  VGS  Vtn
W
L
(8.1)
nCox W
(VGS  Vtn )2 1   (VDS  VDS , sat ) 
2 L
for VGS  Vtn and VDS  VDS , sat  VGS  Vtn
(8.2)
Appendix A
Fundamental building blocks
192
For many years, equations (8.1) and (8.2)[4][10] have been utilized for
identifying the operating region and hence calculating the drain current of the
transistor, where μn is the surface mobility parameter for NMOS transistor, λ is the
channel length modulation parameter and Cox is the unit-area gate oxide capacitance,
which is calculated by the relation:
Cox   ox / tox
(8.3)
where εox is the dielectric constant (3.45×10-11) of SiO2 and tox is gate oxide thickness.
For most recent DSM process and advanced transistor models [32] (e.g., BSIM4,
EKV), specific calculation equations and coefficient definitions may be different, but
two basic principles can be considered as rules of thumb:

All transistor must be treated with the pre-knowledge of its DC biasing
condition.

If the channel length effect can be neglected, from equation(8.2), it may
be concluded that when a transistor is working in the saturation region, a
constant gate-source voltage (VGS) biasing generates constant drain
current (ID), and vice versa.
To observe these rules more clearly, consider the example circuit shown in Figure
A-1, where we set bias voltage for gate(VGS) to be constant, and observe the drain
current(ID) by sweeping drain node voltage(VDS).
D
G
S
ID
0.15 m
0.13 m
VGS
VDS
GND
VGS-Vtn
120
VGS=1.2V
Drain node Current ID (μA)
100
80
VGS=1.0V
triode
60
VGS=0.8V
40
saturation
VGS=0.6V
20
VGS=0.4V
0
0
0.2
0.4
0.6
0.8
Drain node voltage VDS(V)
1
1.2
Figure A-1 Current-voltage characteristics for st12 NMOS (W/L=150nm/130nm)
Appendix A
Fundamental building blocks
193
It can be observed that when transistor is operating in the triode region, the drain
current is more dependent on the variation of drain node voltage (VDS), whereas the
gate source voltage (VGS) is the dominant factor when the transistor is operating in the
saturation region. Therefore, it may be concluded that when two identical transistors
are working in the saturation region, provided that they have same gate-source bias
voltage, their drain current should be almost the same. This is the fundamental concept
of the basic analogue circuit module - the current mirror.
A.1.1 Current mirror
As shown in Figure A-2, transistor M1 is diode connected which means it must
work in the saturation region as long as the reference current Iref is strong enough to
drive the gate voltage of M1 higher than the threshold voltage (Vtn). Therefore,
provided that the output voltage Vo is higher than VGS1-Vtn, from equation (8.2), the
drain currents of M2, M3, M4 can be obtained by following equations:
I D,M 2  I ref 
I D,M 3  2 I ref 
I D, M 4  4 I ref 
nCox W
2
L
(VGS1  Vtn )2 1   (VDS  VDS ,sat ) 
nCox 2W
2
L
nCox 4W
2
L
(8.4)
(VGS1  Vtn )2 1   (VDS  VDS ,sat ) 
(8.5)
(VGS1  Vtn )2 1   (VDS  VDS , sat ) 
(8.6)
VDD

R1
Iref
Iref
M1
VGS1
W
L
2Iref
4Iref
M3
M2
W
L
M4
4W
L
2W
L

GND

Iref
Vo


2Iref
Vo

Figure A-2 Conceptual model of current mirror
Vo

4Iref
Vo

Appendix A
Fundamental building blocks
194
Theoretically, from equations (8.4)-(8.6), transistors M2-M4 can be considered as
three separate current sinks, each of which can constantly sink multiples of the
reference current. Additionally, these equations indicate the general principle that any
amount of constant current sink can be obtained by adjusting the dimensions of the
transistor if the amplitude of reference current (Iref) or reference voltage (VGS1) is
known in advance.
However, real circuit performance may differ significantly from these theoretical
conclusions. Firstly, variability of transistor dimensions, threshold voltage (Vtn) and
surface mobility (μn) make these theoretical models less accurate. Secondly, the
generation mechanisms of the reference current (Iref) or reference voltage in Figure A-2
are highly dependent on the supply voltage (VDD), which means that small amounts of
variation of supply voltage (VDD) will significantly vary the amplitude of reference
current and reference voltage. Thirdly, as mentioned in section 1.2.1, channel length
modulation effects (λ) cannot be ignored if a higher operational gain is required. To
solve these last two problems, the beta-multiplier circuit and cascode current mirror
structure have been developed
A.1.2 Biasing circuit and cascode current mirror
Beta-multiplier
Firstly, consider the reference current (Iref) generation mechanism (surrounded by
dashed line) shown in Figure A-2. Supposing that the channel length modulation effect
can be ignored, from equation(8.2), it is not difficult to derive following relation:
I ref 
nCox W
2
L
(VGS1  Vtn )2 
nCox W
2
L
((VDD  I ref R1 )  Vtn )2
(8.7)
Reorganizing this equation, we can find that Iref is completely proportional to the
supply voltage VDD, as illustrated by equation (8.8)
2 I ref L
nCoxW
 I ref R1  VDD  Vtn
(8.8)
Therefore, to break this dependence, the beta-multiplier circuit is introduced as
shown in Figure A-3 (a). In this function, two identical transistors M3 and M4 give
equal amounts of reference current in each rail. Provided that the width of transistor M2
is purposely sized to be K times of M1‘s, we can conclude that VGS1 must be higher
than VGS2and following relations are obtained:
Appendix A
VDD
Fundamental building blocks
195
VGS1  VGS 2  I ref R2
(8.9)
M4
M3
Iref
MA3
VGS3
M3
MS2
Iref
VDD
VDD
VDD
VDD
VDD
MA4
VDD
C1
M4
Vbiasp
MS3
Vbiasn
MS1
M1
W
L
M1
M2
VGS1
R2
GND
M2
VGS1
KW
L
VGS2
C2
Iref
Iref
MA1
GND
GND
GND
GND
(a)
R2
MA2
GND
GND
(b)
Figure A-3 Beta-multiplier for constant biasing generation
From equation(8.2), we can write:
VGS1 
VGS 2 
2 I ref L
nCoxW
2 I ref L
nCox KW
 Vtn
(8.10)
 Vtn
(8.11)
Substitute equation (8.10) and (8.11) into(8.9), and reorganizing to solve for Iref:
I ref
2L
 2
R2  n CoxW
1 

1 

K

2
(8.12)
It is important to realize that in this new approach, Iref is a function that no longer
depends on VDD. Furthermore, to address the finite output resistance of all MOSEFTs,
as shown in Figure A-3 (b), a differential amplifier (MA1-MA4) is embedded within
the beta-multiplier to increase the output resistance.
Note that a ―start up function‖ is included so that we can ensure VGS1 (gate
voltage of M1 and MS1) always higher than the threshold voltage (Vtn), and hence
make sure that total circuit functions correctly. Otherwise, if VGS1 is lower than the
nominal threshold voltage, transistor MS1 is off and leads to an increase of the gate
voltage of MS3, which means that a higher amount of leakage current flows from the
VGS3 to VGS1 and in turn keeps transistor M1 and MS1 away from the ―off‖ state.
When these functions were realized with the st12 process, a reference current Iref
was set at the level of 10μA (approximately) and the transistor length purposely set
at1µm, which is better for minimizing device mismatch. Two reference voltages
Appendix A
Fundamental building blocks
196
Vbiasn(VGS1) and Vbiasp(VGS3) are defined at approximately 380mV and 820mV, which is
about 5% of VDD plus the threshold voltage of NMOS and PMOS, respectively. Based
on the process parameters listed in Table 1-3, all transistor dimensions can be
calculated initially. Further refined with simulation, the final component values and
transistor dimensions are given in Table A-1 and simulation results are given in Figure
A-4.
Table A-1 Component values and transistor dimensions for Beta-multiplier in Figure A-3
Component
Dimensions
Component
Dimensions
R1
82K Ohms
MA1, MA2 (W/L)
1.45μm/1.00μm
R2
10.4K Ohms
MA3, MA4 (W/L)
5.60μm/1.00μm
M1(W/L)
1.45μm/1.00μm
MS1, MS3 (W/L)
0.40μm/0.50μm
M3, M4 (W/L)
5.15μm/1.00μm
MS2 (W/L)
0.50μm/4.00μm
M2 (W/L)
5.80μm/1.00μm
C1, C2
4.00μm/1.00μm
15
Reference current Iref (μA)
Slope < 0.127μA/V
10
Slope ≈ 10.6μA/V
5
Basic approach in Figure 2-2
0
Beta-multiplier in Figure 2-3 (b)
0
0.5
1
1.5
Supply voltage VDD (V)
Figure A-4 Dependence of reference current (Iref) on supply voltage (VDD).
A simulation was performed with the supply voltage (VDD) swept from 0V to
1.5V (+25%). As expected, the reference current (Iref) in the beta-multiplier was kept
almost constant during the majority of the sweep range (VDD>0.6V), whereas a huge
amount of variation is observed in the basic approach (Figure A-2).
It must be pointed out that, when the above schematic level design is
implemented in practice, the quality of layout becomes one of the dominant factors that
influences the performance of the final IC. There are numerous techniques to
implement high performance IC layout for analogue applications. In this section, using
the beta-multiplier function proposed in Figure A-3 (b) as an example, three
fundamental analogue layout techniques are introduced: common centroid[10], guard
rings [58] and dummy transistors.
Appendix A
Fundamental building blocks
197
The common centroid technique is often utilized to cancel the effect of linear
process parameter gradients. Rather than laying out a device with a large ratio of W/L
side by side, it is preferable to divide this device into many identical ‗finger‘ devices,
connected in parallel and symmetrically lay out these transistors across a central axis.
Consider the transistors M1 and M2,which have the dimensions of 1.45µm/1.00µm and
5.8µm/1.00µm, respectively. Therefore, we choose 0.725µm/1.00µm as a common
factor that divides M1 to 2 fingers and M2 to 8 fingers as shown in Figure A-5.
VDD
N-well
Dummy cell
Poly
N-type guard ring
P-active
MS2
MA3
C1
M3
MA4
M4
R2
MA2
MA1
C2
Common centroid
M1
M2
Figure A-5 Layout of beta-multiplier
Actually, it can be observed that two current mirrors (M3-M4/MA3-MA4), which
are the core part of the beta multiplier, are all purposely placed with the symmetry to
the transistor M1, with the aim of process parameter gradient cancellation. In addition,
Appendix A
Fundamental building blocks
198
as highlighted with transistors MA3/MA4, two dummy transistors are added at the ends
of each stack to ensure that the unit stacks of matched stacks see the same adjacent
structure, and guard rings are created to provide effective isolation from other devices
on the chip[58].
Cascode current mirror
As illustrated in Figure A-1, the channel length modulation effect can
significantly degrade the performance of the current source/sink. To solve this problem,
a cascode current mirror structure can be adopted when a higher operational gain is
required. As shown in Figure A-6, provided that we have a constant stable reference
voltage (Vbiasn) and transistor M1 has the same dimension as in beta-multiplier, the
output current has a normal amplitude 10μA. However, instead of being constant, the
output current increases as output voltage increases. The small signal model can further
explain this phenomenon, where the ratio of output voltage to output current is termed
as output resistance Ro. For the single transistor, it is not difficult to find that output
resistance is:
Ro  vo / io  ro
(8.13)

Vo
Iref

io
Iref
Iref
Vbiasn
Vbiasn

Vo
M1

g m vgs1
io

ro
vo

M3
g m vgs 3
Vo
Vbias4

M2

g m vgs 2
ro

vgs 3
vo
ro

GND
GND
(a)
(b)
1
1
Slope  
ro 1280 K 
1
1
Slope 

g m ro2 15200 K 
12
Current amplitude (μA)
10
8
6
Single
Cascode
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
Output voltage (V)
Figure A-6 How the finite output resistance of the MOSEFT affects the output current
Appendix A
Fundamental building blocks
199
In order to increase the output resistance, the simplest way is to cascode another
transistor as shown in Figure A-6 (b). Two constant biasing voltages (Vbiasn and Vbias4)
are set at 380mV and 250mV respectively, and transistor M2 and M3 are sized at
7.10μm/1.0μm which can sink 10μA current. From the small signal model of the
cascode structure, it can be written that:
vgs 3  io vo
(8.14)
io  gmvgs 3  (vo  (vgs 3 )) / ro
(8.15)
The current through M3 is then:
Substituting equation (8.14) into (8.15) and solving for vo/io:
vo / io  Ro  (2  gm ro )ro  gm ro2
(8.16)
The improvement introduced by the cascode structure can be observed in Figure
A-6, as expected, the slope of drain current decreases by a factor of 12
(15200K/1280K). If a higher output resistance is required, a differential amplifier can
be incorporated to regulate the drain node of transistor M2 (illustrated in section 2.2.3).
VDD
VDD
Vbiasp
Beta-multiplier in
Figure2-3(b)
5.15 m
1.00 m
Iref1
Iref8
7.10 m
1.00 m
7.10 m
1.00 m
7.10 m
1.00 m
7.10 m
1.00 m
Vbiasn
GND
6.50 m
1.00 m
GND
GND
29µm
GND
120µm
Figure A-7 Biasing and reference current generation circuit
Appendix A
Fundamental building blocks
200
Finally, as shown in Figure A-7, 8 copies of the current sink illustrated in Figure
A-6 (b) are created, which are utilized for the reference and biasing for other functions
(e.g, op-amp) within the final PLL design.
A.1.2 Bandgap reference (BGR)
It seems that a beta-multiplier can successfully break the dependence of biasing
voltage on supply voltage variation; however, a good (ideal) voltage/current reference
should be independent of the temperature and process variation as well. In this section,
we introduce the practical realization of temperature independent voltage/current
reference function - the bandgap reference.
16
Reference current (μA)
Reference voltage(mV)
440
420
380mV@27˚C
400
380
≈0.48mV/˚C
360
340
-40
0
40
80
120
14
10μA@27˚C
12
10
≈0.0477μA/˚C
8
6
-40
Temperature (˚C)
(a)
0
40
80
120
Temperature (˚C)
(b)
Figure A-8 Temperature behaviour of bias voltage Vbiasn and drain current of M1
Referring back to the biasing voltage generation circuit shown in Figure A-3,
consider the reference voltage Vbiasn, which is purposely designed at 380mV. In this
instance, what we are interested in is its temperature behaviour. As shown in Figure
A-8(a), the above biasing circuit is simulated with the environmental temperature
sweeping from -40℃ to 120℃. It is can be seen that the reference voltage Vbiasn
increases proportional with temperature at a rate of0.48mV/°C, which is defined as the
Temperate Coefficient (TC) with a value of480ppm/℃.
In addition, as shown in Figure A-8 (b), the temperature behaviour of the
reference current (drain current of transistor M1 in Figure A-3) is analyzed as well. It
can be seen that the reference current increases proportionally with temperature at a
rate of 0.0477μA/℃. If we define these kinds of behaviour as Proportional-ToAbsolute-Temperature (PTAT), to compensate this increment, a Complementary-ToAbsolute-Temperature (CTAT) mechanism is required. Normally, a bipolar transistor
Appendix A
Fundamental building blocks
201
creates a CTAT voltage reference. However, since the design kits of st12 do not
provide the models of bipolar transistors, the bipolar model must be built artificially, to
form a diode.
P
N
P
P+
N+
P+
N+
P+
N-well
7.4 μm
6 μm
P-plus
4 μm
N-well
N-plus
4 μm
P-plus
Figure A-9 Layout of pseudo PNP bipolar transistor
As shown in Figure A-9, this diode is formed by a P+ implant that is embedded in
an N-well. The dimension of P+ implant defines the area of the diode, which is 4µm ×
4μm in this example. When this diode is embedded into a BGR circuit, current is
injected through the P+ implant to the N-well and to the P-substrate. In order to prevent
this injected current flowing to other functions built on the same substrate, a P-type
based guard ring is placed surrounding the N-well. It should be noted that the P+
implant, N-well and P-type guard rings create a pseudo PNP bipolar transistor, while
the P-type guard ring and N-well are tied to the ground.
Appendix A
Fundamental building blocks
202
Therefore, before utilizing this diode into a BGR design, the correct
characterization of its voltage, current and temperature relations is important. Consider
the circuit shown in Figure A-10, where a constant 1µA current is injected into the
forward based diode. By sweeping the simulation environmental temperature, the diode
voltage (VD) variation can be seen.
676
25˚C
Diode Voltage VD (mV)
1μA
VD
Area=16m-12
-6
Perimeter=16m
D1
Layout in Figure 2-9
674
26˚C
672
27˚C
670
28˚C
668
29˚C
1.2
1.0
1.4
1.6
time (μs)
1.8
2.0
850
Diode voltage VD (mV)
800
750
≈ -1.77mV/˚C
700
650
600
550
-50
-25
0
25
Temperature ˚C
50
75
Figure A-10 Voltage, current and temperature characteristics of the diode shown in Figure A-9
According to [10], current through a forward-biased diode is given by
I D  I S  eVD / nVT  I S  eVD q / nkT
(8.17)
where Is is diode‘s scale current at the order of 1×10-18, n is the process fitting
parameter, VT is thermal voltage given by kT/q, k is Boltzmann constant (1.3809 × 1023
), T is temperature in Kelvin, q is electron charge (1.6022 ×10-19) in Coulombs. From
simulation results shown in Figure A-10, the fitting parameter n for the diode is
adjusted to 0.938 and it can be observed a CTAT voltage behaviour with the
temperature coefficient is about -1770ppm/℃. These two parameters are utilized for the
BGR design in the next step.
Appendix A
Fundamental building blocks
203
First, following the principle introduced in beta-multiplier design, where it is
important to ensure that the reference voltage is independent of the supply voltage, the
circuit in Figure A-11 is created. Again, two identical transistors M3 and M4 give equal
amounts of reference current in each rail and a differential amplifier is embedded to
increase the output resistance. The difference is that the current sink transistors in the
beta-multiplier are replaced by the diodes created above, and note that diode D2 is
formed by K (=9) parallel connected D1.
VDD
VDD
M3
M4
-
I
+
nk  ln K
T
qR
R
VD2
VD1
D1,1
GND
D2 = D1, 9
GND
Figure A-11 Diode-reference, self-biasing circuit.
From equation(8.17), currents through D1 and D2 and the diode voltages for each
diode are shown below:
I D1  I S eVD1 / nVT  VD1  nVT  ln
I D1
IS
I D 2  K  I S eVD 2 / nVT  VD 2  nVT  ln
I D2
K  IS
(8.18)
(8.19)
Bearing in mind that VD1=VD2+ID2R and ID1=ID2=I, the following relations are
derived:
I S eVD1 / nVT
I S eVD1 / nVT
nVT  ln
 nVT  ln
 I S eVD1 / nVT  R
IS
K  IS
(8.20)
Finally:
R
nVT ln K
nk ln K
, I
T
I
qR
(8.21)
If we analyse equation (8.21) in more detail, it is important to notice that in this
circuit, the diode current shows PTAT behaviour. Consequently, given the target for a
temperature independent current source, two resistors (L·R) are incorporated to create a
Appendix A
Fundamental building blocks
204
CTAT current as shown in Figure A-12. As the temperature increases, the diode
voltage (VD1) decreases, hence causing the current through resistor (L·R) to decrease.
VDD
VDD
VDD
MA3
VDD
MA4
ICTAT+IPTAT M3
M4
VDD
VDD
M5
M6
M7
C≈ 0.2pF
ICTAT+IPTAT
VD1
MA1
ICTAT
Vref=600mV
Vbiasp
MA2
Vbiasn
IPTAT
R=16KΩ
MA5
VD2
L·R
≈ 225KΩ
≈ 38KΩ
L·R
≈ 225KΩ
≈119KΩ
N·R
≈ 90KΩ
D1,1
GND
D2 = D1, 9
GND
GND
GND
GND
GND
GND
GND
Figure A-12 Schematic of total bandgap reference circuit
When this theoretical design is implemented in practice, firstly, we choose
VD1=700mV, which is slightly higher than the single diode voltage at room
temperature. In particular, the assumption is that transistors M3 and M4 have the same
potential (700mV) at their drain and gate nodes, and the transistor dimensions for M3
and M4 are sized to W/L=1.0μm/0.4μm.
Next, from equation (8.17) and using the fitting parameter n=0.938, the current
through D1 is obtained by I=ID1≈3.3μA. Provided the diode D2 is formed by 9 parallel
connected D1, using equation (8.21), the value of resistor R is calculated to be 16KΩ.
Therefore, the following equations are written with all necessary parameters and
figures available:
I PTAT 
nk ln K
T
qR
(8.22)
VD1
LR
(8.23)
I CTAT 
Finally, suppose we are required to generate a constant reference voltage at half
of VDD(=1.2V), based on the circuit shown in Figure A-12, the combination of all
PTAT and CTAT currents through resistor N·R generate Vref=600mV.
Vref ,600 mV  N  R( I CTAT  I PTAT )
 nVT  ln K  N  N VD1 / L
(8.24)
Appendix A
Fundamental building blocks
205
For zero temperature coefficients:
k / q  0.085 mV / C
Vref ,600 mV
 0  N n
T
VT
T
1.77 mV / C
 ln K 
N VD1

L
T
(8.25)
Rearranging for L:
L
1.77
n  ln K  0.085
(8.26)
Thus, L is calculated for 9.95(L·R=161KΩ) and substituting this value into
equation (8.24), we get N for 4.85(N·R=78.4KΩ). Use these values for preliminary
simulation, the conclusive results are shown in Figure A-12 and listed in Table A-2.
Bearing in mind that the temperature behaviour of resistors and transistors are not
modelled in the above equations and the channel length modulation effect in the
reference voltage rail are neither considered, it is not surprising to find that final
dimensions and component values show a certain amount of difference from the
theoretically derived values.
Table A-2 Component values and transistor dimensions for BGR in Figure A-12
Component
Dimensions
Component
Dimensions
R
16K Ohms
M7 (W/L)
0.48μm/0.40μm
R·L
225K Ohms
MA1(W/L)
2.0μm/0.40μm
R·N
90K Ohms
MA3 (W/L)
4.2μm/0.40μm
M3, M4 (W/L)
1.0μm/0.40μm
MA1 (W/L)
2.0μm/0.40μm
M5 (W/L)
1.0μm/0.40μm
MA3 (W/L)
4.2μm/0.40μm
M6 (W/L)
3μm/0.40μm
MA5 (W/L)
2.0μm/1.0μm
600.00
Reference voltage(mV)
599.95
599.90
< 4.5μV/˚C(4.5ppm/˚C)
599.85
599.80
599.75
599.70
-40
0
40
80
120
Temperature (˚C)
Figure A-13 Temperature behaviour of BGR reference voltage at 600mV
Appendix A
Fundamental building blocks
206
Figure A-13 shows the temperature behaviour of BGR circuit (Vref=600mV). It
can be observed that the reference voltage almost maintains a constant level over the
temperature range between -40℃ to 120℃, with a temperature coefficient less than
4.5ppm/℃. Furthermore, based on the PTAT and CTAT mechanisms that have been
realized above, the DC biasing reference points (Vbiasn,Vbiasp) are generated with a
temperature independent characteristic as well, with device dimensions shown in
Figure A-12.
Take for example, for the biasing voltage Vbiasn analyzed in Figure A-7, its
temperature behaviour is shown in Figure A-14, from which we can observe a
tremendous amount of improvement. Although our knowledge about the process
variations tells us that when we realize this circuit in practice, measurement results will
differ from these perfect simulation results, the internal temperature-current balance
mechanism, formed by PTAT and CTAT currents, can ensure a significant amount of
improvement than the basic biasing approach.
Reference voltage(mV)
440
420
≈ 480 ppm/˚C
400
380
360
340
-40
< 5.7 ppm/˚C
0
40
Basic biasing
BGR
80
120
Temperature (˚C)
Figure A-14 Temperature behaviour comparison between BGR and basic biasing approach
Fundamental building blocks
207
112µm
Appendix A
150µm
Figure A-15 Layout of BGR
The layout of the BGR circuit is shown in Figure A-15, from which we can see
the purposely modelled diode (D1) and 9 of these connected in parallel to form D2. All
resistors were realized with unsilicide poly, which are the red portions of the layout. It
should be pointed out this BGR design is a preliminary example which is used to
explain the basic theory. When a BGR is used as a reference current/voltage generation
function within an industrial product, further optimization are required to improve the
PSRR (Power-Supply-Rejection-Ratio) and effect of variability on the process corners.
A.2 Operational amplifier
The operational amplifier (op-amp) is such an important building block that
numerous papers [4][10][30][96] address the issues of its designs and realizations. It
plays a fundamental role in many analogue IC designs, and many books [87] have been
published to present designs, realizations and applications in all aspects. In this section,
without going into a detailed analysis, basic opamp concepts are introduced, such as
Miller capacitance, pole splitting, and common-mode input voltage. Finally, one
example op-amp, which indeed is a rail-to-rail folded-cascode op-amp with class AB
output buffer and gain enhancement module, is presented with schematic, layout and
simulation results.
Appendix A
Fundamental building blocks
208
A.2.1 Single ended amplifier
Consider the example circuit shown in Figure A-16 (a), which has the same
structure as the right half rail of beta-multiplier circuit as shown in Figure A-3 (a). In
the amplifier design, depending on the application and design specifications, both the
speed (bandwidth) and the device mismatch are compromised. Therefore, in the
following example, we choose the channel length to be 3 times the minimum allowable
size 0.4µm, which is a typical balanced choice for analogue circuit design [10].
Furthermore, the DC current is defined as 20µA and this sets the DC biasing overdrive
voltage headroom at 15% of VDD, both of which can boost the amplifier bandwidth.
Therefore, the transistor sizes and DC biasing voltage are obtained as shown in Figure
A-16. Since the AC small signal behaviour is of interest, an ac signal (vs) is added in
series with the known DC bias condition (Vbiasn=470mV), and the transfer function
vout(s)/vin(s) is analyzed. The source node of transistor M1 is shared by both input and
output signal, therefore this type of amplifier is often termed as a Common Source (CS)
amplifier.
Firstly, for the low frequency (DC) gain of amplifier, from equation (8.2) and
process parameters listed in Table 1-3, the transconductance gm of transistor M1 is
given:
g m1  nCox
W
(VGS1  Vtn )  92.2 A / V
L
(8.27)
From a DC simulation, the output resistance ro1 of transistor M1 is estimated to
be 285KΩ, and if the output resistance of transistor M3 is assumed to be approximately
the same (≈285KΩ), the total output resistance is obtained:
Ro  ro1 || ro3  (285K  285K ) / (2  285K )  142.5K
(8.28)
Therefore, the low frequency small signal gain ADC=|Av| of this amplifier is:
Av 
R
Resistance in drain
 o  g m1 Ro  13.14  22.37dB
1
Resistance in source
g m1
(8.29)
Appendix A
Fundamental building blocks
209
VDD
M3
Vbiasp=730mV
M3
2.13 m
0.40 m
ro 3
Cgd 3
Cgd 1
vout
vout
vs
vin
vs
M1
M1
Cgd 1
0.63 m
0.40 m
vin


Cgs1
ro1 vin  vgs1
g m1vgs1
Ro
Cgd 3


Cgs1
vout
Vbiasn=470mV
GND
GND
(a)
(c)
(b)
Figure A-16 Common source amplifier with current source load.
Secondly, focussing on the frequency response, the dominant capacitive
components within the amplifier must be quantified, including the Cgs1 (gate-source
capacitance of M1), Cgd1 (gate-drain capacitance of M1), Cgd3 (gate-drain capacitance of
M3), as shown in Figure A-16(b). Normally, when a transistor is working in its
saturation region, equation (8.30) is used for the gate-source capacitance calculation [4]
and hence Cgs1 is calculated by 0.667·
0.63µm·
0.40µm·
0.0143 ≈ 2.41fF.
2
Cgs  W  L  Cox
3
(8.30)
Cgd  W  Cgdo
(8.31)
Whereas gate-drain capacitance is:
where Cgdo is the gate-drain overlap capacitance per-unit width. According to the
process parameters listed in Table 1-3, a transistor with 10µm width has a gate drain
capacitance of 5.25fF (4.48fF for PMOS). Thus, we estimate the Cgdo for the st12
process is 525pF/m (448pF/m for PMOS). Consequently, the gate-drain capacitances of
M1 and M3 are calculated to be 0.33fF and 0.954fF respectively.
Therefore, a generic small signal model for the CS amplifier can be derived as
shown in Figure A-16(c), from which we can have the following derived equations:
(vout (s)  vin (s))sCgd1  gm1vin (s)  sCgd 3vout (s)  vout (s) / Ro  0
(8.32)
Ro sCgd 1  Ro g m1
vout
( s) 
vin
Ro sCgd 1  Ro sCgd 3  1
(8.33)
From equation (8.33), it can be concluded that a zero occurs at frequency fz
fz 
and one pole occurs at frequency f1
g m1
2 Cgd 1
(8.34)
Appendix A
Fundamental building blocks
f1 
210
1
2 (Cgd 1  Cgd 3 ) Ro
(8.35)
If we substitute all the calculated component values, we get fz=44.3GHz and
f1=868MHz and can obtain the bode plot (in MATLAB) of the transfer function (8.33)
as shown in Figure A-17:
gain  22.95dB
25
Av( f )
dB
20
Calculation
15
Simulation
10
5
0
-5
-10
-15
7
10
f1  570MHz
8
10
9
10
10
10
Frequency(Hz)
11
10
12
10
180
160
Calculation
140
Av( f )
degree
Simulation
120
100
80
60
40
20
0
7
10
8
10
9
10
10
10
Frequency(Hz)
11
10
12
10
Figure A-17 Frequency response of CS amplifier in Figure A-16
In addition to the bode plot of the known equation(8.33), ac analysis simulation
(SPECTRE-RF) results of the above amplifier are plotted, from which we observe the
DC gain to be 22.95dB and the pole frequency around 570MHz. It is not surprising to
find some difference between the calculation and simulation results, since only those
two dominant capacitive components are modelled in the above theoretical equations.
On the other hand, it must be noted that in the above circuit (Figure A-16), an
ideal driving source v is assumed to be working with zero source impedance. In
practice, when the driving source impedance is included, the transfer function and the
location of system poles changes significantly.
Appendix A
Fundamental building blocks
211
VDD
Vbiasp
2.13 m
0.40  m
M3

vin
vout
vin
vg 1
Rs
vs
Rs
0.63 m
0.40  m
vg1 C gd 1

Cgs1
g m1vgs1
Ro
Cgd 3

vout

M1
Vbiasn
GND
(a)
(b)
Figure A-18 Common source amplifier with current source load and source impedance
As shown in Figure A-18, a source resistance Rs is inserted at the gate of
transistor M1, which is defined as node ―vg1‖. From equation (8.33),:
Ro sCgd 1  Ro g m1
vout
( s) 
vg 1
Ro sCgd 1  Ro sCgd 3  1
(8.36)
Therefore the relation between vg1 and vin can be expressed as:
vg1 ( s)  vin ( s)
Rs
 sCgs1vg1 ( s)  sCgs1 (vg1 ( s)  vout ( s))  0
(8.37)
Rearranging for vg1(s), we get:
vin ( s )
 vout ( s ) sCgd 1
Rs
vg 1 ( s ) 
1
 sCgd 1  sCgs1
Rs
(8.38)
Substituting equation (8.38) into (8.36) gives:
vin ( s)
 vout ( s ) sCgd 1
Ro sCgd 1  Ro g m1
Rs
vout ( s) 

Ro sCgd 1  Ro sCgd 3  1 1  sC  sC
gd 1
gs1
Rs
(8.39)
Rearranging for vout(s)/vin(s):
vout
( s) 
vin
Ro sC gd 1  Ro g m1
s [ Ro Rs (C gd 1C gs1  C gd 3C gs1  C gd 3C gd 1 )]  s[(C gd 1  C gd 3 ) Ro  (C gs1  C gd 1 ) Rs  C gd 1 g m1 Ro Rs ]  1
2
Again, the zero frequency is still there, given by:
(8.40)
Appendix A
Fundamental building blocks
fz 
212
g m1
2 Cgd 1
(8.41)
whereas the roots of the polynomial in the denominator are given by [10]:
f1 
1
2 [(Cgd 1  Cgd 3 ) Ro  (Cgs1  Cgd 1 ) Rs  Cgd 1 g m1Ro Rs ]
f2 
g m1Cgd 1
2 (Cgd 1Cgs1  Cgd 3Cgs1  Cgd 3Cgd 1 )
(8.42)
(8.43)
Further examining the equation for low frequency pole, f1, and remembering that the
low frequency gain Av=gm1·
Ro, equation (8.42) is rewritten as:
f1 
1
2 [(Cgd 1  Cgd 3 ) Ro  (Cgs1  Cgd 1 (1  Av )) Rs ]
(8.44)
It is interesting to note that when the source resistance is zero (i.e. Rs=0),
equation (8.44) is identical to equation (8.35). Meanwhile, it needs to be pointed out
that in practical op-amps, the coefficient (1+|Av|) is always large. Therefore, when this
coefficient is multiplied with capacitance Cgd1, the value of Cgd1 plays a dominant role
in the determination of the location of the pole frequency. Actually, because the two
nodes of capacitance Cgd1 are connected between the input and output nodes of the
amplifier, it can be effectively modelled as two separate capacitors connected to ground
as shown in Figure A-19 .
Or, for example, when the gate node (vg1) of M1starts to increase, the drain node
(vout) of M1 drops at a rate of Av, which means the current flow into and out of the
capacitance should be depicted by equation (8.45):
i
vg1  vout
1/ sCgd 1
 sCgd 1 (1  Av )vg1  sCgd 1 (1 
1
)vout
Av
(8.45)
Appendix A
Fundamental building blocks
213
VDD
VDD
M3
Vbiasp
M3
2.13 m
0.40 m
ro 3
Cgd 3
vout
vout
vin
vg 1
Rs
vs
0.63 m
0.40 m
M1
vin
Rs
vg 1
M1
ro1
vs
C gd 1 (1  Av )
Vbiasn
Cgs1
Cgd 1 (1 
GND
GND
(a)
1
)
Av
(b)
Figure A-19 Modelling of Miller capacitance
This mechanism is known as the ―Miller theorem‖[4], and capacitance Cgd1 is
termed the ―Miller capacitance‖. Furthermore, it can be found that effectively
increasing the capacitance Cgd1 can lead to the low frequency pole f1 (equation (8.42)
)being moved to a lower frequency and the high frequency pole f2 (equation (8.43))
being moved to a higher frequency. In other words, these two poles split from each
other, so the approach is named ―pole splitting‖.
40
20
Calculation
Simulation
0
Av( f )
dB
-20
-40
-60
-80
7
10
f1  140MHz
8
10
9
10
10
10
Frequency(Hz)
11
10
12
10
200
150
Calculation
Simulation
100
Av( f )
degree
50
0
-50
-100
7
10
8
10
9
10
10
10
Frequency(Hz)
11
10
12
10
Figure A-20 Frequency response of CS amplifier with source resistance
Appendix A
Fundamental building blocks
214
To demonstrate the above analysis, suppose that the source resistance Rs is
derived as 142.5KΩ. From equation(8.42), the calculated -3dB frequency (f1) is at
133.3MHz. And as shown in Figure A-20, the discrepancy between simulation and
calculation results (equation (8.40)) is tiny at a lower frequency range. If we compare
these results with the case that the source resistance is ―zero‖ as shown in Figure A-17,
the decrease of low frequency pole is obvious due to the pole splitting mechanism.
The reason why the source resistance in the above example is set to 142.5KΩ; is
primarily because that in two stages amplifier, the output impedance of first stage
behaves as the source resistance seen by the input node of second stage, which is
demonstrated in Figure A-21. Consequently, equation (8.41)-(8.44) can be migrated
into the analysis of a two stage amplifier.
VDD
M3
M4
Vbiasp
2.13 m
0.40 m
2.13 m
0.40 m
Cgd 1
vout
vin
vs
vg 2
0.63 m M2
0.40 m
M1

0.63 m vin  vgs1
0.40 m

Cc
vg 2
g m1vgs1
Ro1
Cin
g m 2 vgs 2
Ro 2

Co
vout

Ro 2  ro 2 ro 4
Ro1  ro1 ro 3
Vbiasn
Cin  Cgd 1  Cgd 3  Cgs 2
GND
Cc  Cgd 2
(a)
Co  Cgd 4  Cload (if any )
(b)
Figure A-21 (a) Two stage single-ended amplifier, (b) its small signal model
The location of zero is given by:
fz 
gm 2
g
 m 2 (if Cc  Cgd 1 )
2 (Cc  Cgd 1 ) 2 Cc
(8.46)
The locations of poles are given by:
f1 
1
2 [(Cc  Co ) Ro 2  (Cin  Cc ) Ro1  Cc g m 2 Ro 2 Ro 2 ]
(8.47)
g m 2Cc
2 (CcCin  CoCin  CoCc )
(8.48)
f2 
Moreover, the low frequency small signal gain is ADC=Av=gm1·
Ro1·
gm2·
Ro2.
In addition, in practical op-amp design, the DC gain of the amplifier is
considerably higher and the effective miller capacitance Cc is much bigger. Therefore,
Appendix A
Fundamental building blocks
215
the consequent result is that f1 moves to a much lower location than the other poles and
zeros, and hence the transfer function of amplifier can be written as:
Av ( f ) 
Vout ( f )
ADC
g m1 Ro1 g m 2 Ro 2


Vin ( f ) 1  j f 1  j 2 f  Ro1 g m 2 Ro 2Cc
f1
(8.49)
from which the unity gain frequency is approximated as:
Av ( f )  1

fun 
g m1
2 Cc
(8.50)
As proof of the above analysis, consider a design example, where we want to
design a two-stage amplifier that can supply a unity gain at a frequency (fz) of 100MHz.
From equation (8.50), the calculated effective Miller capacitance Cc is about 146fF.
Furthermore, from equations (8.46)-(8.49), the calculated the DC gain (Av) of the two
stages amplifier is 44.74dB, and dominant pole (f1) located at 503KHz, second pole (f2)
is at 3.143GHz, zero (fz) also located at about 100MHz. The simulation results shown in
Figure A-22 validate these calculation results.
VDD
M3
M4
Vbiasp
2.13 m
0.40 m
2.13 m
0.40 m
vout
146 fF
vin
vs
M1
0.63 m
0.40 m
0.63 m
0.40 m
M2
Vbiasn
GND
60
f1  585KHz
40
Av( f )
dB
20
-20
fun  f z  195MHz
Av  45.97dB
0
4
10
5
10
6
10
7
8
10
10
Frequency(Hz)
9
10
10
10
11
10
9
10
10
10
11
10
0
-100
Av( f )
degree
Phase margin ≈30°
-200
-300
-400
4
10
5
10
6
10
7
8
10
10
Frequency(Hz)
Figure A-22 Two stage amplifier with Miller capacitance compensation
Appendix A
Fundamental building blocks
216
As shown in Figure A-22, the effective capacitance Cc is realized by placing a
capacitor (≈146fF) between the gate and drain node of M2. Generally, in practical opamp design, in addition to this capacitor, a resistor is connected in series as well. This is
because when an op-amp is used within a negative feedback loop, stability issues
require that the phase shift at the unity gain frequency (fun) stays as far away possible
from 180°. On the other hand, when the phase shift is 180°, it is hoped that the
frequency component in this frequency is attenuated as much as possible. The phase
difference between 180°and the phase point, where unity-gain frequency happens, is
defined as the ―phase margin‖.
Note that in the transfer function (8.40) of the above design example, the zeros
located at unity gain frequency. Therefore, cancellation of this zero, which is achieved
by adding a resistor, can reduce the phase shift by 90°. From equation (8.46), the value
of this added resistor Rz is estimated at the level of 1/gm2:
fz 
1
2 Cc 1/ g m 2
 f z _ cancel 
1
2 Cc  (1/ g m 2  Rz )
(8.51)
VDD
M3
M4
Vbiasp
2.13 m
0.40  m
2.13 m
0.40  m
vout
8.8K 146 fF
vin
vs
M1
0.63 m
0.40  m
0.63 m
0.40  m
M2
Vbiasn
GND
60
f1  585KHz
40
Av( f )
dB
20
fun  105MHz
0
Av  45.97dB
-20
-40
4
10
5
10
0
-100
Av( f )
degree
6
7
10
10
Frequency(Hz)
8
10
9
10
10
10
11
10
8
10
9
10
10
10
11
10
Phase margin ≈92°
-200
-300
-400
4
10
5
10
6
7
10
10
Frequency(Hz)
Figure A-23 Two stages amplifier with Miller capacitance compensation and zero cancellation
Appendix A
Fundamental building blocks
217
Improvement of the phase margin by adding this zero cancelling resistor (Rz) can
be found in Figure A-23, where the unit gain frequency (fz) happens at about 105MHz
with phase margin at about 92°. Actually, the bode plot shown in Figure A-23 is the
general form of a CMOS op-amp and the analysis demonstrated above shows the
fundamental principles relating to op-amp design, with the exception of one thing, the
polarity of the input and output signal. One question that may arise is how is an op-amp
used within a negative feedback loop since the two stage amplifier shown in Figure
A-23 does not have a negative input node? The answer is that a general-purpose opamp incorporates a differential amplifier stage at its input ports as shown in Figure
A-24.

Op_amp

Cc

A1
A2
Buffer
Gain stage
Output buffer

Differential
amplifer
Figure A-24 Bock diagram of two stage op-amp with output buffer
A.2.2 Differential amplifier
Ideally, a differential amplifier is a device, which only functions with the
difference between two input signals, but does not function with the biasing voltage of
the input signal.
Appendix A
Fundamental building blocks
1/ g m3
id 1
M3
id 1
M4
218
ro 4
vout
vp
id 1
ro 2
vm
id 2
M1
M2
Vbiasn
Ro
M5
Figure A-25 Analytical model of differential amplifier
To make a qualitative analysis, consider the circuit shown in Figure A-25, where
two identical transistors M1 and M2 have their source node coupled to a current sink
(M5) and transistors M3 and M4 form a current mirror. Small signal models of these
transistors are shown with grey lines.
Stay with the ideal condition that current sink M5 has an infinite output resistance
(Ro=infinite). Therefore, current id1, id2 are only determined by the input signal vp, vm.
The current mirror structure ensures that current (id1) flow within the M1 and M3 is
mirrored into M4. As a result, the output voltage is:
vout  (id 1  id 2 )  (ro 2 || ro 4 )
(8.52)
Provided that the input signal vp and vm are in the differential form (vp=-vm), the
following relations can be derived:
id1  gmnv p  gmn (vm )  id 2
 id1  id 2   gmn (v p  vm )
(8.53)
Thus the differential mode gain (Ad) can be derived as
Ad 
Vout
 gmn  ( ro 2 || ro 4 )
v p  vm
(8.54)
where gmn is the transconductance of transistor M1 and M2.
On the other hand, returning to the practical situation, where the current sink has
a finite value of output resistance (Ro), if the input signals have same phase (vp=vm),
what we should realize is that currents id1 and id2(id1=id2=id) are determined both by the
input signal and finite output resistance, which are defined by:
vc  v p  vm  vgs1,2  2id Ro  2id Ro
(8.55)
In this situation, the output voltage vout is given by:
vout  id 
1
1
 id 
g m3
gm4
(8.56)
Appendix A
Fundamental building blocks
219
Then, the common mode gain Ac is defined by:
Ac 
vout 1/ g m3
1


vc
2 Ro
2 g m3 Ro
(8.57)
As an ideal differential amplifier, where we don‘t want any common mode
voltage, the ratio between the differential mode gain and common mode gain is defined
as Common Mode Rejection Ratio (CMRR):
Ad
 20  log[ gmn  ( ro 2 || ro 4 )2 gm 3 Ro ]
Ac
CMRR  20  log
(8.58)
Obviously, the most straightforward way to increase the CMRR is to increase the
output resistance (Ro) of current sink. However, this may lead to other negative effects
that designers may want to avoid. For example, consider the circuit shown in Figure
A-26, where a cascode structure adopted within the tail current path increases the
output resistance of the current sink. We understand that this amplifier can correctly
function only if all the transistors are working in the saturation region. Using the
cascode structure means that the minimum allowable input common voltage in Figure
A-26 is reduced by Vds,sat(VGS-Vtn) compared to the amplifier in Figure A-25. For the
st12 process utilized in this project and the DC biasing circuit shown in Figure A-16,
this means about 80mV-100mV reduction of the active region that amplifier can
correctly work within.
M4
M3
vout
vp
vm
M1
M2
Vbiasn2
M6
Vbiasn1
M5
Figure A-26 Differential amplifier with cascode tail current
Appendix A
Fundamental building blocks
220
A.2.3 Operational amplifier
As an outcome of the above analysis, a two stages op-amp with a class AB output
buffer [10] is presented in Figure A-28. As is shown in the later chapters of this thesis,
this op-amp is one of the pivotal components in the novel PLL design. Although we
only need this op-amp to drive a small pure capacitive load (<0.2pf), the unity-gain
bandwidth needs to be as wide as possible. It is also deirable that this wide bandwidth
characteristic can be maintained over a wide range of common mode input voltages, or,
say, at least from Vtn to VDD-Vtp. Finally, the power consumption of this op-amp is
critically confined to be no more than 1mW.
To achieve the above design target, firstly, a pair of differential amplifiers are
used to extend the common mode input voltage. In order to ensure that a higher DC
gain can be maintained within this common mode input region, the DC biasing voltage
for the transistors and their tail current is of great concern. As shown in Figure A-27, in
this design, the sub-threshold biasing point for the transistor was chosen within the tail
current path. Actually, the advantage of this approach can be seen in Figure A-6, where
a constant drain current can be maintained within 90% of the current source‘s output
voltage swing. Obviously, the disadvantage of this approach is a bigger chip area, but
as will be discussed in Chapter 6, in terms of the overall system this increase is not
significant.
VDD
VDD
VDD
VDD
VDD
Vbias1
32 m
0.8 m
3.68 m
0.80  m
32 m
0.8 m
3.68m
0.80m
3.68m
0.80m
32 m
0.8 m
Vbias2
32 m
0.8 m
4.8  m
0.8  m
Iref1
1.04 m
0.80  m
Vbiascm
Vbias3
6.9 m
0.8 m
6.9 m
0.8 m
6.9 m
0.8 m
6.9 m
0.8 m
6.9 m
0.8 m
GND
Vbias4
6.9 m
0.8 m
GND
VDD
~950mV
Vbias1
Vbias2
~800mV
~600mV
~400mV
~250mV
Vbias3
Vbias4
GND
GND
Figure A-27 DC biasing circuit for op-amp
Appendix A
Fundamental building blocks
221
Secondly, two gain enhancement modules were embedded within the op-amp,
which regulate the drain node of cascode devices in the main gain stage. Note that a
source follower was used to allow for the amplification of signals that are close to the
ground (P) or power (N).
Thirdly, an output buffer was incorporated which can ensure that the op-amp has
the capability to drive a 0.2pF loading capacitance at unity gain bandwidth (1.2GHz).
All the transistor and passive component dimensions are shown in the Figure A-28 and
the corresponding layout is shown in Figure A-29.
Appendix A
Fundamental building blocks
VDD
VDD
Vbias1
38.0 m
0.13 m
Vbias2
38.0 m
0.13 m
VDD
5.20  m
0.13 m
5.20  m
0.13 m


5.00  m
0.13 m
2.60 m
0.13 m
500 fF
vm
22.5 m
0.13 m
1.40m
0.13m
Vbias2
0.50 m
0.13 m
+
0.4 m
0.4 m
500 fF

1.40 m
0.4 m
0.3 m
0.4 m
GND
120 fF
2.00 m
0.13 m
GND
VDD
VDD
0.7  m
0.4  m
Vbiascm
1.00 m
0.13 m
P
GND
1.2  m
0.8  m
9.00  m
0.13 m
GND
2.00 m
0.13 m
GND
VDD
0.50 m
0.13 m

18.0 m
0.13 m
vout
Vbiascm
1.00 m
0.13 m
18.0 m
0.13 m
Vbias4
VDD
Vbiascm
1.40 m
0.13 m
2.00 m
0.13 m
2.60 m
0.13 m
N
Vbias3
vp
Vbias3
222
out
0.3 m
0.4 m
Vbiascm
0.6 m
0.4 m
3.0  m
0.4  m
0.6 m
0.4 m
1.5 m
0.4 m
out
+
-
0.33 m
0.8 m
1.80 m
0.4 m
GND
GND
P
N
Figure A-28 Schematic of a folded cascode op-amp with input common range extension and a
gain enhancement module
Appendix A
Fundamental building blocks
223
DC biasing
Generation
60µm
120µm
Differential
input pair
Figure A-29 Layout of op-amp in Figure A-28
As an assessment of this proposed op-amp, post layout level simulation results of
the op-amp‘s frequency response are shown in Figure A-30. It must be noted that the
DC biasing voltage (Vc) was swept from 200mV to 1000mV, and it was found that
within the majority of the sweep range (400mV-800mV), the unity gain frequency was
about 1.0GHz-1.2GHz and the DC gain up to 74.28dB.
Appendix A
Fundamental building blocks
224

vin

Vc
100 F
vout
Op_amp in
FigureA-28
200 fF
100M 
0
Phase margin >70°
-100
Av( f ) -200
degree
-300
-400 3
10
4
10
100
5
10
6
7
10
10
Frequency(Hz)
8
10
9
10
gain  75.67dB
Av( f ) 50
10
10
11
10
Vc=200mV
Vc=400mV
Vc=600mV
Vc=800mV
Vc=1000mV
gain  67.3dB
dB
fun  1.7GHz
0
fun  623MHz
-50 3
10
4
10
5
10
6
7
10
10
Frequency(Hz)
8
10
9
10
10
10
11
10
Figure A-30 Frequency response of op-amp in Figure A-28 (Post layout level simulation
results)
Furthermore, it must be pointed out that the above competitive results were
achieved with a DC power consumption of less than 0.7mW. If a higher unity gain
frequency is required, the transistor dimensions can be increased within the op-amp,
but the price would be a significant increase in power consumption.
Appendix B
Relation between jitter and phase noise
225
Appendix B Relation between
jitter and phase noise
Jitter and phase noise are those two interactive parameters that are used to
measure the signal purity in time and frequency domain respectively. Depend on
different noise sources and different shapes of phase noise spectrum, particular
mathematical equation between jitter and phase noise may appear some difference. In
this appendix, without assume a particular spectral density of phase noise, a general
link is derived between jitter and phase noise. Fundamentally, the derivation illustrated
below is same as the model given in Appendix of[34], but a more careful derivation is
proposed here from the beginning to the end.
Generally, consider the sinusoidal signal given in Equation (2.16):
Vout  A cos[2 f0t   (t )]
(9.1)
Suppose this signal is feed into an oscilloscope, which sample the input signal at
the defined threshold voltage (e.g. Vdd/2). The timing jitter Δt is termed as fluctuation
of time difference between every two or more periods at the threshold voltage crossing.
Take for example, at time instance t1and t2, the term inside bracket of equation (9.1)
can be written as:
2 f0t1   (t1 )  0
(9.2)
2 f0t2   (t2 )  2 N
(9.3)
where t1 is the first threshold voltage crossing point and t2 is the Nth threshold voltage
crossing point. Subtracting above two equations gives:
2 f0 (t2  t1 )   (t2 )   (t1 )  2 N
(9.4)
Appendix B
Relation between jitter and phase noise
226
(t)
10
8
6
4
2
0
t1
t2
t
Δt

T0
Figure B-1 Illustration of Jitter
The time difference between these two sample points is the number of nominal
period (T0=1/f0) plus the jitter:
  t2  t1  NT0  t
(9.5)
Substituting equation (9.5) into (9.4) yields:
2 f0  NT0  t    (t2 )   (t1 )  2 N
(9.6)
Organize this equation:
t 
T0
( (t1 )   (t2 ))
2
(9.7)
Illustration of these terms can be found in Figure B-1.
Since (t) is a continuously evolving variable, Δt is a stationary process.
Therefore, the standard derivation of Δt can be can be obtained:
 2t 

T02
E  2 (t1 )   2 E  (t1 ) (t2 )   E  2 (t2 ) 
4 2
where E[·] denote the expect value.

(9.8)
Appendix B
Relation between jitter and phase noise
227
Furthermore, from[37][38], the autocorrelation function of (t), R(), is defined
as:
R ( )  E  (t1 ) (t1   )  E  (t1 ) (t2 )
(9.9)
And note that autocorrelation and power spectral density function form a Fourier
transform pair[42], where equation (9.9)can be derived




R ( )   S ( f )e j 2 f  df   S ( f ) cos(2 f  )df
(9.10)
From which it can find that the value at the origin of autocorrelation function is equal
to the average power of the signal

R (0)  E  2 (t1 )   E  2 (t2 )    S ( f )df

(9.11)
Therefore, substituting equation (9.10) and (9.11) into(9.8), yields:
2T02
4 2
4T02
 2
4
8T 2
 02
4
 2t 








0
S ( f )(1  cos(2 f  ))df
S ( f ) sin 2 ( f  )df
(9.12)
S ( f ) sin 2 ( f  )df
It may note that when the time difference () is compared among every cycles, term N
in equation (9.5) is 1, which gives:
  T0  1/ f0
(9.13)
Hence, equation (9.12)can be organized as

 2t  2 S ( f )
0
sin 2 ( f / f 0 )
df
 2 f 02
(9.14)
Finally, according to[38], power spectral density function, S(f), can be
approximated to phase noise L ( f ) for large offset which gives:
  2
2
t

0
sin 2 ( f / f 0 )
L( f )
df
 2 f 02
(9.15)
Therefore, within appropriate offset frequency range, the mean square value of
timing jitters can be related with single side band phase noise with above equation.
Appendix B
Relation between jitter and phase noise
228
Appendix C
Measurement results of prototype chip 2
229
Appendix C Measurement results
of prototype chip 2
Appendix C
Measurement results of prototype chip 2
230
Appendix C
Measurement results of prototype chip 2
231
Appendix C
Measurement results of prototype chip 2
232
Appendix D
Matlab code for VCO model
233
Appendix D Matlab code for VCO
model
Appendix D
Matlab code for VCO model
234
Part(a) System settings and input variables
%Simulation_enviroment setting
systs=10e-11;
runtime=50e-6;
maxstep=systs;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%Process parameter
eox = 3.45e-11; % permittivity of the silicon oxide F/m
tox = 2.474e-9; %gateoxide thickness m
Cox = eox/tox; % gate oxide capacitance per unit areaf/m^2
up = 0.00704; %mobility of p
un = 0.02499; %mobility of n
Kpn = un*Cox;
Kpp = up*Cox;
ko = 1.38e-23; %Bolzman Constant
T = 300; %Temperature
Kfn=1e-24; %Flicker noise coefficient N
Kfp=1e-24; %Flicker noise coefficient P
gama = 2/3; %Thermal noise coefficient
Vth = 0.233; %Threshold voltage
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%Input VCO/Transistor dimensions
Wnc = 64e-6;
%Cascode N
Lnc = 0.4e-6; %Cascode N
Wpc = 199e-6; %Cascode p
Lpc = 0.4e-6; %Cascode p
Wni = 64e-6;
%Inverter N
Lni = 0.4e-6; %Inverter N
Wpi = 199e-6; %Inverter P
Lpi = 0.4e-6; %Inverter P
N=4; %Number of delay
VDD=1.2;
Vct=1.2; %control voltage
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%Calculated transistor/VCO paramters
half_rail= (VDD)/2;
VGS=VDD*0.75;
Veff=(VGS-Vth);
Ronn = (VGS)/(0.5*Kpn*(Wni/Lni)*(Veff^2));
Ronp = (VGS)/(0.5*Kpp*(Wpi/Lpi)*(Veff^2));
Cap=2.5*(Wni*Lni*Cox+Wpi*Lpi*Cox);
parastdelay=0*(Ronp+Ronn)*Cap;
gmln=un*Cox*(Wni/Lni)*(Vct-Vth); %transconductance of N-lump
fthermaln=4*ko*T*gmln*gama; % thermal noise floor of N
cornern=(Kfn/(Cox*Wni*Lni))*gmln*(1/(4*gama*ko*T)); %corner frequency N
thermal_floorn=(fthermaln/(2*systs));
gmlp=up*Cox*(Wpi/Lpi)*(Vct-Vth); %transconductance of P-lump
fthermalp=4*ko*T*gmlp*gama; % thermal noise floor of P
cornerp=(Kfp/(Cox*Wpi*Lpi))*gmlp*(1/(4*gama*ko*T)); %corner frequency P
thermal_floorp=(fthermalp/(2*systs));
Figure D-1 MATLAB control code for the propose Simulink VCO model (part A)
Appendix D
Matlab code for VCO model
235
Part(b) Simulation control and post processing for phase noise plot
freqtotal=[]; %initialization of variable
phasetotal=[];
phasemean=[];
Vct=1.2;
runs=1;
for it=1:runs
seedn1=floor(mod(now^2,17101)); % randomly generate the seed for N random generator
seedp1=floor(mod(now^2,44120)); % randomly generate the seed for P random generator
sim('dual_VCO_freq_noise_model_simple_phase_400n_v001.mdl');
%Run simulation of the proposed Simulink model;
freqtotal=[freqtotal;freq.signals.values];
freqmean=mean(freq.signals.values) % calculate the mean frequency
phasetotal=[phasetotal;phase.signals.values];
phasemeantmp=freqmean*phase.time; % corresponding phase from mean frequency
phasemean=[phasemean;phasemeantmp];
end
phaseoffset = phasetotal-phasemean; %Phase difference between the reality and ideal(mean)
value=phaseoffset;
Fs=1/systs;
f =[1e4:0.2e4:1.9e5,2e5:0.2e5:1.99e6,2e6:0.2e6:1.9e7,2e7:0.2e7:1.9e8,2e8:0.2e8:5e8];
[Pxx,f] = periodogram(value,'', f, Fs); %calculate the PSD of phase-offset
figure(1)
semilogx(f,((10*log10(Pxx/(1)))),'-r');
grid on;
Figure D-2 MATLAB control code for the propose Simulink VCO model (part B)
Appendix D
Matlab code for VCO model
236
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