Volume 44, Number 1, 2003
23
Sequencer for Four Phase Stepper Motor
Control
Alexandru MORAR
“Petru Maior” University of Târgu – Mureş, Romania
Department of Electrical Engineering
RO – 4300 Târgu – Mureş, 1 N. Iorga St.,
E–mail: morar@uttgm.ro
Abstract: The author propose in this paper a synthesis method of reversible pulse sequencers for 4 phase
stepper motor and the usual operating sequences: normal drive, wave drive, half- step drive. From the
study of different variants of pulse sequencers, the author concluded that the synthesis using T flip-flops is
more economical, concerning the simplicity of the combinational part and the time spared to perform this
synthesis. Concerning the code used for assignation, the use of natural binary code led to simpler
structures. The sequencers described in this paper, which can be made with TTL integrated circuits, offer
a high functioning safety.
Keywords: stepper motor, sequencer pulse, synthesis method.
1. Introduction
The performances of a stepper motor
(SM) are tightly connected with type and
quality of the used command and supply
circuits. Among performances like damping,
maximum values of operating frequency and
dynamic torque, it can be noted here the
efficiency and power losses which also
depend in a large measure on the command
and supply circuits [1][2][3]. Irrespective of
open-loop or closed-loop control, in order to
control and supply a SM the elements shown
in figure 1 are needed. The control of a
stepper motor is usually done by a power
electronic system which supplies sequentially
the phases of the motor. The distribution
sense of supply, as well as the sequence type
(symmetrical, are asymmetrical) and the
command frequency of phases done by
logical sequential processing with integrates
circuits. The current waveform in motor’s
phases are done by an power electronic
switching stage.
The role of this device is to take over
the command signals – usually standard TTL,
CMOS (the command, sense and sequence
type signals) – to distribute sequentially, to
amplify them and to deliver them to motor’ s
phases. Considering the above mentioned
consideration, the author propose in this
paper a synthesis method of reversible pulse
sequencers for 4 phase SM and the possible
operating sequences of it: wave drive, normal
drive and half – step drive [1] [2].
2. Synthesis of pulse sequencers
The pulse sequencers are blocks
which use command pulse train (TTL or
CMOS compatible) and the sense command,
in order to provide as output m (the number
of motor phases) pulse trains phase shifted
one to another with 2π/m electrical degrees
(the electric step) [2]. Theoretically, any
pulse sequencer has a sequential part (usually
consisting in a counter) and a combinational
part which performs the decoding of
operating sequence and, sometimes, the sense
of rotation if a synchronous counter or a shift
register is used.
24
ACTA ELECTROTEHNICA
DC POWER SUPPLY
V+
Controller
P.C. (μs)
Manual
pulse generator
Controller
P.C. (μs)
Manual
command
M
U
X
M
U
X
Command
pulse
Sense
Sequence
S
E
Q
U
E
N
C
E
R
A
B
C
D
FA
D
R
I
V
E
R
FB
S.M.
FC
FD
4 PHASE
STEPPER
MOTOR
Fig. 1. Electric drive system with stepper motor.
The versions achieved with flip-flop
circuits are included among the simplest
pulse sequencers [1] [3]. Using the
synchronous
flip-flop,
the
hazard
phenomenon is eliminated. We describe
below the method of synthesis of a four
phases stepper motor (A, B, C, D) sequencers
for three supplies: wave drive, normal drive
and half-step.
The study of pulse sequencers
concluded that the synthesis using T flip-
flops is more economical, concerning the
simplicity of the combinational part and the
time spared to perform this synthesis.
Concerning the code used for assignation, the
use of natural binary code led to simpler
structures. The S variable establishes the
rotation sense as following: clockwise S=1,
anticlockwise S=0. The T flip-flop
functioning is based on truth and excitation
tables as seen in figure2.
Fig. 2. Truth and excitation table for T flip-flop.
2.1. Synthesis of sequencers for wave drive
On wave drive mode it is supplied a
phase, one by one. So, there the following
situations:
- the clockwise (S=1) imposes the
order: A, B, C, D, A, B,….;
- the anticlockwise (S=0) imposes
the order: A, D, C, B, A, D,…;
Analyzing the sequence for every
rotation sense results the necessity of a
logical sequential circuit with four stable
states. These can be materialized with two T
flip-flops, of which outputs are noted with
Q1(MSB), Q0(LSB).
g.3. Assignation table
Fig. 3. Assignation states.
Volume 44, Number 1, 2003
The assignation of states is shown in
figure 3 and the transitions graph is shown in
figure 4. Figure 5 shows the excitation table
and figure 6 shows the status decoding.
25
The logic block diagram and logic
timing diagram of wave drive sequencer are
shown in figure 7 and figure 8.
Fig. 7. Logic block diagram for wave drive mode.
Fig. 4. Transitions graph for wave drive mode.
S
0
0
0
0
1
1
1
1
tn
Q1
0
0
1
1
0
0
1
1
Q0
0
1
0
1
0
1
0
1
tn+1
Q1 Q0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
0
T1
T0
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
Fig. 5. Excitation table for wave drive mode.
Q1 Q0 Sk
0
0
1
1
0
1
0
1
S0
S1
S2
S3
Motor Phases
A = Q1 ⋅ Q0
A B C D
1 0 0 0 ⇒ B = Q1 ⋅ Q0
0 1 0 0
C = Q1 ⋅ Q0
0 0 1 0
D = Q1 ⋅ Q0
0 0 0 1
Fig. 6. States decoding for wave drive mode.
Fig. 8 Logic timing diagram for wave drive mode.
2.2. Synthesis of sequencers for normal
drive
On a normal drive mode there are
supplied two phases simultaneously. So,
there are following situations:
- the clockwise (S=1) imposes the
order: AB, BC, CD, DA, AB,…;
- the anticlockwise (S=0) imposes the
order: AB, AD, CD, BC, AB, AD,…;
As it was described above results the
necessity of a logical sequential circuit with
four stable states, which means two T flipflops of which outputs are noted with
Q1(MSB), Q0(LSB). The assignation of states
is shown in figure 9 and the transitions graph
is shown in figure 10.
Phases supplied
AB
BC
CD
AD
Sk
S0
S1
S2
S3
Q1 Q0 Q0
0 0 0
0 1 1
1 0 0
1 1 1
Fig. 9. Assignation states.
Q0
S0 S1
S2 S3
Q1
26
ACTA ELECTROTEHNICA
Fig. 13. Logic timing diagram for normal drive mode.
Fig. 10. Transition graph for normal drive mode.
We can see that the assignation of
states and the transitions graph are same with
the previous sequencer. Thus, result the same
logical expressions for memory excitation
variables. The states decoding is shown in
figure 11.
Q1 Q0 Sk
0
0
1
1
0
1
0
1
S0
S1
S2
S3
Motor Phases
A B C D
1 1 0 0
0 1 1 0
0 0 1 1
1 0 0 1
⇓
A = Q1 ⋅ Q 0 + Q1 ⋅ Q 0 = Q1 ⊕ Q 0
B = Q1
C = Q1 ⋅ Q 0 + Q1 ⋅ Q 0 = Q1 ⊕ Q 0
D = Q1
Fig. 11. States decoding for normal drive mode.
The logic block diagram is shown in
figure 12 and logic timing diagram of wave
drive sequencer in figure 13.
2.3. Synthesis of sequencers for half - step
drive
A half – step drive alternates a phase
supply with two successive phases supply:
one of these is the one supplied individually
in a previous moment. There are following
situations:
- the clockwise (S=1) imposes the order:
A, AB, B, BC, C, CD, AD, A,…;
- the anticlockwise (S=0) imposes the
order: A, AD, D, CD, C, BC, B, AB, A,.. .
As it was described above results the
necessity of a logical sequential circuit with
eight stable states, which means three T flip –
flops of which outputs are noted with
Q2(MSB), Q1, Q0 (LSB). The assignation of
states is shown in figure 14 and the
transitions graph is shown in figure 15.
Phases
Supplied
A
AB
B
BC
C
CD
D
AD
Sk Q2 Q1 Q0
S0
S1
S2
S3
S4
S5
S6
S7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Q1
Q0
S0
S4
Q2
Fig. 12. Logic block diagram for normal drive mode.
S2
S5
S3
S6
S1
S7
Fig. 14. Assignation states.
Volume 44, Number 1, 2003
27
Q1
1
0
0
1
S
1
0
0
1
0
1
1
0
Q0
0
1
1
0
Q2
⇓
T1 = S ⋅ Q 0 + S ⋅ Q 0 = S ⊕ Q 0
Q1
S
1
0
0
1
0
0
0
0
0
1
1
0
Q0
0
0
0
0
Q2
⇓
T2 = S ⋅ Q1 ⋅ Q 0 + S ⋅ Q 1 ⋅ Q 0
Fig. 16. Excitation table for half – step drive mode.
Fig. 15. Transitions graph for half step drive mode.
Figure 16 shows the excitation table
and figure 17 a, b shows the states decoding.
Excitation table
Q2 Q1 Q0 Sk
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S0
S1
S2
S3
S4
S5
S6
S7
Motor phases
A B C D
1 0 0 0
1 1 0 0
0 1 0 0
0 1 1 0
0 0 1 0
0 0 1 1
0 0 0 1
1 0 0 1
Q1
1
0
0
0
0
1
Q0
1
0
Q2
⇓
A = Q 2 ⋅ Q1 ⋅ Q 0 + Q 2 ⋅ Q1
Q1
1
1
1
1
S
Q2
1
1
1
1
1
1
1
1
⇓
T0= “1”
1
1
1
1
Q1
Q0
0
0
Q2
1
0
1
0
Q0
1
0
⇓
B = Q 2 (Q 1 + Q 0 )
Fig. 17.a. States decoding for half – step drive mode.
28
ACTA ELECTROTEHNICA
Q1
0
1
0
0
1
0
Q0
0
1
Q2
⇓
C = Q 2 ⋅ Q1 ⋅ Q 0 + Q 2 ⋅ Q1
Q1
0
0
Q2
0
1
0
1
Q0
0
1
⇓
D = Q 2 (Q1 + Q 0 )
Fig. 17.b.States decoding for half–step drive mode.
The logic block diagram for half-step
drive is shown in figure 18. The logic timing
diagram of half step-drive sequencer is
shown in figure 19.
We achieved these sequencers using
LS TTL integrated circuits made by Texas
Instruments.
Fig. 18. The logic block diagram for half-step drive.
3. Conclusion
The performances of a stepper motor
are tightly connected with type and quality of
the used command and supply circuits.
Therefore, a high attention should be granted
to the sequencer, too.
Fig. 19. The logic timing diagram for half-step drive.
The sequencers described in the
paper, which can be made with LS TTL
integrated circuits, offer a high functioning
safety. We preferred sequencers with
counters instead of shift registers because of
the noise behavior (accidental external
impulse) of these two types of sequencers.
References
[1] Acarnley, P.P.,: Stepping Motors: a
Guide to Modern Theory and Practice.
Peter Peregrinus Ltd., ISBN: 0 86
341027 8, London, 1992.
Sisteme electronice de
[2] Morar, A.,:
comandă şi alimentare a motoarelor pas
cu pas implementate pe calculatoare
personale.
Teză
de
doctorat,
Universitatea Tehnică din Cluj-Napoca,
2001.
[3] Morar, A.,: Echipamente de comandă a
motoarelor pas cu pas implementate pe
calculatoare personale.
Editura
Universităţii “ Petru Maior ” din Tg.Mureş, ISBN: 973-8084-47-4 , Tg.Mureş,2002.
[4] Toacşe, Gh.,: Sinteza translatorului
pentru motorul pas cu pas (The synthesis
of the stepper motor’s sequencer), In:
EEA – Electrotehnica, No.2, pp. 81 - 85,
Bucureşti, 1976.