Test Report: DC Power-Line Communication
Reference Design
5HIHUHQFH'esign
Literature Number: TIDU168
October 2013
Chapter 1
TIDU168 – October 2013
System Description
The DC (24 V, nominal) Power-Line Communication (PLC) reference design is intended as an evaluation
module for users to develop end-products for industrial applications leveraging the capability to deliver
both power and communications over the same DC-power line. The reference design provides a complete
design guide for the hardware and firmware design of a master (PLC) node, slave (PLC) node in an
extremely small (approximately 1-inch diameter) industrial form factor. The design files include
schematics, BOMs, layer plots, Altium files, Gerber Files, a complete software package with the
application layer, and an easy-to-use Graphical User Interface (GUI).
The application layer handles the addressing of the slave (PLC) nodes as well as the communication from
the host processor (PC or Sitara™ ARM® MPU from Texas Instruments). The host processor
communicates only to the mater (PLC) node through a USB-UART interface. The master node then
communicates to the slave nodes through PLC. The easy-to-use GUI is also included in the EVM that runs
on the host processor and provides address management as well as slave-node status monitoring and
control by the user.
The reference design has been optimized from each slave (PLC)-node source-impedance perspective that
multiple slaves can be connected to the master (see Section 2.1). Protection circuitry has also been added
to the analog front-end (AFE) so that it can be reliably AC coupled to the 24-V line (see Section 2.4). Also
note that this reference design layout has been optimized to meet the PLC-power requirements. See for
the AFE031 layout requirements for high-current traces.
At the heart of this reference design are the AFE from TI, AFE031, to interface with power lines and the
TMS320F28035 Piccolo™ Microcontroller that runs the PLC-Lite protocol from TI.
1.1
AFE031
The AFE031 device is a low-cost, integrated, power-line communication (PLC) AFE device that is capable
of capacitive-coupled or transformer-coupled connections to the power line while under the control of a
DSP or microcontroller. The AFE031 device is also ideal for driving low-impedance lines that require up to
1.5 A into reactive loads. The integrated receiver is able to detect signals down to 20 µVRMS and is
capable of a wide range of gain options to adapt to varying input signal conditions. This monolithic
integrated circuit provides high reliability in demanding power-line communications applications. The
AFE031 transmit power-amplifier operates from a single supply in the range of 7 V to 24 V. At a maximum
output current, a wide output swing provides a 12-VPP (IOUT = 1.5 A) capability with a nominal 15-V
supply.
The analog and digital signal-processing circuitry operates from a single 3.3-V power supply. The AFE031
device is internally protected against overtemperature and short-circuit conditions. The AFE031 device
also provides an adjustable current limit. An interrupt output is provided that indicates both current limit
and thermal limit. There is also a shutdown pin that can be used to quickly put the device into its lowest
power state. Through the four-wire serial-peripheral interface, or SPI™, each functional block can be
enabled or disabled to optimize power dissipation. The AFE031 device is housed in a thermally-enhanced,
surface-mount PowerPAD™ package (QFN-48). Operation is specified over the extended industrial
junction temperature range of –40°C to +125°C.
2
System Description
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C2000
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1.2
C2000
The F2803x Piccolo family of microcontrollers (C2000™) provides the power of the C28x core and controllaw accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This
family is code-compatible with previous C28x-based code, as well as providing a high level of analog
integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made
to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with
internal 10-bit references have been added and can be routed directly to control the PWM outputs. The
ADC converts from 0 to 3.3-V fixed full scale range and supports ratiometric VREFHI and VREFLO
references. The ADC interface has been optimized for low overhead and latency.
Based on TI’s powerful C2000-microcontroller architecture and the AFE031 device, developers can select
the correct blend of processing capacity and peripherals to either add power-line communication to an
existing design or implement a complete application with PLC communications.
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3
Chapter 2
TIDU168 – October 2013
Test Data
NOTE: The test data for the DC-PLC Reference Design is also included in the reference design
document TIDU160.
2.1
Multiple Slave Nodes Support
The reference design is optimized from an impedance perspective to support multiple slave nodes. Refer
to the SAT0021 schematic (see Figure A-1), as more and more nodes are added, the C11 capacitor is
added in parallel and therefore the total capacitance as seen by a slave node increases. To support
multiple slave nodes, the source impedance must be very small as compared to the load impedance (see
Figure 2-1).
C11 (100 pF) creates a low-pass filter and, as multiple nodes are added, the effective capacitance
increases. Note that a PLC network is a star topology where each node drives the effective combination
load of every other node. Thus C11 is chosen to be 100 pF such that even when up to 10 nodes are
added the effective capacitance would be 100 pF x× 10 = 1nF. Therefore the impedance at the PLCmodulation band (see ) is calculated with Equation 1
1
Impedance =
= approximately 1.8kW
2pƒC
where
•
•
ƒ = 90 kHz
C = 1 nF = 100 pF × 10
(1)
Figure 2-1. Power-Line Communication AC-Coupling Protection Circuitry
NOTE: Equation 2 is a key requirement to drive multiple slave nodes.
Source Impedance << Load Impedance
(2)
For the following calculation assume that the PLC-Lite modulation frequency is approximately 40 KHz. The
source impedance of a PLC node is then calculated as shown in Equation 3.
1
1
Source Impedance =
=
= 0.18 W
2pƒc 2p(40000)(0.000022)
where
•
4
c = C6 = 22 µF (see )
Test Data
(3)
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Multiple Slave transmissions and System Latency
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Assume that the load impedance of a given slave node as seen by the driver PLC-node is approximately
30 Ω. As multiple slaves are added, this load impedance is reduced as the loads are seen as a parallel
combination of load impedances. For example, if there are nine slaves on the system, then the total load
impedance as seen by one driver PLC-node is calculated as shown in Equation 4.
9 (slaves) + 1 (Master) = 10 PLC nodes, Load Impedance = 30/10 = 3 Ω
4 (slaves) + 1 (Master) = 5 PLC nodes, Load Impedance = 30/5 = 6 Ω
(4)
(5)
Based on the system requirements, optimizing the capacitance C6, 22 µF, and C11, 100 pF, is important
in order to meet the requirement of Equation 2.
Figure 2-2. Test Results: One Master and Four Slaves
Figure 2-3. Test Results: One Master and No Slaves
As seen in Figure 2-2 and Figure 2-3, there is an insignificant change in amplitude of the modulation
signal as more slaves are added. In the previous setup, the 24-V DC line is probed (AC coupled) to the
oscilloscope. The oscilloscope is triggered when the button on the PLC node is pressed as it generates a
PLC communication packet.
2.2
Multiple Slave transmissions and System Latency
Figure 2-4. System Latency
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Multiple Slave transmissions and System Latency
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PLC-Lite contains a simple CSMA/CA, MAC which means that if multiple slaves try to access the 24-V DC
line, the MC layer in PLC-Lite senses that the line is busy and backs off for a random duration. The total
latency for a typical transaction is thus a function of this random back-off for both the initial message and
response, as well as the fixed time required to transmit the messages on the line. As shown in Figure 2-4,
the system-level latency with one button press event was captured at approximately 80 to 200 ms. This
measurement is typical for the default MAC and PHY layer settings used by the demonstration firmware.
Modifying MAC or PHY layer parameters can change the system latency.
6
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15-V Power-Supply Performance for AFE Power Amplifier
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2.3
15-V Power-Supply Performance for AFE Power Amplifier
For this reference design, note that the 24-V DC supply generates a 15-V and 3.3-V supply as well as it is
modulated by the AFE031 for PLC communication. The key point to note is that the switching-regulator
operation that generates the 15 V and 3.3 V can interfere with PLC modulation if proper power supply
filtering is not included in the design.
To ensure the above requirement, refer to the schematic as shown in : the first circuit seen by the 24-V
DC line is a low-pass filter (see Section 2.3.1) which is a very important element of the design. Without
this low-pass filter circuit, PLC communication will not work.
Figure 2-5. Power Section of the Schematic Showing the Low-Pass Filter
Figure 2-6. 15-V Section of the Power Schematic
In the DC-PLC reference design, another key requirements is to ensure that in an application when a PLC
node transmits or receives data, the power amplifier for the AFE031 device is provided with the necessary
power (500-mA power budget for the maximum TX swing) to drive the line and to drive the line with a fast
response time. The LM34910 step-down switching regulator is used in this reference design (see
Figure 2-6) to generate the 15 V for the power amplifier of the AFE031 device. The LM34910 device
features all of the functions required to implement a low-cost efficient buck-bias regulator capable of
supplying up to 1.25 A to the load. This buck regulator contains a 40-V N-Channel buck switch, and is
available in the thermally enhanced WSON-10 package.
NOTE: The LM34910 device features a hysteretic-regulation scheme that requires no loop
compensation, results in fast load-transient response, and simplifies circuit implementation.
The operating frequency remains constant with line and load variations because of the inverse relationship
between the input voltage and the on-time.
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15-V Power-Supply Performance for AFE Power Amplifier
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PLC Modulation
15-V DC Power
Figure 2-7. LM34910 With a 22-µH Inductor (TX Level 2 Vpp)
As shown in Figure 2-7, the LM34910 device as implemented in this reference design, provides the
necessary power for the AFE031 to meet the PLC functionality.
NOTE: As seen in Section 2.5, the TX level of 2 Vpp is enough to drive up to a 40-m (length) cable
without any BER.
2.3.1 T-Type Low-Pass Filter Design
As shown in and , a low-pass filter separates the PLC modulation signal from the switching regulator. The
Fc of the low-pass filter is calculated based on the band occupied by the PLC modulation. As shown in ,
the PLC Lite occupies 42 to 90 kHz. Therefore, the Fc as per the low pass filter in comprises of L = 360
µH (180 µH + 180 µH) and C of 1 µF.
1
Fc =
= approximately 17 kHz
p ´ LC
(6)
NOTE: Because of the space constraint on this reference design, the previous values of LC were
selected. However in applications where board space is available, a lower cutoff Fc (lower
than 10 KHz) is desirable.
8
Test Data
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PLC-Coupling Circuit Protection
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2.4
PLC-Coupling Circuit Protection
Figure 2-8. First-Stage AC Coupling
Figure 2-9. Second-Stage AC Coupling
To ensure the reliability of the overall system, the 24-V line is not directly AC coupled to the AFE031
device. The line goes through a two-step AC coupling (see Figure 2-8 and Figure 2-9). In the first stage,
the 24-V line is AC coupled to an intermediary stage that has a TVS protection and therefore arrests
voltage surges to 9.2 V for a peak surge current of 43.5 A. In this stage the common mode is biased to the
GND. In the second-stage AC coupling, the data is AC coupled to the AFE031 device with a DC bias of
7.5 V. To ensure reliability, a simple test of powering off the node completely and then powering up the
node was performed on five nodes approximately 250 times. This stress tests ensures that the surges on
the power supply can be applied to the node under test.
Table 2-1. Reliability Data
PLC NODE
COMPLETE POWER-ON AND
POWER-OFF SEQUENCE
1
250 times
2
250 times
3
250 times
4
250 times
5
250 times
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STATUS
Pass, no reliability failure, no change in current
drawn observed pre-stress and post-stress
Test Data
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PLC-Coupling Circuit Protection
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2.4.1 PLC TX and RX Impedance-Path Testing
The impedance path of the TX and RX is optimized to avoid any signal losses to the PLC-modulation
signal.
Figure 2-10. Power-Line Communication AC-Coupling Protection Circuitry
Figure 2-10 shows that R1 at 0 Ω provides optimized load impedance to the modulation signal. If R1 in
Figure 2-10 is even changed to 15 µH (for example), the modulation signal is severely impeded as shown
in Figure 2-11 and Figure 2-12.
PLC Transmitter
Signal
PLC Transmitter
Signal
PLC Receiver
Signal
PLC Receiver
Signal
Figure 2-11. RX Signal Impeded With 15-µH
Inductance
10
Figure 2-12. RX Signal Optimized With 0-Ω Resistor
(R1)
Test Data
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PLC-Cable Performance Data
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2.5
PLC-Cable Performance Data
For performance characterization, a 40-m cable was used. To characterize the cable, use the following
steps:
1. Generate a chirp signal.
2. Capture the response of the chirp after the cable as shown in Figure 2-13.
3. Post-process (correlation) the signal using Matlab® to generate the impulse response.
4. Leverage the impulse response of the given 40-m cable to generate approximately 320-m cable
impulse response.
Figure 2-13. Cable Modeling Approach
Figure 2-14. Channel-Frequency Response of 40-m
Cable (Using Actual Cable)
Figure 2-15. Channel-Frequency Response of 320-m
Cable (Extrapolated)
The channel loss of the 320-m cable is not significantly more than the 40-m cable even up to 100 KHz as
shown in Figure 2-14 and Figure 2-15.
The 40-m cable was then used with the DC-PLC hardware to collect the BER measurements across
different AFE031 TX-amplitudes as shown in Figure 2-16. The software and firmware used to conduct
BER testing is part of the PLC-Lite SDK and are not included in the demonstration software provided with
this design.
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PLC-Cable Performance Data
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Figure 2-16. BER Measurement Using the 24-V DC PLC Hardware and the 40-m Cable
Figure 2-17. BER Data: No Packet Errors With Levels 5 and 6 (15 dB and 18 dB Below 15-V pp)
12
Test Data
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PLC-Cable Performance Data
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Figure 2-18. BER Data: No Packet Errors, Level 7 (21 dB Below 15-V pp)
Table 2-2. BER Measurement Results
TX AFE031 LEVEL
DECIBELS BELOW MAXIMUM
AMPLITUDE
5
15 dB
6
18 dB
7
21 dB
BER DATA
0 packet error out of 10000 packets transmitted
The data listed in Table 2-2 confirms that the TI PLC-Lite solution with an OFDM solution can support
cable length up to 320 m with a very-low TX amplitude of the AFE031 resulting in a large margin to
support even longer cables.
2.5.1 Thermal Performance of the Design
To confirm the thermal performance of the design a simple test was performed. To perform the test, the
power amplifier was programmed to send a PLC-modulation signal every 1 second. Thermal-imaging
camera hot spots were analyzed at time (t0) and then 30 minutes after launching the application (t1). The
purpose of this test is to confirm that the design can effectively dissipate heat without localized heating.
As shown in Figure 2-19 and Figure 2-20, there is no localized heating observed in the system after time,
t1, compared to t0. For layout guidelines of the AFE031 device and high-current trace routing, see
Section D.1.
NOTE:
For the thermal-performance application testing, the TX setting for the AFE031 device was
set to Level 3.
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IEC Electrostatic-Discharge Testing
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Figure 2-19. t0
2.6
Figure 2-20. t1
IEC Electrostatic-Discharge Testing
The UART and JTAG interface pins on the SAT0022 processor section have IEC ESD-protection up to
±30-kV air, as well as ±30-kV contact which is provided by the TPD1E10B06 device from TI (see the
product folder for more information, http://www.ti.com/product/tpd1e10b06). lists the device level-IEC ESD
testing data.
Table 2-3. Device-Level IEC ESD Testing
IEC-CONTACT
SPEC = ± 30 kV
LEVEL
14
IEC-AIR
SPEC = ± 30 kV
UNIT1
UNIT2
UNIT3
UNIT1
UNIT2
UNIT3
±2 kV
PASS
PASS
PASS
PASS
PASS
PASS
±4 kV
PASS
PASS
PASS
PASS
PASS
PASS
±6 kV
PASS
PASS
PASS
PASS
PASS
PASS
±8 kV
PASS
PASS
PASS
PASS
PASS
PASS
±15 kV
PASS
PASS
PASS
PASS
PASS
PASS
±20 kV
PASS
PASS
PASS
PASS
PASS
PASS
±25 kV
PASS
PASS
PASS
PASS
PASS
PASS
±30 kV
PASS
PASS
PASS
PASS
PASS
PASS
Test Data
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Appendix A
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Schematics
The schematics are presented in the following order:
1. PLC Node
• Power Section — SAT0021 (see Figure A-1)
• C2000 and AFE031 — SAT0022 (see Figure A-2, and Figure A-3)
• Application Board — SAT0023 (see Figure A-4)
2. USB to UART Board — SAT0045 (see Figure A-5)
3. Master Base Board — SAT0029 (see Figure A-6)
4. Slave Base Board — SAT0030 (see Figure A-7)
5. JTAG Programming Board — SAT0024 (see Figure A-8)
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Schematics
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15
Appendix A
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24_IN
J1
24V Power i
1
2
3
4
4 pin connector that provides 24V and GND to the PLC node
MMS-102-02-T-DV
24_IN
GND
24_POWER
D2
L3
L4
7447789218
180µH
0.65V
ZHCS350TA
Low Pass Filtering that isolates the Power Line Communication Signal from the Switching Regulator
7447789218
C36 180µH
1.0µF
50V
GND
R41
R42
4.99k
1 kOhms
15V Power
U1
GND
6
7
R43
76.8k
8
FB
RTN
SS
SGND
RON/SD
9
VCC
24_POWER
10
11
TPAD
GND
VIN
ISEN
BST
SW
5
3
Switching Regulator that converts 24V to 15V
PMEG6010CEH,115
4
GND
A
2
C29
35V
1
0.047µF
K
D1
15V Power
i
L1
15V Power
i
R47
1.1
LM34910CSD/NOPB
C33
1.0µF
50V
C34
4700pF
100V
Vafe_15
VLC6045T-220M
C35
0.1µF
50V
C32
4.7µF
35V
i
Ground
Switching Regulator that converts 15V to 3.3V
3.3V POWER
GND
U2
1
Vafe_15
2
C30
10µF
35V
R15
3
10k
4
GND
PGND
PG
VIN
SW
TPAD
9
EN
VOS
GND
AGND
FB
8
3.3V Power
i
R44 100k
L2
7 3.3V_L2_Buck
VLF3012ST-2R2M1R4
i
3.3V Power
6
R45
562k
5
3.3V
C31
22µF
10V
R46
180k
TPS62170DSG
GND
Power Line Communication AC Coupling Protection Circuitry
PLC_MOD
24_IN
22µF
R1
0
PLC node Board to Board Connectors
3.3V
Vafe_15
3.3V Power i
PLC_MOD
Ground i
C18
10µF
C5
10µF
35V
Vafe_15
3.3V
SW_INPUT_LEGACY
J4
J6
DNI
DNI
LED_CONTROL_LEGACY
2
1
C10
10µF
2
1
24_IN
C17
47µF
C11
100pF
2
1
2
L6
1m
1
D3
SMAJ5.0CA-13
2
1
R32
4.7
2
1
C6
J5
J7
DNI
DNI
GND
GND
GND
GND
GND
Figure A-1. SAT0021 — Power Section of the PLC Node
16
Schematics
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Appendix A
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R11
3.3V
10k
3.3V
SW_INPUT_LEGACY
LED_CONTROL_LEGACY
nACK
GPIO_34
PG
nEN
R32
10k
GND
C21
43
44
45
46
47
48
49
50
U4
TMX320F28035RSHS
GPIO36/TMS
GPIO5/EPWM3B/SPISIMOA/ECAP1
GPIO4/EPWM3A
GPIO2/EPWM2A
GPIO0/EPWM1A
VDDIO
VDD
51
52
54
55
53
VREGENZ
GND
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
2
GPIO22/EQEP1S/LINTXA
1.2µF
6.3V
GPIO1/EPWM1B/COMP1OUT
1
GPIO34/COMP2OUT/COMP3OUT
GND
GPIO20/EQEP1A/COMP1OUT
i Ground
GPIO21/EQEP1B/COMP2OUT
GND
VSS
C20
0.1µF
TPAD
C19
0.1µF
56
57
i 3.3V Power
TMS
TDI
GPIO35/TDI
42
TDO
GPIO23/EQEP1I/LINRXA
GPIO37/TDO
41
TCK
3
R14
4.75k
RESETn
GPIO38/TCK/XCLKIN
VSS
GPIO19/XCLKIN/SPISTEA /LINRXA/ECAP1
XRS
VDD
40
SPISTEA
C22
1.2µF
6.3V
3.3V
VDD
4
39
C25
15 pF
GND
5
GND
38
TRST
VSS
37
GND
6
GND
3.3V
8
X1
R17
10k
ADCINA6/COMP3A/AIO6
X2
9
ADCINA4/COMP2A/AIO4
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
35
34
GPIO_06
C26
15 pF
GND
GPIO_34
10
ADCINA3
GPIO7/EPWM4B/SCIRXDA
Y1 GND
ABM3B-20.000MHZ
36
2
R16
10k
ADCINA7
GND
7
3
4.75k
1
TRST
GND
C23
1.2µF
6.3V
4
R15
33
GPIO_07
TDO
GND
11
R23
12
56
C27
3300pF
50V
13
GPIO12/TZ1 /SCITXDA
ADCINA1
GPIO16/SPISIMOA/TZ2
ADCINA0/VREFHI
GPIO17/SPISOMIA/TZ3
VDDA
GPIO18/SPICLKA/LINTXA/XCLKOUT
C24
2.2µF
10V
5
TRST
6
1
2
1
2
RESETn
TEST2
VDDIO
VSS
GPIO29/SCITXDA/SCLA/TZ3
GPIO30/CANRXA
GPIO31/CANTXA
ADCINB7
ADCINB6/COMP3B/AIO14
ADCINB4/COMP2B/AIO12
ADCINB3
SPISOMIA
29
SPICLKA
27
26
25
24
23
22
21
20
TPD1E10B06DPYR
J1
2
6
5
D6
1
D9
1
D11
1
19
2
18
1
ADCINB2/COMP1B/AIO10
2
ADCINB1
2
1
VSSA/VREFLO
1
D7
TPD1E10B06DPYR
D8
TPD1E10B06DPYR
D10
TPD1E10B06DPYR
D12
TPD1E10B06DPYR
D13
TPD1E10B06DPYR
D15
TPD1E10B06DPYR
17
TCK
2
16
TMS
4
1
15
3
30
1
J2
TDO
SPISIMOA
D5
GND
TDI
31
GPIO28/SCIRXDA/SDAA/TZ2
GND
2
GPIO_12
3.3V
14
1
32
TPD1E10B06DPYR
2
TPD1E10B06DPYR
nACK
4
2
TPD1E10B06DPYR
2
PG
3
28
ADCINA1
ADCINA2/COMP1A/AIO2
D14
1
TPD1E10B06DPYR
2
nEN
2
GND
GND
RX_A
1
3.3V
7
TX_A
3.3V
GND
8
851-43-006-20-001000
GND
GND
851-43-008-20-001000
Figure A-2. SAT0022 — Processor Section of the PLC Node
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Schematics
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Appendix A
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Vafe_15
TX_LINEPF
R1
Vafe_15
i High Current Trace
10k
GND
GND
R3
10k
R4
10k
R5
10k
GND
2
SPICLKA
3
SPISIMOA
4
SPISOMIA
5
SPISTEA
6
7
GPIO_12
9
GND
37
ZC_IN2
ZC_OUT1
39
CS
E_Rx_OUT
C4
0.012µF
50V
36
GND
35
3.3V
34
GND
33
C6
0.1µF
32
C7
C8
C9
0.012µF 0.012µF 0.012µF
31
3.3V
49
AVDD2
GND
SD
AGND2
INT
REF2
C15
IN2
(CIN)
3300pF50V
1000pF
50V
GND
30
29
28
GND
Rx_C1
Rx_C2
RX_LINEF
25
C14
680pF 50V
C16
330
(Bias Gen Cap)
GND
680pF 50V
i High Current Trace
i High Current Trace
D1
STPS1L40A
GND
26
10000pF
ADCINA1
GND
Rx_F_IN
27
24
22
C13
R9
i High Current Trace
K
23
21
C12
Vafe_15
Rx_F_OUT
Rx_PGA2_IN
Rx_PGA2_OUT
Rx_PGA1_OUT
20
REF1
19
PA_IN
Tx_F_OUT
18
13
GND
17
AGND1
16
AVDD1
Tx_F_IN2
Rx_PGA1_IN
Tx_F_IN1
12
TSENSE
Tx_PGA_OUT
10
3.3V
11
R27
100k
38
E_Rx_IN
C3
0.012µF
50V
1.0µF 10V
3.3V
Vafe_15
ZC_IN1
E_Tx_OUT
DOUT
15
GND
41
DIN
C2
0.1µF
50V
C11
GPIO_06
R8
33k
ZC_OUT2
E_Tx_IN
Tx_PGA_IN
R7
10k
8
40
SCLK
DAC
C1
0.1µF
50V
U3
AFE031
E_Tx_CLK
14
R6
10k
PA_GND2
DVDD
TPAD
GPIO_07
PA_GND1
PA_OUT2
42
43
PA_OUT1
46
45
47
44
PA_VS2
DGND
PA_VS1
1
R2
10k
PA_ISET
3.3V
Tx_FLAG
3.3V
Rx_FLAG
48
GND
A
PLC_MOD
C28
K
10µF50V
AC Coupling Stage for Power Line Communication
D2
STPS1L40A
A
R28
100k
SW_INPUT_LEGACY
LED_CONTROL_LEGACY
PLC_MOD
J4
J6
J3
2
2
1
3.3V
2
Vafe_15
2
1
24_IN
2
1
RX_LINEF
GND
2
1
GND
J7
GND
C17
1
D4
TPD1E10B06DPYR
1
D3
TPD1E10B06DPYR
10µF
50V
GND
Figure A-3. SAT0022 — AFE Section of the PLC Node
18
Schematics
TIDU168 – October 2013
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Copyright © 2013, Texas Instruments Incorporated
Appendix A
www.ti.com
3
4
Application Board for the PLC Node
SW1
KSC222J LFS
R31
10k
2
R33
10k
GND
R32
0.0
3
1
3.3V
Q1
BSS123W-7-F
100V
2
1
24_IN
D1
A
D2
K
A
HSMG-A100-K72J2
D3
K
A
HSMG-A100-K72J2
D4
K
A
HSMG-A100-K72J2
typ Forward Voltage 2.2V and test current 10mA
D5
A
D6
K
A
HSMG-A100-K72J2
J4
K
A
...
D*8
K
HSMG-A100-K72J2
A
D*9
K
HSMG-A100-K72J2
GND
110
HSMG-A100-K72J2
D7
HSMG-A100-K72J2
R34
33k
R35
K
A
R36 DNI
0.0
SW_INPUT_LEGACY
R38 DNI
0.0
LED_CONTROL_LEGACY
D*10
K
HSMG-A100-K72J2
R37
10
A
K
HSMG-A100-K72J2
R39
0.0
Vafe_15
3
1
Q2
2N7002E-T1-E3
60V
1
R40
10k
2
24_IN
2
SSHS-501-D-04-G-LF
GND
J6
1
3.3V
GND
2
SSHS-501-D-04-G-LF
J7
1
2
LED_CONTROL_LEGACY
SW_INPUT_LEGACY
SSHS-501-D-04-G-LF
Figure A-4. SAT0023 — Application Section of the PLC Node
TIDU168 – October 2013
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Schematics
Copyright © 2013, Texas Instruments Incorporated
19
Appendix A
www.ti.com
Power Suppy for TUSB3410
U1
USB_TO_SERIAL_5V
4
C1
0.1µF
USB_TO_SERIAL_5V
5
FB1
USB_TO_SERIAL_3_3V
2
VBUS_OUT
GND
1
IN
2
GND
OUT
1
PG
GND
TPS79733DCKR
R1
C3
10000pF
BK1608HS600-T
3
NC
C2
1µF
PG
100k
GND
PUR
R2
1.50k
J1
U2
R3
D_P
R4 33
4
5
USB_TO_SERIAL_3_3V
23
24
DR_N
22pF
C4
33
DR_P
22pF
C7
1µF
8
5
7
6
10
9
GND
D_N
3
C5
0548190519
11
EP
GND
SDA
GND
Y1
33pF 2
C8
USB_TO_SERIAL_3_3V GND
11
10
SCL
C6
GND
GND
ID
D+
DVBUS
VBUS
GND
6
7
GND
ID
2
EN
ACK
VBUSOUT
VBUSOUT
DD+
7
6
1
1
27
12MHz
GND
26
U3
TPD4S014DSQR
R10
15.0k
33pF
GND
C9
1µF
R15
15.0k
nRESET
9
R13
USB_TO_SERIAL_3_3V
DM
DP
TEST0
TEST1
X2
RESET
1
12
VREGEN
SUSPEND
WAKEUP
CLKOUT
4
C10
1µF
USB_TO_SERIAL_3_3V
USB_TO_SERIAL_3_3V
C12
C11
10000pF 1µF
R17
90.9k
VBUS_OUT
GND
3
25
R7
J2
5
R9
10k
R11
4
GND
R12
nACK
15.0k
0
3
D4
1
2
2
GND
2
R14
22
PG
0
D1
33
EP
6
GND
USB_TO_SERIAL_3_3V
15.0k
PUR
2
USB_TO_SERIAL_3_3V
15.0k R8
5
1
GND
D5
1
850-10-006-20-001000
2
2
VDD18
8
18
28
GND
GND
GND
VCC
VCC
1
330
21
14
15
16
13
20
DTR
DSR
DCD
RI/CP
CTS
RTS
D3
330
R6
19
SOUT/IR_SOUT
X1/CLKI
R5
17
SIN/IR_SIN
SCL
SDA
GND
GND
32
31
30
29
P3.0
P3.1
P3.3
P3.4
PUR
33.0k
nVREG
3
4
2
1
VBUS
3
1
R16
nVREG
nEN
R26
MMBD4148
C14 TUSB3410IRHB
C13
10000pF 1µF
0
GND
D6
1
2
10k
GND
GND
GND
nACK
R18
100k
D7
GND
1
2
GND
GND
GND
nEN
USB_TO_SERIAL_3_3V
USB_TO_SERIAL_3_3V
USB_TO_SERIAL_3_3V
R27
2.21k
R21
15.0k
R22
nRESET
D2
SML-P12YTT86
100
1
2
SKRKAEE010
U4
R23
SDA
C15
1µF
R19
1.50k
R20
1.50k
SW1
5
0
R24
SCL
0
USB_TO_SERIAL_3_3V
R25
15.0k
GND
C16
GND
6
7
8
SDA
VSS
SCL
E2
WC
E1
VCC
E0
4
3
2
1
M24128-BWMN6TP
GND
10000pF
GND
GND
Figure A-5. SAT0045 — USB to UART Interface Board for Host-to-Master PLC-Node Communication
20
Schematics
TIDU168 – October 2013
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Copyright © 2013, Texas Instruments Incorporated
Appendix A
www.ti.com
J1
J2
24_IN
1-1123724-2
1-1123724-2
1
2
1
2
24V Power i
24_IN
i
24V Power
J3
GND
4
3
24V Power i
2
GND
1
0877580416
24_IN
GND
24V POWER
D1
1
2
i
24V Power
1
2
1
3
103-12100-EV
R1
2
50.5k
2.2V
SML-LX0805SUGC-TR
SMAJ1
36V
SMAJ36A-13-F
GND
Base Board For the Master PLC Node
Figure A-6. SAT0029 — Base Board to Mount the Master PLC
J1
J2
24_IN
1-1123724-2
1-1123724-2
2
1
2
1
24_IN
24V Power i
i
24V Power
GND
J3
J4
4
4
3
24V Power i
3
24V Power i
GND
2
2
1
1
24_IN
0877580416
D1
S1
GND
1
2
i
24V Power
1
2
1
3
103-12100-EV
R1
2
D2
S2
1
50.5k
2.2V
SML-LX0805SUGC-TR
SMAJ1
36V
SMAJ36A-13-F
0877580416
24_IN
2
i
24V Power
1
2
GND
1
3
103-12100-EV
SMAJ3
36V
SMAJ36A-13-F
GND
J5
GND
J6
4
4
3
24V Power i
R2
2
50.5k
2.2V
SML-LX0805SUGC-TR
3
24V Power i
2
2
1
1
24_IN
24_IN
0877580416
GND
S3
i
24V Power
2
1
2
1
3
103-12100-EV
SMAJ2
36V
SMAJ36A-13-F
0877580416
D3
GND
S4
1
2
D4
1
R3
2
i
24V Power
50.5k
2.2V
SML-LX0805SUGC-TR
1
2
1
3
103-12100-EV
GND
SMAJ4
36V
SMAJ36A-13-F
2
R4
50.5k
2.2V
SML-LX0805SUGC-TR
GND
Base Board For the Slave PLC Nodes
Figure A-7. SAT0030 — Base Board to Mount the Slave PLC Nodes
Interface Board that connects to the 8 pin
connector (C2000 - processor) for JTAG
programming
J1
HD1
R2
0.0
1
4
3
6
R6
0.0 R8
R10
2
GROUND
0.0
R3
8
R5
5
8
7
10
9
0.0
TP2
TP3
R7
TMS
0.0
0.0
R12
TP4
0.0
12
11
14
13
TDO
R13
0.0
TP5
TDI
TSM-107-01-S-DV-P-TR
TSM-107-01-S-DV-P-TR-ND
6
0.0
TRST
5
TCK
0.0
4
R9
R11
7
R4
0.0
0.0 R14
3
2
1
0.0
ED8650-ND
850-10-050-20-001000
This board connects to the 8-pin connector (C200 processor) for JTAG.
Figure A-8. SAT0024 — JTAG Interface Board for Programming C2000
TIDU168 – October 2013
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Schematics
Copyright © 2013, Texas Instruments Incorporated
21
Appendix B
TIDU168 – October 2013
Bill of Materials
To download the bill of materials (BOM) for each board, see the design files at
www.ti.com/tool/24VDCPLCEVM. Figure B-1 shows the BOM for the SAT0022.
LINE
NO.
KS PART CUSTOMER QTY VALUE
NUMBER PART
NUMBER
DESIGNATORS
1
27513
B 14
2
0.012µF
2
27513
B 14
3
0.012µF
3
22444
B7
4
0.1µF
4
12420
B9
1
0.1µF
5
27514
B 14
1
1.0µF
6
11116
B1
1
10000pF
7
11296
B1
1
1000pF
8
11229
B1
2
15pF
9
11637
B2
2
3300pF
10
13093
B3
2
680pF
11
12509
C4
1
2.2µF
PKG/ CASE
T.COEFF/
PWR
TOL VOLT DESCRIPTION
RATED
DISTRIBUTOR
DIST P/N
MANUFACTURER
MNFR. PART #
LOT NO
C3, C4
0402
X7R
10
50V
Capacitors
Digi-Key
399-9949-1-ND
Murata
GRM155R71H123KA12D
K10000048010
C7, C8, C9
0402
X7R
10
50V
Capacitors
Digi-Key
399-9949-1-ND
Murata
GRM155R71H123KA12D
K10000048010
C1, C2, C19, C20
0402
X7R
10
50V
Capacitors
Digi-Key
445-5932-2-ND
Tdk Corporation
C1005X7R1H104K
K10000028604
C6
0402
X7R
10
16V
Capacitors
Digi-Key
445-4952-2-ND
Tdk Corporation
C1005X7R1C104K
K10000049921
C11
0402
X7S
10
10V
Capacitors
Digi-Key
445-9116-1-ND
Tdk Corporation
C1005X7S1A105K050BC
K10000048128
C13
0402
X7R
10
50V
Capacitors
Digi-Key
490-4516-2-ND
Murata Electronics North AmGRM155R71H103KA88D
C12
0402
X7R
10
50V
Capacitors
Digi-Key
445-1256-2-ND
Tdk Corporation
C1005X7R1H102K
C25, C26
0402
C0G
5
50V
Capacitors
Venkel
C0402COG500-150JNE
Venkel
C0402COG500-150JNE
OB6223AYV
C15, C27
0402
X7R
10
50V
Capacitors
Digi-Key
311-1034-2-ND
Venkel
C0402X7R500-332KNE
K10000034924
C14, C16
0402
C0G
5
50V
Capacitors
Digi-Key
490-3240-2-ND
Murata
GRM1555C1H681JA01D
K10000011519
C24
0603
X7R
10
10V
Capacitors
Digi-Key
445-5958-2-ND
Murata Electronics North AmGRM188R71A225KE15D
K10000049081
Capacitors
12
27515
C 17
3
1.2µF
C21, C22, C23
0805
X7R
10
6.3V
13
24690
E4
2
10µF
C17, C28
1206
X5R
10
50V
14
27535
U 179
1
TMX320F28035RSHS
U4
56-VFQFN
15
14220
M 14
11
10.0K
0402
1/10W
16
11016
M1
2
100K
R1, R2, R3, R4, R5, R6, R7, R11, R16,
R17, R32
R27, R28
0402
17
11322
M4
33.2K
R8
18
21035
M 24
19
28777
20
13137
21
24301
22
23
24
Digi-Key
399-4929-1-ND
Kemet
C0805C125K9RACTU
Capacitors
Digi-Key
445-5998-2-ND
Tdk Corporation
C3216X5R1H106K
K10000044076
Integrated Circuits
Mouser
595-TMS320F28035RSHT
Texas Instruments
TMX320F28035RSHS
K10000049505
1
Resistors
Digi-Key
P10.0KLTR-ND
Yageo America
ERJ-2RKF1002
K10000048777
1/16W
1
Resistors
Digi-Key
311-100KLRTR-ND
Yageo America
RC0402FR-07100KL
K10000045631
Resistors
Digi-Key
P33.2KLTR-ND
Panasonic - Ecg
ERJ-2RKF3322X
510283380
Resistors
Digi-Key
P330LTR-ND
Panasonic - Ecg
ERJ-2RKF3300X
K10000049592
Panasonic - Ecg
ERA-2AEB4751X
0402
1/16W
1
50V
1
330
R9
0402
±100ppm/°C
1
1/10W
2
4.75K
R14, R15
0402
1/16W
0.1
M 11
1
56.2
R23
0402
1/16W
1
X8
13
TPD1E10B06DPY
0402
27533
AE 41
2
STPS1L40A
D3, D4, D5, D6, D7, D8, D9, D10, D11,
D12, D13, D14, D15
D1, D2
27534
U 175
1
AFE031AIRGZT
U3
48-VQFN
27536
W 13
1
20.0000MHz
Y1
4-SMD 5mm x 3.2mm
25
20983-6
AM 78/LB 12 1
1 X 6 R/A
J1
26
20983-8
AM 78/LB 12 1
1 X 8 R/A
27
26194
AM 88
FW-50-01-L-D
1
4
K10000049918
K10000032586
Resistors
K10000045794
75V
Resistors
Digi-Key
P56.2LTR-ND
Panasonic - Ecg
ERJ-2RKF56R2X
7121255502
6.0V
Circuit Protection
Texas Instruments
TPD1E10B06DPYR
Texas Instruments
TPD1E10B06DPY
K10000042224
1A
40V
Discrete Semiconductor Products
Digi-Key
497-3753-1-ND
Stmicroelectronics
STPS1L40A
K10000048127
Integrated Circuits
Texas Instruments
AFE031AIRGZT
Texas Instruments
AFE031AIRGZT
K10000045657
-20°C ~ 70°C 20
18pF
Crystals
Digi-Key
535-9125-1-ND
Abracon Corporation
ABM3B-20.000MHZ-B2-T
K10000049524
0.05"
Connectors
Digi-Key
851-43-010-20-001000
Mill-Max
851-43-010-20-001000
K10000044132
J2
0.05"
Connectors
Digi-Key
851-43-010-20-001000
Mill-Max
851-43-010-20-001000
K10000044132
J3, J4, J6, J7
0.05"
Connectors
Samtec
FW-50-01-L-D-300-280
Samtec
FW-50-01-L-D-300-280
K10000041242
DO-214AC, SMA
Figure B-1. SAT0022 — BOM
22
Bill of Materials
TIDU168 – October 2013
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Appendix C
TIDU168 – October 2013
Layer Plots
To download the layer plots for each board, see the design files at www.ti.com/tool/24VDCPLCEVM.
Figure C-2, Figure C-2, and Figure C-3 show the layer plots for the SAT0021, SAT0022, and SAT0023
respectively.
Figure C-1. SAT0021 — Layer Plot
Figure C-2. SAT0022 — Layer Plot
Figure C-3. SAT0023 — Layer Plot
TIDU168 – October 2013
Submit Documentation Feedback
Layer Plots
Copyright © 2013, Texas Instruments Incorporated
23
Appendix D
TIDU168 – October 2013
Altium Project
To download the Altium project files for each board, see the design files at
www.ti.com/tool/24VDCPLCEVM. Figure D-1, Figure D-2, and Figure D-3 show the layout for the
SAT0021, SAT0022, and SAT0023 respectively.
Figure D-1. SAT0021 — Layout
Figure D-2. SAT0022 — Layout
24
Figure D-3. SAT0023 — Layout
Altium Project
TIDU168 – October 2013
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Copyright © 2013, Texas Instruments Incorporated
AFE031 High-Current Trace Layout
www.ti.com
D.1
AFE031 High-Current Trace Layout
In a typical power-line communications application, the AFE031 device dissipates 2 W of power when
transmitting into the low impedance of the AC line. This amount of power dissipation can increase the
junction temperature. An increase in junction temperature can lead to a thermal overload that results in
signal transmission interruptions if the proper thermal design of the PCB has not been performed. Proper
management of heat flow from the AFE031 device as well as good PCB design and construction are
required to ensure proper device temperature, maximize performance, and extend device operating life.
For a layout example of high-current traces see Figure D-4. To achieve lower thermal resistance, 2-oz
copper was used in the design as shown in Figure D-5.
NOTE: The AFE031 device has a power amplifier that requires high-current trace layout.
High Current Traces
35
Four-Layer PCB, PCB
2
Area = 4.32 in , 2 oz Cu
(Results are from thermal
simulations)
Thermal Resistance (°C/W)
33
31
29
27
25
23
21
19
17
15
0.5
1
1.5
2
2.5
Cu Thickness (oz)
Figure D-4. High-Current Traces
Figure D-5. AFE031 — Thermal Resistance as a
Function of Copper Thickness
See Section 2.5.1 for thermal performance data of the design when the application software is running.
TIDU168 – October 2013
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Altium Project
Copyright © 2013, Texas Instruments Incorporated
25
Appendix E
TIDU168 – October 2013
Gerber Files
To download the Gerber files for each board, see the design files at www.ti.com/tool/24VDCPLCEVM
26
Gerber Files
TIDU168 – October 2013
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Appendix F
TIDU168 – October 2013
Software Files
To download the software files for the reference design, see the design files at
www.ti.com/tool/24VDCPLCEVM
TIDU168 – October 2013
Submit Documentation Feedback
Software Files
Copyright © 2013, Texas Instruments Incorporated
27
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