IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
Software PLL Based Control Algorithm for Power Quality
Improvement in Distribution System
Abstract—This paper deals with a software phase locked loop (SPLL) based control algorithm for a
three phase distribution static compensator (DSTATCOM) for power quality improvement under
linear/nonlinear loads in a distribution system. In this control approach, amplitude of fundamental active
and reactive power components of load currents is extracted for estimation of reference source currents.
The DSTATCOM is modeled in the Matlab environment using Simulink and Sim Power System (SPS)
toolboxes. Matlab based developed model of DSTATCOM is used to simulate its performance. Simulated
performance of DSTATCOM is found satisfactory under time varying and unbalanced linear and
nonlinear consumer loads.
Keywords—Load balancing; Harmonic elimination; Reactive power compensation, SPLL; ZVR
I.
INTRODUCTION
A review on the classification of active power compensators and various control algorithms are presented to
select the optimum control strategies and power circuit configuration for their proper utilization in field
application [8]. Selection of DC link voltage, interfacing inductor and value of capacitor depends upon the
rating of VSC (Voltage Source Converter) based DSTATCOM [9, 10]. Prime requirements for desired
compensation are fast detection of distortion with high accuracy, fast processing of the reference signals and
high dynamic response of the controller [11-13]. For extraction of reference signals, many control algorithms
are reported in the available literature [14] such as nonlinear control algorithm [15], sinusoid-tracking algorithm
[16], SRF theory based control [17], digital signal processor based simplified current regulator [18], phasedictated sinusoid-tracking algorithm, extraction of non stationary sinusoidal and nonlinear time frequency
analysis [19-21], parallel neural networks based algorithm [22] and digital PLL scheme using modified
synchronous reference frame [23]. A PLL is a technique that synchronizes the frequency as well as phase of
output signal with respect to supply signal. PLL based control algorithms are referred as double-frequency and
amplitude compensation control technique to reduce the drawback of power based PLL [24], digital phaselocked-loop based control algorithm [25], multiple-complex coefficient-filter-based PLL [26], soft phase locked
loop algorithm for series active compensator [27-28] and software phase locked loop control algorithm [29-30].
Software PLL consists of two interconnected feedback loops. One loop controls the amplitude and the other
loop is used for the phase control. The SPLL (software phase locked loop) based control algorithm can estimate
the harmonics and reactive power component of currents instantaneously and also able to extract amplitude,
frequency and phase angle of the input signal even at weak supply signals. In the literature, software PLL based
control algorithm has been reported for single phase AC system for power factor correction [29].
In this paper, a signal processing control algorithm based on SPLL in time domain is used in three
phase distribution system for unity power factor (UPF) and zero voltage regulation (ZVR) modes of operation of
DSTATCOM for compensation of current related power quality problems such as reactive power component of
currents, harmonics currents and balancing of unbalanced loads. The proposed control approach based on SPLL
has the following features.
(a) It can estimate instantaneously active, reactive and harmonic power components of load currents and
adaptive with respect to frequency variation.
(b) Dynamics response of this control algorithm is fast in the application of harmonics compensation and load
unbalancing because delay in the estimation of reference signal is less.
(c) It provides fast response to sudden changes in the loads due to the tracking time of the phase locked loop.
(d) Due to simple structure, its implementation and processes in programmable devices like FPGAs and DSPs
are easy.
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
II.
DESIGN AND CHARACTERISTICS OF DSTATCOM
The schematic diagram of a DSTATCOM in a distribution system is shown in Fig. 1. The
DSTATCOM consists of a three-leg VSC and connected to a three phase distribution system with grid
impedance „ZS‟ supplying power to three phase loads. A three-phase VSC consists of six IGBTs (insulated gate
bipolar transistors) switches with anti parallel diodes.
Fig. 1. Schematic diagram of DSTATCOM
Three phase loads may be linear lagging power factor loads or unbalanced loads or nonlinear loads.
Interfacing inductors (Lf) are used at AC side of VSC for reducing ripples in compensating currents. A series
connected capacitor (Cf) and a resistor (Rf) are used as a ripple filter in parallel with the loads and the
compensator to reduce switching ripples at the PCC voltage injected by switching of DSTATCOM. The
compensating currents (iCabc) are injected by the DSTATCOM to cancel the reactive power component of
currents, harmonics currents of the polluted loads. Main functions of DSTATCOM are compensation of reactive
power component of load currents, harmonics currents suppression and load balancing in the distribution
system. For a considered load of 26 kVA, the compensator data are given in Appendix. The rating of the VSC
for power quality improvement is found to be 12 kVA (20% higher than reactive current from rated value).
III.
PROPOSED CONTROL ALGORITHM
Fig. 2 shows the block diagram of a control algorithm based on SPLL in time domain for extraction of
reference source currents. Basic equations used for estimation of different control signals of control algorithm
are given below.
A. Estimation of Unit Voltage Templates
The in phase voltage unit templates are estimated using phase voltage (va, vb, vc) at PCC as [17],
And the quadrature unit template are given as,
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
B. Estimation of Amplitude of Load Currents
The amplitude of fundamental component of load currents is estimated by using amplitude loop of
SPLL functions in each phase. SPLL used in phase „a‟ receives the input signal as the load current iL and
estimates its amplitude [29]. As block diagram of control algorithm is shown in Fig. 2(a), the normalized output
signal is used in the amplitude loop to obtain the amplitude error signal E a. Input signal and the output
normalized signal are squared so that when the phase are tracked amplitude error signal (Ea) can be estimated.
Ea passed through proportional-integral (PI) regulator with the loop filter giving the filtered signal e1, which has
attenuated the second order harmonic.
Fig. 2(a). Generation of reference currents using SPLL based control algorithm
The filtered DC component of e1 is used to correct the amplitude around the nominal amplitude (1p.u.).
This signal is normalized with correction factor E1= (1+e1) as shown in Fig. 2(a). The low pass filter in a
proportional regulator (kp) improves the response of a simple PI controller because it suppresses second order
harmonic component of Ea and therefore it reduces the ripple in E1. The inverse of square root of E1 provides the
amplitude of phase „a‟ load current (|ILa|) and normalized signal is obtained by multiplication of input signal and
square root of e1 signal with the help of frequency average section which is inbuilt in SPLL. The input of
frequency average block is multiplied by the normal frequency gain and integrated with respect to time. After
integration, its output is subtracted from its one cycle delay signal and feed back with input signal. Used
frequency average block is able to reduce the ripple component in the amplitude signal because its integrator
attenuates the high frequency components and also suppress the harmonic component of the applied signal.
Similar way other phases amplitude of fundamental load currents ILb and ILc are also extracted.
C. Estimation of sin and cos Component of Load Currents
Sinusoidal tracking algorithm is used for extraction of sin θLa and cos θLa component of the load currents
[19]. Block diagram of this algorithm is shown in Fig. 2 (b). Difference between iLa and iLo is the total distortion
in the load currents and it is denoted by ier. Internal parameters k1, k2 k3 and ωo are positive real value. The
selection process of internal constants is described in [20-21] and these constants decide the behavior of the
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
algorithm in terms of convergence speed and accuracy. Values of the internal parameters k1, k2 and k3 are
considered as 4, 1, and 1 for this study. It is observed that the variations in sin θLa and cos θLa components of
load current are effectively tracked within couple of cycles. If the value of internal constants increases then
tracking cycle reduces. The advantages of this algorithm are high estimation accuracy, low computational time
which is necessary in most of practical applications. Similarly, phase „b‟ and „c‟ load currents sin θ and cos θ
components (sin θLb, cos θLb and sin θLc, cos θLc) are also estimated respectively.
D. Estimation of Amplitude of Active and Reactive Power Components of load currents
An amplitude of active and reactive powers component of three phase load currents can be estimated after
extraction of amplitude of phase „a‟ load current |ILa|, phase „b‟ load current |ILb|, phase „c‟ load current |ILc|
and sinθ and cosθ component of three phase load currents. Procedure of estimation is as,
Amplitude of Phase „a‟ active current component is as,
Amplitude of Phase „a‟ reactive current component is as,
Similarly, amplitude of phase „b‟ and „c‟ active (ILpb, ILpc) and reactive (ILqb, ILqc) power components of
currents are also estimated.
E. Estimation of Average Amplitude of Active and Reactive Power Components of Load Currents
The average fundamental amplitude of active and reactive power components of three phase load
currents are estimated using the amplitude of load active and reactive power components of per phase current.
An average value for extraction of three phase reference source currents is as,
F. Unity Power Factor Mode of DSTATCOM
The control algorithm for harmonic elimination and reactive power compensation in the operation of
UPF mode of DSTATCOM considers that the source must deliver the average value of the active power
component of the load currents along with the active power component of current for maintaining the DC link
(Icp) of the compensator. Difference between reference DC link voltage and sensed DC link of the DSTATCOM
is the error in DC link voltage (vdce) of the DSTATCOM. The output of DC link voltage PI regulator for
maintaining DC link voltage of the DSTATCOM of the nth sampling instant is expressed as,
where Icp(n) considered as the active power component of source current for maintaining the DC link of the
DSTATCOM and Kpd and Kid are the proportional and integral gain constants of the DC link PI voltage
regulator.
Total amplitude of active power component of the reference source current is computed as the addition
of active current requirement for maintaining DC link of the DSTATCOM and average magnitude of load active
currents as,
G. Zero Voltage Regulation Mode of DSTATCOM
The control algorithm of DSTATCOM for ZVR mode of operation considers that the source must
deliver active power component of the reference source current (Ispt) along with the difference of load reactive
power current (ILqA) and the output reactive current component obtained from the voltage PI regulator (Icq) used
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
for regulating the voltage at PCC. The amplitude of PCC terminal voltage (vt) is controlled to reference voltage
(vt*) using the PI regulator. The output of voltage PI regulator is considered as the reactive component of
current (Icq) for zero-voltage regulation of AC voltage at PCC. This value at the nth sampling instant is
expressed as,
where ve is difference between amplitude of reference PCC voltage (vt*) and sensed PCC voltage (vt).
Kpq and Kiq are the proportional and integral gains of the PI regulator over the PCC voltage.
Total amplitude of reactive power component of the reference source current is computed as a
difference of output of voltage PI regulator and average load reactive currents as,
H. Estimation of Source Reference Currents and Generation of IGBTs Gating Pulses
Three phase reference source active power components of currents are estimated using an amplitude of
source active current (Ispt) and in phase unit voltage templates (uap, ubp, ucp) as,
Similarly, reference source reactive power components of current components are estimated using
amplitude of source reactive current (Isqt) and quadrature unit voltage templates (uaq, ubq, ucq) as,
Total reference source currents are obtained after addition of reference source active and reactive
current components as
The current errors are estimated from three reference phase source currents (i*sa, i*sb, i*sc) with
comparison of sensed source currents (isa, isb, isc). Using PI current regulator, these current errors are amplified
and output of PI current controllers are compared with triangular wave carrier signal of 10 kHz to generate
gating pulses for IGBTs of VSC.
IV.
RESULTS AND DISCUSSION
A model of a DSTATCOM in MATLAB environment with SIMULINK and Sim Power System (SPS)
toolboxes is developed for compensation of three phase linear and nonlinear loads. The performance of the
software PLL based control algorithm for three-phase DSTATCOM is studied for PFC and ZVR modes of
operation under linear and nonlinear loads. The performance of DSTATCOM is analyzed under time varying
loads and the results are discussed in the following sections.
A. Performance of DSTATCOM in UPF Mode
The dynamic performance of a three-leg VSC based DSTATCOM for UPF mode with linear lagging
power factor load is shown in Fig. 4. Performance of DSTATCOM is analyzed on the bases of phase voltages at
PCC (vabc), balanced source currents (is), load currents (iLa, iLb, iLc), compensator currents (iCa, iCb, iCc), and DC
link voltage (vdc) which are shown under a varying load (at t=1.75 s to 1.85 s) conditions. This shows the
satisfactory operation of DSTATCOM for reactive power compensation at load injection and load removal.
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
B. Performance of DSTATCOM in ZVR Mode
In ZVR mode, the amplitude of PCC voltage is regulated to the reference amplitude by injecting extra
reactive power at PCC. Fig. 3 shows the dynamic performance of the DSTATCOM used for reactive power
compensation required for voltage regulation and load balancing under linear loads (at t=1.75 s to 1.85 s). The
performance of DSTATCOM is analyzed on the bases of PCC phase voltages (vabc),balanced source currents
(is), load currents (iLa, iLb, iLc), compensator currents (iCa, iCb, iCc), amplitude of voltages at PCC (vt) and DC link
voltage (vdc) under time varying linear loads.
The performance of DSTATCOM is also studied under voltage fed type nonlinear loads. Its Dynamic
performance and waveform of phase „a‟ voltage at PCC (vsa), source current (isa) and load current (iLa) are
shown in Fig.4.
Fig. 3. Dynamic performance of DSTATCOM under varying linear loads in ZVR mode
Fig. 4. Dynamic performance of DSTATCOM under varying voltage fed type nonlinear loads in ZVR mode
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
V.
Simulation Model and Results
Discre te ,
Ts = 5e -006 s.
powe rgui
Vabc_s
Three-Phase
Series RLC Load
Vabc_L
A
a
A
B
b
B
b
B
Iabc_s
C
c
C
c
C
Iabc_L
b
c
a
a
A
C
B
A
Vabc_c
Iabc_s
Iabc_c
Gate
signal
rm s
[ILn]
RMS
signal
rm s
B
C
Gate
A
[ISn]
Subsystem4
Uc
Uc
RMS1
Va
Vb
-
Ua
Ua
Vabc_s
+
Ub
Ub
Vt
Vt
Wa
Wa
Scope7
Wb
Wb
Vc
Wc
Wc
+
v
-
Unit voltage
Template Generator
Vdc
Scope3
Scope4
Fo= 45Hz
N= 2
Vdc
PID
Iabc_s
PID Controller
Ua
700
Ub
Constant
Uc
Fo= 10Hz
N= 2
1/3
Add2
Signal(s)
Add3
Out1
iLf a
In1
Pulse s
PWM Generator
Gain
Out2
Out1
Iabc_L
iLabc
iLf b
In1
iLf c
In1
Scope6
Out2
Out1
1/3
Subsystem
Add4
Scope5
Fo= 10Hz
N= 2
Out2
Scope2
Wa
Gain1
Wb
Scope8
Scope9
Wc
-C-
PID
Constant3
PID Controller1
a
Vabc_L
From11
b
Vtm
Scope10
Fo= 16Hz
N= 2
c
Fig.5. Simulation model for proposed circuit
500
0
-500
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.25
1.3
1.35
1.4
Time
1.45
1.5
1.55
1.6
500
0
-500
1.2
100
0
-100
1.2
200
100
0
-100
1.2
Fig.6. Dynamic performance of Source voltage (V sabc), Load voltage (VLabc), Source currents (Isabc) and Load
Current (ILabc) for linear load in UPF Mode
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B.Srikanth & K.Naresh Kumar
Gate
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
Fig.7. Dynamic performance of Source currents (Isabc), Controller voltage (V cabc), and Controller current (Icabc)
for linear load in ZVR Mode
500
0
-500
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.25
1.3
1.35
1.4
Time
1.45
1.5
1.55
1.6
500
0
-500
1.2
50
0
-50
1.2
50
0
-50
1.2
Fig.8. Dynamic performance of Source voltage (Vsabc), Load voltage (VLabc), Source currents (Isabc) and Load
Current (ILabc) for non-linear load in UPF Mode
Fig.9. Dynamic performance of Source currents (Isabc), Controller voltage (V cabc), and Controller current (Icabc)
for non linear load in ZVR Mode
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B.Srikanth & K.Naresh Kumar
IOJETR TRANSACTIONS ON ALTERNATE ENERGY SOURCES
IOJETR. Trans. Power. Engg 2000; 18:327–343
Published online 30 October 2014
VI.
CONCLUSIONS
The proposed control algorithm based on SPLL of three-phase DSTATCOM has been found to provide
acceptable performance characteristics in UPF as well as ZVR modes of operation. The performance of
DSTATCOM has been observed satisfactory for reactive power compensation load balancing and harmonic
elimination under linear and voltage fed type nonlinear loads. Self supporting DC link voltage of the
DSTATCOM has also been regulated without any overshoot to rated value in dynamic conditions.
APPENDIX
AC supply: 3-Phase, 415 V (L-L), 50Hz; Source Impedance: Rs = 0.07 Ω, Ls = 2.2 mH; Loads: (1)
Linear: 24 kW and 10 kVAR (lagging power factor), (2) Non-linear: Three phase full bridge uncontrolled
rectifier with parallel connected R = 11 Ω and C = 125μF elements; Ripple filter: R f = 5 Ω, Cf = 7μF; DC link
capacitance: 5500μF; Reference DC link voltage: 700 V; Gains of PI regulator for DC link voltage: Kpd = 2.12,
Kid = 1.05; Gains of AC bus voltage PI regulator: Kpq = 0.13, Kiq = 0.7; Sampling time(ts) = 10μs, Switching
frequency (fs) = 10 kHz
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