LTI-EPLL Based Control Algorithm
For Solar PV Power Generating System
Bhim Singh and Shailendra Dwivedi
Department of Electrical Engineering, Indian Institute of Technology Delhi, New Delhi-110016, India
Emails: bsingh@ee.iitd.ac.in, er.dwivedi88@gmail.com
Index Term- Solar PV Array, Linear Time Invariant
Enhance Phase Locked Loop (LTI-EPLL), Grid
Integration, Power Quality.
I. INTRODUCTION
The use of conventional sources of energy results in
global warming that affects the whole world. It is
realized on the burning of fossil fuels that produce
harmful gases which affects the living organism. Now a
days large amount of electrical power is generated
through the use of conventional technology. Hence, it is
necessary to use some alternative sources of energy
(solar, wind, etc) [1]. Currently very less amount of
electrical power is generated through alternative sources
of energy so an increased focus is required to increase
the amount of electricity produced in this natural way.
Solar photovoltaic (PV) power generating system is
popular technology to overcome the power quality and
energy problems by integrating clean power to AC grid
with an improved power quality [2]. A maximum power
from solar array is attained through MPPT algorithm by
using a DC-DC boost converter. Presently, the large
number of algorithms are proposed by the researchers to
track the MPPT [3], [4]. In this paper, perturb and
observe based control algorithm is used to extract the
maximum power from the solar array.
Due to presence of nonlinear loads, power feeding to
the grid is not clean. To feed the clean power to the grid,
a power conditioner is required. In proposed system,
VSC (Voltage Source Converter) is working as a power
conditioner and LTI-EPLL (Linear Time InvariantEnhanced phase Locked Loop) based control algorithm
is employed to control this VSC. Evolution of different
algorithms and classification is discussed by many
researchers [5-8]. To solve the power quality problems
of the grid interface SPV system, a precise and quick
response of reference signal is required in the presence
of distorted load current. As LTI-EPLL based control
algorithm has an input-output. So it can be represented
in transfer function form. Possessing a transfer function
description is very easy for design and development of
proposed control algorithm. There are some issues with
general PLL and other PLL structures like stability
problem, their nonlinearity structure, and dependency on
the input signal. These issues become noticeable when
PLL structures are included in the enormous closed loop
systems.
II. DESIGN OF PROPOSED SYSTEM
The design of proposed 30 kW solar PV grid
interfaced power generating system as shown in Fig. 1,
is given in terms of solar PV array, DC-DC boost
converter, DC bus capacitor and interfacing inductors as
follows,
Boost Converter
ipv
Voltage Source Converter
S1
S3
S5
R-C
Filter
Lb
Solar PV
Array
Abstract-This paper deals with a double stage grid
integrated solar photovoltaic (SPV) power generating
system employing linear time invariant enhanced
phase locked loop (LTI-EPLL) based control
algorithm. Proposed system consists of solar PV
array, DC-DC boost converter, DC-AC voltage
source converter (VSC) and three-phase, 415V, 50Hz
distribution system. There are two stages in this
system. First stage is a DC-DC conversion and second
stage is a DC-AC conversion. For better utilization of
solar PV array and maximize the solar PV energy
extraction, perturb and observe based control
algorithm is employed. Proposed system not only
feeds the power to the grid, moreover it includes the
features of power factor correction, harmonics
elimination, load balancing and reactive power
compensation of three phase distribution system by
using LTI-EPLL based control algorithm. Proposed
system is modeled and its performance is simulated
in MALAB/SIMLINK platform and results are
shown to validate the design and control of proposed
SPV system under nonlinear loads.
vpv
A
Lfa
iina
Cdc
B
S4
S6
iinb
C
S2
isb
vsb
vsc
iinc
Lfc
iLa iLb iLc
ipv
MPPT
Control
isa
vsa
Lfb
S1-S6
Linear/non
linear loads
LTI-EPLL Based
Control Algorithm
Fig.1System Configuration
isc
Grid
A. Design of Solar PV Array
The proposed system is designed for the peak power
capacity of 30 kW rated at 415 V, 50 Hz ac grid.
TABLE-I
DESIGN OF SOLAR PV ARRAY
PV Module
Short circuit current (Isc)
3.8A
Open circuit voltage (Vocn)
21 V
Voltage at MPP, Vmpp
0.85*21=17 V
Current at MPP, Impp
0.85*3.8=3.2 A
700V
Power at MPP, Pmpp
30 kW
Thus the array of 30 kW peak power capacity is
designed with 13 modules in parallel and 34 modules in
series with an PV array of 13*34 modules.
B. Design of DC-DC Boost Converter
The ripple current for inductor at D = 0.2 is given as,
V D
595*0.2
(1)
Lb  MPP 
 3.93 mH
I1 f sw (3.025*10000)
where ΔI1 is input current ripple, and it is considered as
6 % of DC-DC boost converter inductor current I1 (PMPP/
VMPP) = 50.42 A. Thus a calculated value of ΔI1 is 3.025
A.
Thus the inductance (Lb) value is selected as 3.93 mH.
Vdc
Selection of DC Capacitor Voltage
The design of DC link voltage Vdc is given as,
 = 2
3m
= 713.27  700 V
2 * 415
3 *0.95
I1 
Pmpp
3 * VLL

30000
( Pdc / Vdc )
3 * 415
 2*  * v 
dcrip
Number of parallel module Imp=np*Isc
(np)
np=13 Modules
2VLL
The grid current is calculated as,
Cdc 
Number of series module ns=700/21=34 Modules
(ns)
2
=
(3)
 41.73 A
(4)
D. Design of DC bus Capacitor
The DC bus capacitor value is estimated as,
Current at MPP, Impp= Pmpp/ Imp=30000/(0.85*700)
Vmpp
=50.42 A
C.
3mVdc
3 *0.95*700

 3.83 mH
12hf s I1 12*1.2*104 *(0.05* 41.73)
Considering, ∆I1, = 5% of input current, fs = 10 kHz.
Here h is overloading factor which is taken as 1.2. The
Lf from (3) is calculated as 3.83 mH.
Solar PV Array
Voltage at MPP, Vmpp
Lf 

where VLL is the VSC AC line voltage, m is modulation
index.
A. Selection of AC Inductor
The AC inductor (Lf ) value is calculated on the basis
that current ripple ∆I1, switching frequency fs, Vdc and it
is given as,
(30*103 / 700)
= 3250.7 F
 2*314*0.03*700 
(5)
where Id is the DC bus current of VSC, ω is angular
frequency and vdcrip is % ripple voltage considered as 3%
of Vdc.
Hence estimated value of DC bus capacitor Cdc is 3250.7
µF and it is selected as 4000 µF.
III. CONTROL ALGORITHMS
There are mainly two stages of proposed SPV system.
First stage is used to extract the maximum power from
SPV array by using DC-DC boost converter and second
stage is used to control a grid interfaced VSC which is
also operating as a shunt active filter. The details of
control algorithms are as follows.
A. MPPT Control
There are so many algorithms to track the MPP. Some
are simple which are based on current or voltage
feedback and some are reasonably complicated. P&O
(Perturb and Observe) is simple as compared to other
MPPT algorithms. According to the structure of MPPT,
the required parameters are voltage and current feedback
signals. The maximum power point is obtained when
dPpv/dVpv=0, the slope of the dPpv/dVpv=0 can be
calculated by output voltage and output current. The
output of the MPPT block is duty ratio. Moreover, it can
be given as,
dPpv
(2)
=
dV pv
(n) 
Ppv (n)  Ppv (n  1 )
V pv (n)  V pv (n  1 )
,
(6)
where Ppv (n)  V pv (n) I pv (n)
B. Control of VSC
Figs.2 shows the control algorithm for extraction of the
fundamental component of load currents and estimation
of in-phase and quadrature voltage templates. These
fundamental components are used to extract active and
reactive power components of load currents. These real
and reactive components of load currents are used to
estimate reference grid currents. Three phase sensed
voltages (vsa, vsb, vsc), load currents (iLa, iLb, iLc), and Vdc of
VSC are main parameters of the control algorithm.
The in phase voltage templates are estimated as follows
[9],
wpa 
v
vsa
v
, wpb  sb , wpc  sc
Vt
Vt
Vt
(7)
The quadrature voltage templates are estimated as
follows,
wqa  
wqc 
wpb
3
3wpa
2 3

wpc

wpb
3
2 3
, wqb 

3wpa
2 3

wpb
2 3

wpc
2 3
,
wpc
2 3
(8)
Amplitude of PCC voltage (Vt) is estimated as,
V 
t
2
2
2
{(2 / 3)(vsa  vsb  vsc )}
(9)
This Vt is passed through the LPF to eliminate the
negative sequence voltage from PCC voltage and to
achieve the fundamental component of positive sequence
PCC voltage.
The LTI-EPLL algorithm is having fully LTI structure
that is constituted by an input-output transfer function.
This type of configuration is not available for any other
PLL structure. This has revealed the fact that LTI-EPLL
structure is equivalent to band pass filter. This type of
algorithm is very useful where PLL is involved.
The input and output of the LTI-EPLL blocks are
sensed load current and extracted fundamental load
current. The transfer function of LTI-EPLL algorithm is
as follows,
iLfa (s)
( G1s )

iLa (s) (s 2  G2 s  n 2 )
(10)
where G1 and G2 are the gains which play an important
role to control the transient and steady state behavior of
LTI-EPLL and makes the fundamental load current
sinusoidal. The values of these gains are 20. The transfer
function from iLa to iLfa is having unity gain and zero
phase shift at the center frequency and zero gain at zero
frequency. The realization of LTI-EPLL algorithm
reveals high structural robustness with respect to EPLL
algorithm.
State space representation of load current is as follows,
diL3
 G1 * iL1 * sin(iL7 )
dt
diL 7
cos( iL 7 )
 n  iL1 * G2 *
dt
iL3
(11)
(12)
Where ωn is the natural frequency and iL1, iL2, iL3, iL4, iL5,
iL6 and iL7 are the components of load current.
So by using these equations fundamental component of
phase „a‟ load current is extracted. Similarly fundamental
components of load currents of phase „b‟ and „c‟ (ifLb,ifLc)
are extracted.
To estimate the fundamental active component of load
current of phase „a‟, sample and hold logic is employed
to sample the analogous fundamental active component
of load current and store its value for some length of
time. The output of zero crossing detector is used for the
triggering to this block. A quadrature template (wqa) is
used as an input to the zero crossing detector which is
900 apart from the in phase template (wpa). The output
signal of the sample and hold circuit is considered as
fundamental active component of phase „a‟ load currents
(iLa, iLb, and iLc). Correspondingly, fundamental active
components of phase „b‟ and „c‟ load currents are
extracted.
For extracting fundamental reactive component of
load current of phase „a‟, another sample and hold logic
is used and in phase template is used as an input for the
another zero crossing detector which provides the
triggering pulses to the sample and hold logic. The
output of this sample and hold logic is the fundamental
reactive component of phase „a‟ load current. Similarly
fundamental reactive components of phase „b‟ and „c‟
(iLqb, and iLqc) are estimated.
The magnitude of
fundamental active and reactive power components is
passed through the absolute block. An average value of
magnitudes is estimated for load balancing and also uses
to extract the 3-phase grid currents. Magnitude of active
component is estimated as,
I pLA 
i pLa  i pLb  i pLc
3
(13)
Similarly, reactive component (ILqA) can be estimated as,
I qLA 
iqLa  iqLb  iqLc
3
(14)
To estimate the active power component the reference
DC link voltage v*dc and DC link voltage is compared.
This error voltage is given to the PI regulator which
maintains the dc bus voltage as,
vdcer  v*dc  vdc
(15)
The output of PI regulator is represented as Iloss and the
active current component is represented as I*p which is
given as,
I * p  I pLA  I loss
(16)
Thereafter, in phase components or active power
components of reference instantaneous grid currents in
phase of PCC voltages are calculated as,
i* psa  I * p * w pa , i* psb  I * p * wpb , i* psc  I * p * wpc
(17)
vdc
LPF
PI Regulator
vdc*
Signal Extraction of phase „a‟
iLa
iL1
G1
×
iL4
iL2
ʃ
iL3
ωn
iL5
G2
sin
iL7
Hit
crossing
wqa
S&H
u i
pLa
iloss
+
+
+
+
+
1/3
iPLavg
ʃ
S&H
Hit
crossing
u
iqLa
+
+
+
wpa
1/3
Iqq
PI
iLb
Signal Extraction of phase „b‟
iLc
Signal Extraction of phase „c‟
The terminal voltage magnitude (Vt) is calculated in (9)
and the reference terminal voltage amplitude value (Vref*)
are compared. The voltage error is estimated as,
ver  V *tref  Vt
(18)
This error is given to the PI regulator which gives
reactive component of VSC current (Iqq), and grid
reactive component of current is estimated as,
(19)
The reference instantaneous quadrature components of
grid currents are calculated as,
qq
i*qsa  I *q * wpc , i*qsb  I *q * wpb , i*qsc  I *q * wpc
(20)
The reference currents can be generated by using (17)
and (20) as,
i*sa  i* psa  i*qsa , i*sb  i* psb  i*qsb , i*sc  i* psc  i*qsc
(21)
By comparing sensed grid currents and these reference
currents, an error is generated which is given to the
hysteresis controller to generate the gating pulses for
VSC.
C. Comaprison and Stability Analysis of EPLL and LTIEPLL Algorithms
The stability analysis of the EPLL and LTI-EPLL
algorithm is shown in Fig.3. From the Bode plot, it is
observed that LTI-EPLL algorithm provides near to
unity gain of fundamental component of load current.
While in EPLL algorithm, a low attenuation is provided
for all other frequecy component of load current. Hence
output of the LTI-EPLL algorithm is considered that the
fundamental component of load current is in phase with
+
*
+ isa
×
wpc
×
+
+
+
×
isb *
wqa
wqb
wqc
Hysteresis
controller
isa
isb
isc
Gating pulses for VSC
×
+
*
+ isc
×
Vt*
Vt
vsa
vsb
vsc
Fig.2 Control algorithm for proposed system
×
wpb
iLfa
cos
iL6
I *q   I qLA  I
iPLnet
wpa
Determination of Terminal
Voltage and unit templates
wqa
wqb
wpa
wpb
wpc
wqc
the actual load current.
Extra Gain margin by
EPLL Algorithm
LTI-EPLL Algorithm
EPLL Algorithm
Extra Phase Margin
by EPLL Algorithm
Fig.3 Bode plot of EPLL and proposed LTI-EPLL Algorithms
IV.
RESULTS AND DISCUSSION
The response of solar PV power generating system is
simulated by using perturb and observe method for
tracking the MPPT and LTI-EPLL algorithm for
improving the power quality of the proposed system
under linear and nonlinear loads.
The system response has been achieved as grid
voltages (vsa, vsb, vsc), grid currents (isa, isb, isc), DC bus
voltage (vdc), load currents (iLa, iLb, iLc), active power (P),
reactive power (Q) and VSC currents (ic). Here solar PV
array voltage vpv, solar PV array power (Ppv) and current
as ipv respectively. All the responses of the proposed
system is observed as follows,
A. Various Intermediate Signals
Fig.4 shows the intermediate signals iL1, iL2, iL3, ifLa, ipLa,
iavg and iref under sudden removal of load on phase „a‟. It
can be observed under load perturbation, all extracted
components of load current are settled in the few cycles.
However, it does not affect the dynamic response of the
system due to fast action of PI regulator. As the load is
removed then the magnitudes of ifLa, ipLa, and iavg
components are also changed but at the load removal,
reference grid currents are increased as the grid power is
increased.
decreased to 500 W/m2 then corresponding magnitudes
of the grid currents are also decreased. It is realized from
0.4 s to 0.45 s. The response of the proposed system is
satisfactory under different insolation.
Fig.5 Steady state response of proposed system with nonlinear
load
Fig.4 Various Intermediate Signals
B. Steady State and Dynamic Responses of Proposed
System Under Nonlinear Loads
Fig.5 shows simulated results for steady state operation
under nonlinear loads. It is realized that grid currents are
sinusoidal while the load currents are nonsinusoidal. The
compensator currents contain both harmonics current and
current drawn from the solar PV array. The DC link
voltage is also maintained to its reference value.
Fig.6 shows the simulated results of proposed system
under unbalanced nonlinear loads. It can be observed that
grid currents and grid voltages are balanced and
sinusoidal. For realizing the unbalanced operation phase
„a‟ load is removed. Under this condition, the total power
consumed by the load is decreased and total power
feeding to the grid is increased which can be observed in
Figs.7. Harmonic spectra of vsa, isa, and iLa, are observed
as 1.56%, 3.26% and 22.91% in Fig.7. This is meeting an
IEEE-519 standard [10]. So VSC not only balances the
currents it also mitigates the harmonics of the load
current.
C. Performances of Solar PV System under Different
Insolation
The performance of solar PV system under different
insolation is shown in Fig.8. It is realized that when the
value of solar insolation is 1000 W/m2 then the
magnitudes of the grid currents are maintained and it is
realized from 0.35 s to 0.4 s. As the value of insolation is
Fig. 6 Dynamic response of proposed system under nonlinear
load
V. CONCLUSIONS
A grid integration of solar PV power generating system
has been proposed with LTI-EPLL algorithm. LTI-EPLL
algorithm has been used for extraction of fundamental
active and reactive load currents to generate the
switching pulses for three-phase VSC. Based on
simulation results, it has been concluded that proposed
algorithm is able to shape grid currents sinusoidal and
also maintained power factor near to unity. Moreover,
under nonlinear loads the THD of the grid current in the
proposed system is also found within the limit of an
IEEE-519 standard.
(a)
(b)
(c)
Fig. 7 Harmonic spectra of proposed system (a) grid voltage
(b) grid current and (c) load current.
Fig.8 Performance of solar PV system under different
insolation with non linear load
APPENDICES
A. Solar PV array Data
Voc = 21 V, Isc = 3.8 A, Vmpp = 17 V, Impp = 3.2 A. No. of
series cell in each module Ns = 36, the open circuit
voltage of one cell is 0.5V to 0.6V, ns = 34, np = 13
current temperature coefficient Ki = 0.0032 A/K, voltage
temperature coefficient Kv = -0.1230 V/K,.
B. DC-DC Boost Converter design Parameters
Lb = 3.93 mH, D = 0.15, Fs = 10 kHz.
C. Parameters for three-phase VSC
DC link voltage is 700 V, grid voltage = 415 V,
frequency = 50 Hz, Switching frequency (fs) = 10 kHz,
DC link capacitor = 4000 μF, interfacing inductor 3.83
mH, DC voltage controller: Kpd = 0.023, Kid = 1.2, AC
voltage PI controller: Kvp=0.01, Kip=0.015, line
impedance: Ls = 0.4 mH, Rs = 0.02 Ω, nonlinear load:
Diode bridge rectifier with L = 100 μH, R = 15 Ω and
ripple filter: Cf = 12 μF, Rf =6 Ω.
ACKNOWLEDGMENT
Authors are extremely grateful to Department of Science
and Technology (DST), Govt. of India, for aiding this
work under Grant Number: RP02583.
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