Low Conversion Ratio VRM Design
Angel V. Peterchev
Seth R. Sanders
Department of Electrical Engineering and Computer Science
University of California, Berkeley
Abstract— This paper discusses the design considerations for low conversion ratio voltage regulation modules (VRM’s) for the next generation
of microprocessors, focusing on the handling of large, high-slew-rate current transients. A converter topology which deploys an inductive clamp
to handle the unloading transients, while operating at a modest switching
frequency, low current ripple, and low power dissipation, is discussed.
The clamp response is analyzed, and simulation results for a 1 MHz,
100 A, 12-to-1V VRM are presented.
T
TABLE I
N EXT GENERATION MICROPROCESSOR VRM SPECIFICATIONS *
Vin
Vref
Vo;max
Io;max
dIo =dt
Td
I. I NTRODUCTION
input voltage
reference voltage
regulation tolerance
load current
current slew rate
regulator response time
> 12 V
<1V
< 50 mV
> 100 A
> 350 A/s
< 200 ns
(*) Source: reference [1]
HE projected specifications for next generation microprocessor VRM’s [1] are summarized in Table I. The very
low conversion ratio (< = ), the high load current and current slew rate, and the tight output regulation tolerance present
a challenge to VRM design calling for new design solutions.
Various modifications to the basic multi-phase buck converter
have been proposed to address these demanding specifications,
mostly using coupled-inductor topologies [2], [3], [4], [5]. The
present paper introduces a converter topology which deploys
an inductive output clamp to handle the unloading transients.
Section II summarizes the theoretical analysis of the VRM
current step response. Section III discusses considerations in
VRM design. Section IV describes the inductive clamp topology, gives simulated results of its performance, and analyzes
its power dissipation. Finally, the Appendix presents an analysis of the response requirements for a general output clamp.
1 12
multi-phase train
L1
Vin
Vref
L2
Vo
L3
Multi-phase
Controller
R ESR
L4
Co
II. VRM T RANSIENT R ESPONSE
An output voltage transient of a buck VRM (Fig. 1) due to
an increase in the load current I o by Io is illustrated in Fig.2.
The load current step will first cause an output voltage drop of
magnitude Vo;R
Io RESR due to the effective series resistance (RESR ) of the output capacitor 1 . Then, since the controller has non-zero response delay, V o will continue to drop
due to discharge of the output capacitor C o . Let Td be the delay of the controller response, i.e. the time between the instant
a step in the load current has occurred and the resulting update
of the duty cycle by the controller. Then the V o drop due to
Io Td =Co . After
the capacitive discharge will be V o;C
time Td , the controller responds to the load step by increasing
the duty cycle, resulting in inductor current (I L ) increase at a
rate of dIL =dt VL =L, where, assuming saturated controller
Fig. 1. Four-phase VRM.
=
=
=
1 Here, for clarity, we are omitting the initial V drop due to the series induco
tance of the output capacitor. Recent research [6] has developed an advanced
capacitor model for power applications and has indicated that the capacitor
series inductance can be greatly reduced with proper capacitor packaging and
power train layout.
=
response, VL
Vin Vo . Consequently, V o exhibits secondorder behavior and eventually starts to increase. Reference [7]
gives a condition on the total converter inductance L (all phase
inductors in parallel) ensuring that V o starts increasing immediately after IL begins to ramp up,
Lcrit
= o VL=Io
(1)
=
where o RESR Co is the time constant of the output capacitor, which is approximately constant for a particular capacitor
technology.
The unloading current transient (a decrease of I o by Io )
is exactly analogous to the loading transient discussed above,
Vo .
with VL
More discussions of VRM transient response can be found
in [7], [8], [9], [10], [11].
=
∆ Io
Io
dI L /dt
IL
multi-phase train
L1
Vin
Td
Vref
∆ Vo,R
Controller
L < Lcrit
Vo
Vo
L3
Multi-phase
Controller
L = Lcrit
∆ Vo,c
L2
L > Lcrit
R ESR
Co
L4
Fig. 2. Transient response of a buck VRM due to load current step.
TABLE II
Laux
C ONSTRAINTS RESULTING FROM THE SPECIFICATIONS IN TABLE I
assuming ceramic output capacitors with o
Lcrit;load
Lcrit;unload
Rref
= 0:8s
inductive clamp
critical induct. for loading step
critical induct. for unloading step
closed-loop output impedance
88 nH
8 nH
< 0.5 m
Fig. 3. Four-phase VRM with inductive clamp to ground.
III. VRM D ESIGN
From the above analysis it can be seen that provided
L < Lcrit , output impedance control [8] can be used to position the output voltage V o at Vref Rref Io , where Vref is the
reference voltage, and R ref is the targeted closed-loop output
impedance of the converter [7],
inductance for both loading and unloading transients, the converter inductance is constrained by the smaller of L crit;load and
Lcrit;unload . Thus for low conversion ratios L is constrained
by Lcrit;unload resulting in a very low value of L. The relation
for the current ripple in each phase of the converter
ILp p = Vin (1
)
D D=fsw Li ;
for Li
= L1
4
(6)
The desired Rref can be calculated from the parameters in Table I,
Rref < Vo;max = Io;max
(3)
indicates that a low value of L would imply either a high current ripple, resulting in increased conduction losses, or the
need to operate at high switching frequency (f sw ), resulting
in high switching losses [1]. For example, a four-phase buck
converter designed to meet the specifications in Table I with
Li
Lcrit;unload , will have inductor current ripple of 29 A
at 1 MHz. Thus, if the phase inductors are chosen based
on Lcrit;unload , switching frequencies in the 3–5 MHz range
would be required to attain high efficiency.
Returning to (1), for a loading current step, the critical inductance is
IV. VRM T OPOLOGY
Rref
= RESR (1 + Td=o) :
(2)
where Vo;max is the output regulation tolerance, and
Io;max is the maximum load current step (for this calculation we can assume Io;max Io;max ).
Lcrit;load
= o(1
)
D Vin = Io ;
(4)
while for an unloading current step it is
Lcrit;unload
= oDVin =Io:
(5)
Clearly for low conversion ratios, i.e. low values of D,
Lcrit;unload is much smaller than L crit;load . For example, with
D
= there is an order of magnitude difference (see Table
II). By definition L crit is an upper bound for the converter inductance value which allows V o to start increasing immediately
after IL begins to ramp up. If the converter presents the same
= 1 12
=4
A topology which can handle fast current transients at low
conversion ratios and modest steady-state switching frequencies, while maintaining low inductor current ripple, is presented in Fig. 3. It consists of a 4-phase buck converter complemented with an additional low value inductor L aux which
can be switched to ground during large unloading transients.
The inductor values are selected so that,
4
Li = < Lcrit;load
(7)
k Li =4 < Lcrit;unload:
(8)
and
Laux
(a) without clamp
Vo (V)
1.05
1
0.95
0.2
0.4
0.6
0.8
1
1.2
time (ms)
1.4
1.6
1.8
2
1.6
1.8
2
(b) with low−inductance clamp
Vo (V)
1.05
1
0.95
0.2
0.4
0.6
0.8
1
1.2
time (ms)
Fig. 4. Simulation of 4-phase buck converter transient response under a load current step
Thus, for large unloading transients the converter inductance is
lower than its steady state value.
It was calculated in Table II that for the specified VRM requirements, Lcrit;unload
nH is on the order of lead and
PCB trace inductances. Since L crit;unload has a very low
value, some authors have proposed using a resistive output
clamp implemented with a single MOSFET [12].
Parameters for a VRM design based on the considerations and topology discussed above are presented in Table
III. The parameter values indicate that the use of the inductive clamp topology allows for a design operating at a modest fsw = 1MHz, while having a low phase current ripple of
ILp p = 3.2A, and using ceramic output capacitors.
=8
A. VRM Simulation
Fig. 4 shows simulation results for the prototype in Table
III under a 100 A transient. The converter is controlled by a
digital controller [7], [13], with quantization resolution of 11.7
mV (10 bits over 12 V). The controlled quantity (V o0 ) is a combination of V o and the total inductor current, scaled to yield
: m . If Vo0 is close
an output impedance of about R ref
= 0 44 1.4
Io = 100A. Vin = 12V, Vref = 1V, fsw = 1MHz.
to Vref then conventional PID PWM control is used. If V o0 is
more than two quantization bins above V ref , all phase inductors and the clamp inductor (L aux ) are switched to ground to
prevent large overshoot of V o . If, on the other hand, V o0 is more
than four quantization bins below V ref , all phase inductors are
switched to Vin to avoid a large V o undershoot. Quantity V o0 is
sampled at fs;cl
MHz to ensure fast control action. This
control strategy achieves fast saturated response of the converter during large load transients.
=4
As Fig. 4 indicates, if clamping is not used the unloading
transient produces a large overshoot, despite the saturated response of the phase inductors, since L L crit (hereafter Lcrit
implies Lcrit;unload ). When the proposed low-inductance
clamp is added, the unloading overshoot is substantially reduced, becoming comparable in size to the loading undershoot.
The simulation thus confirms the theoretical expectations for
the impact of the critical inductance value on the output voltage regulation.
Vin
L
t=0
Vref
Vin
Io
N
fsw
fs;cl
Td
Li
Laux
Co
RESR
Rref
Nadc
Ndpwm
reference voltage
input voltage
max load current
number of phases
switching frequency
clamp sampling frequency
controller delay
phase inductors
clamp inductor
output capacitance
output capacitor ESR
closed-loop output impedance
1V
12 V
100 A
4
1 MHz
4 MHz
200 ns
290 nH
8 nH
3.2 mF (ceramic)
0.3 m
0.44 m
effective ADC resolution
effective DPWM resolution
10 bit
7 bit (hardware)
+ 4 bit (dither)
iL
Vo
clamp
TABLE III
P ROTOTYPE VRM PARAMETERS
i cl
iC
R ESR
io
Co
Fig. 5. Model of buck converter with clamp for transient analysis.
∆ Io RESR
Vo
io+ iC ( L = Lcrit )
i L ( saturated resp. )
∆ Io
B. Clamp Power Dissipation
The purpose of the clamp in the proposed VRM topology
is to absorb energy from the four phase inductors during fast
unloading transients, and therefore a theoretical understanding
of its behavior and power dissipation is necessary. In order to
ensure proper output impedance regulation during unloading
transients, the energy absorbed by the clamp is approximately
(see Appendix)
Ecl
(L=2
Lcrit
)Io2 ;
for L Lcrit :
Pcl
= (1
)
cl Ecl fload
(10)
where fload is the frequency of the load transients associated
with Ecl . For the design in Table III, assuming a fully dissipative clamp (cl = 0) and full-scale current transients at a
frequency of f load = 5kHz, we obtain
Pcl
1:4 W
1 4 % of the full load power of 100W.
(11)
which is :
V. C ONCLUSION AND F UTURE W ORK
This paper discussed considerations for the design of low
conversion ratio VRM’s. The importance of the critical inductance value for tight regulation of the output voltage was
emphasized. This analysis led to the introduction of a lowinductance clamp topology capable of handling large load transients with tight output regulation at moderate switching frequency, and low current ripple and power dissipation. A simulation illustrating the clamp effect on the output voltage was
presented. Finally, an experimental converter incorporating the
proposed topology is currently under development.
t cl
Fig. 6. Response of the converter in Fig. 5 after an unloading current step of
magnitude Io at time t = 0.
A PPENDIX
C LAMP R ESPONSE A NALYSIS
(9)
assuming saturated response of the main inductors. The inductive clamp is essentially a boost converter transferring energy
from Vo to Vin . Thus, ideally, it can recover all the energy absorbed during an unloading transient by returning it to V in . In
practice this clamping boost converter has efficiency cl , thus
there is a power loss associated with the clamping,
io+ iC ( L > Lcrit )
t=0
A simple model of a buck converter with a clamp is shown
in Fig. 5. For a multi-phase topology, inductor L corresponds
to all the phase inductors in parallel. Fig. 6 shows the behavior
of the converter after an unloading current step of magnitude
Io at time t = 0. We assume that the converter is controlled
to have output impedance equal to the capacitor ESR, thus the
transient produces a V o step of Io RESR . If the inductor has
saturated response, its current after the load step is given by
iL
= Io
Vo t=L;
(12)
where Io is the output current before the load step. Saturated
unloading response of the inductor corresponds to the fastest
rate at which its current can decrease. Meanwhile, the current
flowing into the output capacitor is
iC
where o
= Ioe
t=o ;
= RESR Co, and the load current is
io = Io Io :
(13)
(14)
As illustrated in Fig. 6, if L L crit , the current sunk from the
output node (i o iC ) is always more than the inductor current corresponding to a saturated response. In this case the
inductor current i L can be pulsed by the control circuitry so
that it follows io iC , and thus Vo can indeed follow the step
depicted in the figure. However, if L > L crit , even with saturated response the inductor supplies more current to the output
+
+
450
Finally, note that the above analysis of the energy that a
clamp has to absorb is general, and thus holds for any kind
of clamp (resistive, inductive, etc.).
400
350
Ecl ( µ J )
300
250
200
150
100
50
0
1
2
3
4
5
6
7
L / Lcrit
8
9
10
11
12
R EFERENCES
Fig. 7. Energy that has to be absorbed by the clamp during a full unloading
step.
[1]
[2]
node than the load and the capacitor can sink, thus there is an
“excess” of energy which will result in a V o overshoot as indicated in Fig. 4(a). The role of the output clamp is to absorb
this excess energy during the transient, and either dissipate it,
or recycle it, for example by delivering it back to the converter
input. The current that the clamp has to sink is thus
icl
=iL (io + iC )
=Io(1 e t=o )
Vo t=L; for t 2
(0; tcl)
(15)
( ) = 0:
icl t
(16)
The energy that has to be absorbed by the clamp is then
=
Z tcl
0
()
Vo icl t dt
e tcl =o
) 2VLo t2cl
[8]
(17)
[11]
;
Io L=Vo
(18)
leading to a simple approximate expression for the clamp energy
LIo2 =2
[6]
[9]
which is proportional to the shaded area in Fig. 6. Since the
solution to (16) is transcendental, we cannot obtain an analytic
expression for t cl . We have therefore solved (17) numerically
and plotted the result in Fig. 7 for a range of L=L crit . It should
be noted that for L L crit we have tcl o , thus
Ecl
[5]
[10]
= Vo Iotcl Ioo (1
tcl
[4]
[7]
where tcl is the non-zero solution of
Ecl
[3]
= (L=2 Lcrit)Io2 :
Vo Io o ; for L Lcrit
(19)
[12]
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