Laboratory 7
Bipolar Transistor Biasing and Small Signal Behavior
OBJECTIVES
To learn to bias BJTs in the active region. To learn to use the hybrid π model to perform
small signal analysis of simple transistor circuits.
BACKGROUND
Voltage Divider Bias
Voltage divider bias is the most commonly used technique for biasing transistors in
discrete circuit design. Fig. 7-1 depicts the voltage divider bias circuitry. The voltage
divider formed by resistors R1 and R2 helps set up the DC operating point. Theveninizing
between the transistor base and the ground terminal, we find that the Thevenin voltage
VTH and Thevenin resistance RTH are
VTH = VCC
R2
R1 + R2
Eq. 7-1
RTH = R1 || R2 Eq. 7-2
Fig. 7-1: Voltage divider biasing circuit
Fig. 7-2: Thevenin equivalent of Fig. 7-1
The Thevenin equivalent circuit of Fig. 7-1 is depicted in Fig. 7-2. Knowing that IB =
IE/(β + 1) and applying Kirchoff's voltage law to Fig. 7-2 yields
VTH =
IE
R + VBE + I E RE
β + 1 TH
Eq. 7-3
The emitter current set up in the transistor by the biasing circuitry is thus
IE =
VTH − VBE
R
RE + TH
β +1
Eq. 7-4
To obtain a biasing current IE that is insensitive to variations in temperature and transistor
β, the following conditions must be satisfied:
RE >>
RTH
Eq. 7-5
β +1
VTH >> VBE
Eq. 7-6
Satisfying Eq. 7.5 implies that the voltage drop across RTH is negligible compared to the
sum of the other two terms in Eq. 7.3. This implies that VTH ≈ VBE + I E RE , i.e., VTH is
roughly equal to the potential VB at the base of the transistor. In other words, the base
current drawn from the voltage divider in Fig. 7-1 does not cause the voltage at the midpoint of the divider to drop appreciably from its open circuit value VTH. This can be
accomplished by making the open circuit divider current Idiv = VCC / (R1 + R2) large
compared to the base current IB. Selecting Idiv to lie in the following range accomplishes
this:
0.1I E < I div < I E
Eq. 7-7
The higher Idiv is, the lower the values of R1 and R2 (and RTH), the better Eq. 7-5 is
satisfied, and the more insensitive the bias point is to variations in transistor β. It must
be noted, however, that increasing Idiv leads to higher power dissipation in the voltage
divider and also to lowering of the input resistance between the base and ground
terminals.
The rule-of-thumb given in Eq. 7-7 helps satisfy the condition of Eq. 7.5. Since
VTH ≈ VB , the condition of Eq. 7.6 becomes VB >> VBE. Referring to the base-collector
circuit of Fig. 7-2, we see that making VB large reduces the value of VCB (and thus VCE).
This makes the available VCE voltage swing of the circuit low thus limiting its use as an
amplifier. The following is a rule of thumb for selecting VB:
VTH ≈ VB = VCC / 3 Eq. 7-8
Given a desired bias current IE, Eqs. 7-7 and 7-8 help select values for RE, R1, R2, and RC.
The DC Load Line
The DC load line is a plot of the DC relationship between collector-emitter voltage VCE
and collector current IC. The DC load line is thus the locus of all possible DC operating
points (VCE, IC) for the transistor. Applying KVL to the collector-emitter circuit yields
the DC load line equation. For example, KVL applied to the circuit of Fig. 7-1 yields
VCC = I C RC + VCE + I E RE
Eq. 7-9
To sketch the load line, we will assume that IC = IE. We thus have
VCC ≈ VCE + I C ( RC + RE )
Eq. 7-10
This is a linear relationship between VCE and IC. The load line can be superimposed on a
set of VCE-IC transistor characteristics. The slope of the DC load line is -1/(RC+RE) ⎯ it
intersects the horizontal axis at VCE = VCC and the vertical axis at IC = VCC/(RC + RE).
A transistor amplifier is typically biased near the center of the DC load line. This allows
maximum possible signal swing (without running into cutoff or saturation) when ac
signals are applied to the circuit.
Prelab:
1. Sketch the DC load line of the transistor depicted in Fig. 7-3. Assume that the ac
signal vi = 0. What value of the voltage source Vbb will provide a DC operating point
VCE = 5V, IC = 1mA? (use the β value measured for your transistor). What is the
value of the transistor base current?
Fig.7 -3: Circuit to illustrate transistor operation as an amplifier
2. Assume that the sinusoidal ac source vi is present and has small enough amplitude to
allow linear operation of the circuit. Draw the small signal equivalent circuit of the
circuit of Fig. 7-3. Use the DC operating point of part 1 to determine the parameters
of the hybrid π small signal transistor model. Use the equivalent circuit to determine
the small signal voltage gain of the circuit (ratio of the output voltage vo to the input
voltage vi).
3. Use PSpice to simulate the circuit of Fig. 7-3 with the value of Vbb determined in part
1, and vi having amplitude 0.1V. Obtain plots of the voltages at the base and the
collector of the transistor. Measure the small signal voltage gain of the transistor.
Compare with the theoretical gain determined in part 2.
4. The supply voltage in Fig. 7-1 is VCC = 10V. Bias the circuit to establish a collector
current IC = 1mA. Design your circuit such that the bias point is relatively insensitive
to changes in the β value of the transistor (use the rules-of-thumb of Eqs. 7.7 and 7.8).
Specify values for R1, R2, RC, and RE. Also identify the operating point (VCE, IC) of
your circuit. Sketch the DC load line of the transistor and mark the operating point
on the load line. How much ac voltage swing on VCE is possible without distortion?
5. Use PSpice to simulate your design of part 4 (use a Q2N2222 part for the simulation).
What operating point does the simulation yield? Compare with your calculated value
from part 4.
IN LAB
1. Construct the circuit of Fig. 7-3 (use a 2N2222A transistor from your lab kit). Use the
Wavetek signal generator in place of both Vbb and vi (a DC offset will be used to
generate Vbb). First make vi as small as possible by turning the amplitude knob to the
lowest setting and by leaving the attenuator knob out. Set the frequency of the signal
generator to 1kHz. Now adjust the DC offset until VCE reads 5V on the DMM.
Measure the collector current and record the bias point. Measure Vbb using the DMM
and compare against the value calculated in the prelab. Replace the transistor by
another 2N2222A and record the bias point again. Comment on the changes in VCE
and IC due to the exchange of the transistor.
2. View the Wavetek output on the scope. Adjust the amplitude of the Wavetek until
you obtain a 0.1V amplitude (0.2V p-p) sinusoid riding on the DC level Vbb. Obtain a
printout of the oscilloscope screen displaying both the Wavetek output and the output
signal vo of the amplifier. Measure the small signal voltage gain of the amplifier and
compare with the theoretical value calculated in the prelab.
3. Construct the transistor biasing circuit of Fig. 7-1 with the resistance values designed
in the prelab. Measure the operating point (VCE, IC) of the transistor and compare
with the design values. Replace the transistor by another 2N2222A and measure the
operating point again. Comment on the stability of the operating point of this biasing
circuit relative to that of Fig. 7-3.
4. Set the DC offset of the Wavetek signal generator to zero. AC couple the Wavetek to
the base of the circuit of Fig. 7-1 using a 100μF capacitor. Obtain a printout of the
oscilloscope screen containing the waveform of the Wavetek output and the
waveform at the collector of the transistor. What is the voltage gain of the amplifier?
Measure the largest possible ac signal swing at the collector of the transistor with no
distortion. Compare this with your prelab prediction.